Design of Multi-Time Programmable Intellectual Property with Built-In Error Correction Code Function Based on Bipolar–CMOS–DMOS Process
Round 1
Reviewer 1 Report
Comments and Suggestions for Authors1. Fig.3(b) is not readable, it's recommended to use drawing tools instead of screenshots.
2. the size of MN0, MN1 and CC shoud be listed, which will give readers an important quantitative impression on the circuit design.
3. the MTP cell using the NCAP type coupling capacitor is only 0.44% smaller than the conventional NMOS transistor, It would be better to further explain the advantages of the new structure.
4. why choose 7.75v and -7.75v for VPP and VNN respectively, are there any design considerations or theoretical derivations involved?
5. In table 2, it's stated that the Endurance is 1K and Data Retention is 10 Years@150C, however, there are no data evidence in the manuscript to support.
6. Since the fabrication has been carried out, a chip photo should be given in Figure 16 along with the layout.
7. why the VNN measurement result is only -4.5V, it should be clarified further.
Author Response
Comment 1: Fig.3(b) is not readable, it's recommended to use drawing tools instead of screenshots.
Response 1: Fig. 3(b) was not able to maintain the original image when using drawing tools, so I changed the color of the image to make it easier to view.
Comment 2: the size of MN0, MN1 and CC should be listed, which will give readers an important quantitative impression on the circuit design.
Response 2: The sizes of MN0, MN1 and CC are included in Fig. 1.
Comment 3: the MTP cell using the NCAP type coupling capacitor is only 0.44% smaller than the conventional NMOS transistor, It would be better to further explain the advantages of the new structure.
Response 3: The manuscript is modified as follows:.
In this paper, as a result of comparing the layout size of the coupling capacitor of NMOS transistor type and MTP cell using coupling capacitor of NCAP type in DBHiTeK 180nm BCD process, the layout area of the MTP cell using the coupling capacitor of the NCAP type is about 0.44% smaller, and the MTP cell using the NCAP in Fig. 3 that has completed the electrical characteristic verification in the DBHiTeK process is used to design an MTP IP with built-in ECC function.
Comment 4: why choose 7.75v and -7.75v for VPP and VNN respectively, are there any design considerations or theoretical derivations involved?
Response 4: The reason is added in the manuscript as follows:
The VPP voltage of 7.75 V and the VNN voltage of -7.75 V in program mode and erase mode are the voltages to satisfy the conditions for electron injection or electron ejection to occur in the floating gate (FG) by FN tunneling when an electric field of 10 MV/cm or more is applied to the gate oxide of MN1, which is the SENSE_TG transistor shown in Fig. 1.
Comment 5: In table 2, it's stated that the Endurance is 1K and Data Retention is 10 Years@150C, however, there are no data evidence in the manuscript to support.
Response 5: References for endurance and data retention are added.
Comment 6: Since the fabrication has been carried out, a chip photo should be given in Figure 16 along with the layout.
Response 6: Fab-out wafers are stored in DBHiTek. DBHiTek is a foundry company, so we were told that we could not take photos in-house for technical security reasons. As the authors of this paper, it would be more complete to add it as a reviewer's comment, but we regret that we are unable to attach a wafer die photo due to the Foundry's security policy.
Comment 7: why the VNN measurement result is only -4.5V, it should be clarified further.
Response 7: The reason is added as follows:
In this paper, it is speculated that the VNN measurement voltage is -7.75 V and is clamped to -4.5 V as the target voltage, well junction BV, or body node voltage of the isolated NMOS transistor floats momentarily, and the cause of the defect of the VNN clamping is currently being analyzed.
Reviewer 2 Report
Comments and Suggestions for AuthorsA 4Kb MTP IP with built-in ECC function is designed, using extended Hamming code for single error correction and double error detection. In this paper, a new test algorithm is proposed to test whether the ECC function works properly in the MTP IP of the built-in ECC function, and confirms it by using a logic tester. A new technology to reduce the change of ripple voltage is also proposed. The quality of the paper is very high, and some minor opinions are as follows:
1) In the introduction, the author needs to quote more recently published papers to better explain the innovations of the papers and compare them with other people's articles.
2) In the circuit design part, the author should explain the basic circuit in more detail, and some simple formula parameters should also be explained as the formula (1).
3) Try not to display the tables in the article across pages, such as tables 1, 3, 9 and 4.
4) In the simulation and test part, Figure 17 is not clear at first. Secondly, can the author give more simulation results? And can you give a comparison with other people's results?
5) How is the test environment built? The author has no streamer. How to test it?
6) Why not use a differential amplifier circuit with PMOS differential input pair? What are the advantages of folding cascode CMOS OP-AMP?
7) What is the role of the ring oscillator circuit in the text?
Comments on the Quality of English Language
The English could be improved.
Author Response
A 4Kb MTP IP with built-in ECC function is designed, using extended Hamming code for single error correction and double error detection. In this paper, a new test algorithm is proposed to test whether the ECC function works properly in the MTP IP of the built-in ECC function, and confirms it by using a logic tester. A new technology to reduce the change of ripple voltage is also proposed. The quality of the paper is very high, and some minor opinions are as follows:
Comment 1: In the introduction, the author needs to quote more recently published papers to better explain the innovations of the papers and compare them with other people's articles.
Response 1: References for the recently published papers are added in the introduction.
Comment 2: In the circuit design part, the author should explain the basic circuit in more detail, and some simple formula parameters should also be explained as the formula (1).
Response 2: More description is added in the manuscript.
Comment 3: Try not to display the tables in the article across pages, such as tables 1, 3, 9 and 4.
Response 3: The manuscript under review is revised by the journal committee, so I would like to keep them as they are for readability.
Comment 4: In the simulation and test part, Figure 17 is not clear at first. Secondly, can the author give more simulation results? And can you give a comparison with other people's results?
Response 4: Fig. 17 has been revised to make it easier to read by dividing it into Fig. 17(a) and Fig. 17(b). Most of the simulations and measurements to illustrate the techniques proposed in this paper have been included, so no further additions have been made. Comparison of results with other papers is described in the manuscript as follows:
If the VNN had been -7.75 V instead of -4.5 V in erase mode, the VTE measurement result in Fig. 17 would have been less than -1.5 V, considering that the coupling ratio of the MTP cell in Figure 1 is 0.9. However, the measurement result of the VNN voltage in erase mode is -4.5V, which limits the comparison with the results of other papers. On the other hand, this research team speculates that the VNN measurement voltage is -7.75 V and is clamped to -4.5 V as the target voltage, well junction BV, or body node voltage of the isolated NMOS transistor floats momentarily, and they are currently analyzing the cause of the defect in clamping to -4.5 V.
Comment 5: How is the test environment built? The author has no streamer. How to test it?
Response 5: The following has been added from the manuscript.
Test of wafers is done using Teradyne Catalyst logic tester equipment. Fig. 17 shows the cumulative cell numbers with respect to VTE and VTP, which are the threshold voltages of MTP cells
Comment 6: Why not use a differential amplifier circuit with PMOS differential input pair? What are the advantages of folding cascode CMOS OP-AMP?
Response 6: The differential amplifier with PMOS differential input pair was not used because of the problem as described in the manuscript, and folded cascode CMOS OP-AMP was used. Some of the contents have been modified from the manuscript for better understanding.
Comment 7: What is the role of the ring oscillator circuit in the text?
Response 7: The following has been added from the manuscript.
In general, the ring oscillator circuit used in the DC-DC converter of MTP IP is used to create the pumping clock signal used in the positive charge pump circuit (VPP charge pump circuit) and the negative charge pump circuits (VNN and VNNL charge pump circuits). During the time that the ring oscillator circuit is oscillating, the pumping clocks in the charge pumping circuits are clocking, and the VPP charge pump circuit is pumping positive charge to the VPP output node, and the VNN and VNNL charge pumping circuits are negative charge pumping to the VNN and VNNL output nodes, and the target voltage is exceeded.
Reviewer 3 Report
Comments and Suggestions for AuthorsThe paper appears as a contribution to MTP memory design with ECC for automotive applications, is very technical, and proposes an innovative circuit (IP) using a smaller layout and reduced ripple voltage, with extended Hamming codes for error correction.
Here follow some comments:
Any paper must be exhaustive so please, at least:
- confirm somewhere in the text that MTP stands for "Multi-Time Programmable"
- confirm somewhere in the text that MTP stands for BCD (Bipolar-CMOS-DMOS)
Also, the authors should mention whether the simulations are performed pre- or post-layout to include the parasitics.
Moreover, authors should describe how their IP can adapt to different technologies and technology nodes. Potential limitations due to the 180nm process ?
As usual in these types of papers, scalability should be addressed somehow.
Author Response
The paper appears as a contribution to MTP memory design with ECC for automotive applications, is very technical, and proposes an innovative circuit (IP) using a smaller layout and reduced ripple voltage, with extended Hamming codes for error correction. Here follow some comments:
Comment 1: Any paper must be exhaustive so please, at least:
- confirm somewhere in the text that MTP stands for "Multi-Time Programmable"
- confirm somewhere in the text that MTP stands for BCD (Bipolar-CMOS-DMOS)
Response 1: Modified as you required.
Comment 2: Also, the authors should mention whether the simulations are performed pre- or post-layout to include the parasitics.
Response 2: This is the result of pre-layout simulation, and the content is added from the manuscript.
Comment 3. Moreover, authors should describe how their IP can adapt to different technologies
and technology nodes. Potential limitations due to the 180nm process ? As usual in these types of papers, scalability should be addressed somehow.
Response 3. The content is added from the manuscript.
The MTP cell used in this paper has excellent scalability characteristics as it can be applied to all technology nodes provided with 5V MOS devices, including the 180nm BCD process.
Round 2
Reviewer 1 Report
Comments and Suggestions for AuthorsThe endurance issue is very important for MTP cell. A simple way to check the endurance is to do continous program-erase cycle, for example 1K cyces, and then inspect the changes in the I-V curve or VT. If possible, please provide the endurance testing results. Or you can just state that the endurance and the retention issues will be studied in the future work.
Author Response
Comment: The endurance issue is very important for MTP cell. A simple way to check the endurance is to do continous program-erase cycle, for example 1K cycles, and then inspect the changes in the I-V curve or VT. If possible, please provide the endurance testing results. Or you can just state that the endurance and the retention issues will be studied in the future work.
Response: We don't have an MTP cell TEG (Test Element Group) module, so we can't do endurance testing on MTP cells. Instead, after the defect analysis of the VNN in erase mode is completed, endurance and retention tests are planned. Therefore, we added the following content marked in blue from the manuscript.
For MTP IP, endurance and retention tests are important [18]. If the cause of the defective clamping of VNN to -4.5V in erase mode is found and the problem of VNN clamping to -4.5V on the MTP test chip is solved, we plan to proceed with endurance test and retention test.
Reviewer 2 Report
Comments and Suggestions for AuthorsThe authors have made revisions to the paper and it is now eligible for acceptance and publication. However, there are still too few references to recent published papers in the reference section. It is suggested that the authors should include more recent and relevant literature citations and reviews.
Author Response
Comment: The authors have made revisions to the paper and it is now eligible for acceptance and publication. However, there are still too few references to recent published papers in the reference section. It is suggested that the authors should include more recent and relevant literature citations and reviews.
Response: We included two recent papers related to the MTP paper marked in blue.
