Statistical Signal Integrity Analysis on DFE with Nonideal Latch Model

Abstract

This paper introduces the nonideal latch model for the decision feedback equalizer (DFE) for statistical signal integrity (SI) analysis. The DFE equalizes inter-symbol-interference (ISI) noise from the channel in the time domain. The nonideal DFE may propagate an error due to the ISI noise, and the nonideal latch in the DFE may also generate a bit error in the DFE operation. The dynamic latch in the slicer of the DFE circuit amplifies the received signal in a recursive manner. During the amplification, the voltage difference ebetween the signal and the threshold voltage may be less amplified when the amplification time is not enough. Thus, the nonideal dynamic latch is another error source in the DFE operation. In order to reflect the effect of the nonideal latch, the gray zone is defined based on the transfer function of the dynamic latch with iterations. In other words, the gray zone is approximated with the Gaussian distribution and reflected into the statistical eye diagram. As a result of the nonideal latch model, the statistical eye diagram has blurred probability density functions (PDFs).

1. Introduction

The consumer electronics market has continuously required more functionalities from makers. The more functionalities incorporated with the electrical devices, the more data have to be transmitted and received over physical interconnects. The interconnects include connectors, cables, printed circuit boards (PCBs), and packages. Data transmission at a low speed is not problematic, which is close to an ideal node. When the data rate increases enough, the above interconnects become distributed models [1]. Each block of the distributed model includes a parasitic resistance, inductance, and capacitance [2]. Thus, cascaded models represent the interconnects in terms of the electrical behavior. Generally, an interconnect, which can be expressed as the distributed models, has the frequency response of a low-pass filter (LPF). In other words, the interconnect has a finite bandwidth in the frequency domain. The finite bandwidth is equivalent to electrical degradations such as dispersion, insertion loss, and reflection loss in the time domain. Likewise, the above loss is represented as an RC delay in the time domain. The RC delay causes the transmitted waveforms to be delayed, widened, and attenuated. Signal integrity (SI) analysis investigates the above electrical losses in electromagnetic compatibility (EMC) [3,4,5].

The eye diagram is a critical SI metric that shows the electrical performance in a graphical manner in the time domain [6,7]. The eye diagram is obtained by overlapping the received waveforms at every unit interval (UI). As a result of overlapping the waveforms, the accumulated waveforms can show how reliable the received ONEs and ZEROs are. The reliability corresponds to how far apart the distribution for ONEs are from the distribution for ZEROs in the voltage. The parameter that shows the distance between the distributions is eye height (EH), as shown in Figure 1. Likewise, in the sampling time, eye width (EW) shows the reliability of the received waveforms. The transmitted signal is a rectangular pulse with an amplitude or none depending on the data bit. When the rectangular pulse has an amplitude, the pulse can be separated into transition and hold areas. Typically, the transition area corresponds to the rising and falling edges of the rectangular pulse. The hold area is the timing interval with a constant non-zero voltage or zero voltage. The distance between the distribution of the rising edge and the distribution for the falling edges corresponds to the EW. The ideal EH value is the voltage difference between HIGH and LOW, and the ideal EW value is 1 UI, which is a reciprocal of the given data rate. If the above eye diagram parameters are much different from the ideal case, then the corresponding eye diagram is interpreted as significantly lossy in terms of electrical performances. Hence, the channel has to be designed for the eye diagram to have eye parameters that are close to the ideal values.

The above eye parameters provide the reliability of the data transmission in the voltage and sampling time. In other words, the accuracy of the eye parameters directly relates to the reliability analysis on the data transmission. The characteristic of time-consuming of the eye diagram may make the SI analysis inaccurate. If the number of waveforms is not enough to accurately evaluate the EW and EH values, then the obtained EH and EW values are not reliable. In other words, the calculated EW and EH values can be larger than the real values in some cases. Thus, the channel can be underestimated in the case of a small number of test bits. To avoid the inaccuracy, the number of transmitted bits should be greater than a specific number. The specific number for accurate SI analysis is determined by the data source and electrical performance of the channel. The high-speed channels have been evaluated with as long a test bit as possible, because the accurate criterion for the bit length is unknown.

To avoid the above inefficiency, eye diagram estimation was proposed [8]. The method estimates the EW and EH values with a small portion of channel information. The information used in the estimation is a channel response such as a single-bit response (SBR) and double-edge response (DER). The SBR is the channel output when a single bit is transmitted over the channel; the DER is the channel response for the bit transitions, i.e., high-to-low state and low-to-high state. The estimation methods include peak distortion analysis (PDA) and statistical methods. PDA calculates the EH and EW values for the channel, which are the most critical values of the eye diagram. In other words, PDA only provides the criterion as to whether the given channel supports the reliable data transmission. Unlike PDA, the statistical method calculates the probability distribution functions (PDFs) of the eye diagram, which is all the information of the eye diagram. Therefore, the obtained PDFs show how reliable the channel under evaluation is.

Because the statistical method provides more information compared to the PDA method, it has more applications in other areas such as bit-error rate (BER) analysis [9] and system level. High-speed systems include features to improve the SI and BER performances. Those features include equalizers, error-correction codes (ECCs), scrambling, and multi-level signaling. The above features either directly or indirectly affect the eye diagram; thus, system-level statistical eye diagrams were introduced recently.

The shmoo plot is widely used in semiconductor industry [10,11]. The shmoo plot intuitively shows the system BER performances depending on system conditions such as operation voltage, clock speed, and sampling time. In other words, the shmoo plot may have various x-axes and y-axes depending on which factor is under test. The threshold voltage is one of the typical y-axis parameters in the shmoo plot. In that case, the shmoo plot is equivalent to the BER eye diagram, which can be converted from the statistical eye diagram. The statistical eye diagram provides the PDFs depending on the sampling time and the voltages. The BER eye diagram can be obtained by applying the cumulative summation to the positive and negative directions. Therefore, the statistical eye diagram is also beneficial in terms of the system analysis.

This paper is organized as follows. Section 2 introduces the decision feedback equalizer (DFE) in detail. The components of the DFE and the DFE operation with the latch are introduced. Also, the reason why the dynamic latch is problematic in the statistical eye diagram is introduced to propose the nonideal latch model. In Section 3, the equations for the conventional statistical eye diagram are explained before applying the proposed nonideal latch model. The proposed latch model is reflected in Section 4, and the resultant statistical eye diagrams depending on the threshold voltage are shown to identify the effect of the nonideal latch.

2. Introduction to DFE

Equalizers compensate for the above electrical losses in the time and frequency domains. In other words, the equalizers can make the eye diagram parameters closer to the ideal values. Because the equalizer makes the channel performance equal in the frequency domain, it is named after the behavior. The continuous time linear equalizer (CTLE) either boosts the high-frequency energies or attenuates the low-frequency energies for a flat frequency response. As a channel has a flatter frequency response, the signals are transmitted with less electric degradation. In other words, the CTLE mitigates the uncertainty during the data transmission. The CTLEs are categorized into either passive or active type depending on whether it consumes power or not. The passive CTLE typically attenuates the signals in a low-frequency range, and the active CTLE amplifies signals in a higher frequency range.

A DFE is an active time-domain equalizer to mitigate the inter-symbol-interference (ISI) noise [12,13,14]. As the data rate increases, the amount of ISI noise also increases. Thus, the DFE is an essential part in state-of-the-art high-speed systems [15]. Especially, recent memory applications include the DFE to improve the SI performance [16]. The DFE consists of a slicer, a feedback path, and a summer. The slicer compares the received signal to a threshold voltage to make a bit decision. If the received signal is greater than a threshold voltage, then the output of the slicer would be ONE. If not, the output would be ZERO. After that, the decided bit is propagated to a former stage over the feedback path. The former stage is a summer circuit to add the feedback signal to the received signal. The summed signal is applied to the slicer as an input. The above procedure is recursively repeated, which results in an equalization over the channel.

The typical DFE has two inputs: the received signal and the threshold voltage. A slicer in the DFE circuits consists of multiple stages to successfully compare the received signals to the threshold voltage, as can be seen in Figure 2. The first stage is generally a pre-amplifier to amplify the voltage difference between the two inputs before making a bit decision. In the next stage, the comparator compares which signal is greater and decides the output logic afterward.

Figure 3 shows the details of the comparator in the DFE circuit. A comparator typically includes a dynamic latch and S-R latch. The dynamic latch is a cross-coupled inverter that amplifies the voltage with the output of the other inverter. The S-R latch is to hold the logic from the dynamic latch and to deliver the logic to the next stage. The DFE operates recursively; thus, the output of the S-R latch is propagated to the summer by the feedback loop. Finally, the summer fulfills a weighted summation with the received signal and the previous bits to equalize the expected ISI noise by the previous channels and parasitic RC delay from the channel.

The DFE has fixed values for the tap coefficients, which are equivalent to how much the current waveform is attenuated if needed. The coefficients are figured out from the training with the given channel. Generally, the tap coefficients are proportional to how lossy the given channel is because the amount of RC delay is proportional to the parasitic resistance and capacitance. If the channel has a significant amount of RC delay, then the resultant amount of the ISI noise is also significant. Therefore, the DFE has a controllable equalization performance for the given channel to improve the SI performances.

The above controllability is achieved by training between the Tx and Rx ends. The training is to find the optimal DFE’s tap coefficients, which correspond to the maximum EW and EH values. The training takes a long time to sweep the coefficients for each tap. High-speed systems have different training processes. However, the DFE training is generally executed after the timing training between the Tx and Rx ends. In other words, the DFE training is carried out under the optimal timing condition. Whether the sampling timing is optimal or not affects the DFE operation. Because the output of an inverter is the input of the other inverter, the speed of the dynamic latch is proportional to the voltage gap between the inputs of the comparator. Thus, the optimal sampling timing provides an ideal condition to the dynamic latch during the DFE training.

The inputs are the input voltage $V_{in}$ and the reference voltage $V_{ref}$ from Figure 3. In the case of optimal timing, the input voltage is obtained from the maximum peak of the bit responses. The amplitude is certain compared to other sampling timings. The certainty means it is large enough to make a decision. Figure 4 shows how the voltage transfer behavior of the dynamic latch changes depending on the iteration. As the dynamic latch operates recursively, the dynamic latch becomes ideal, which means that the dynamic latch has an abrupt curve near the threshold voltage. If the input voltage is not large enough compared to the rail voltages, such as VDD or 0 V, then the dynamic latch has to operate recursively until the output voltage converges to one of the rail voltages.

A complementary metal-oxide semiconductor (CMOS) consists of N-type MOS (NMOS) and P-type MOS (PMOS). The NMOS and PMOS have process, voltage, and temperature (PVT) variations during the fabrication process. The PVT variation affects the CMOS performance and causes a variation depending on the fabricated CMOSs. Typically, the PVT variation is represented by a skew model such as a TT (typical–typical), ST (slow–typical), and SF (slow–fast). Hence, the dynamic latch, which is equivalent to the cross-coupled CMOS, is also affected by the PVT variation. The transfer function of the dynamic latch is determined by the characteristics of the P/NMOS and the PVT variation. While characterizing the following transfer function of the dynamic latch, the above effects are already reflected in the iterations. In other words, even though the PVT variation may affect the statistical eye diagram, the proposed method still works in the same manner with the different transfer function of the dynamic latch.

The above iteration affects the shmoo plot when the shmoo plot has the threshold voltage in y-axis. Especially, the transition area is affected compared to the hold area. Because the required iteration number for the convergence is inversely proportional to the voltage gap between the received voltage and the threshold voltage. Figure 5 shows the voltage difference depending on the iteration. Therefore, the effect of the dynamic latch on the shmoo plot should be considered. The nonideal latch model introduced in this paper represents the above effect in the shmoo plot. As we discussed earlier, the shmoo plot is equal to the BER eye diagram when the y-axis is the threshold voltage and the x-axis is the sampling time. Therefore, this paper introduces the statistical eye diagram with the nonideal latch model to achieve the accurate shmoo plot.

Figure 6 shows the zoomed-in voltage gap for the inverter in forward. Although the dynamic latch has a large gain, it may have a smaller gain than what it should have depending on the voltage gap. Thus, the amplification speed of the dynamic latch heavily depends on the received voltage compared to the threshold voltage. When the dynamic latch operates at low speed, the RS latch may catch a wrong value. Therefore, the DFE may fail to equalize the ISI noise due to the speed of the dynamic latch.

3. Statistical Model for the DFE

The statistical SI analysis on the DFE was studied to achieve an efficient and accurate SI evaluation. Ref. [17] introduced the statistical approach with the DFE effect on the statistical eye diagram. Ref. [18] proposed the statistical shmoo plot with the nonideal and ideal DFEs. When the statistical shmoo plot has the y-axis of the threshold voltage, the shmoo plot has the threshold voltage-dependent BER performance with the DFE, because the DFE also has the threshold voltage as an input. Before converting to the shmoo plot, the statistical eye diagram without the DFE is obtained as follows [16]:

$$y\left(t\right)=\left\{\begin{array}{c}{y}_{-N}\left(t\right),t\le t_X\\ y_0\left(t\right),t_X<t\le t_X+1UI\\ y_N\left(t\right),t>t_X+1UI\end{array}\right..$$

(1)

The SBR is divided into the pre-, post-, and main cursors, and the amplitude PDF is defined based on the above cursors:

$$g_N\left(\alpha ,t_S\right)=P\left(X_N=0\right)\cdot \delta \left(\alpha \right)+P\left(X_N=1\right)\cdot \delta \left(\alpha -y_N\left(t_S\right)\right).$$

(2)

The consecutive convolutions are applied to the pre- and post-cursors, respectively:

$$g_{+}\left(\alpha ,t_S\right)={⊛}_{N=1}^{\infty }{g}_N\left(\alpha ,t_S\right),$$

(3)

$$g_{-}\left(\alpha ,t_S\right)={⊛}_{N=-1}^{-\infty }{g}_N\left(\alpha ,t_S\right),\mathrm{and}$$

(4)

$$g_{\pm }\left(\alpha ,t_S\right)=g_{+}\left(\alpha ,t_S\right)⊛g_{-}\left(\alpha ,t_S\right).$$

(5)

Equation (5) is the resultant amplitude PDF from the convolution between the amplitude PDFs for the pre- and post-cursors. Then, a single column of the statistical eye diagram is obtained by applying the following convolution:

$$g\left(\alpha ,t_S\right)=g_{\pm }\left(\alpha ,t_S\right)+g_{\pm }\left(\alpha -y_0\left(t_S\right),t_S\right).$$

(6)

Equation (6) is swept with the sampling time from 0 to 1 UI until the statistical eye diagram is obtained. Hence, the BER eye diagram is obtained by applying an integral from the threshold voltage to infinity or from negative infinity to the threshold voltage:

$$E_0\left(V_{th},t_S\right)={\int }_{\alpha =V_{th}}^{\infty }{g}_{\pm }\left(a,t_S\right)d\alpha ,$$

(7)

$$E_1\left(V_{th},t_S\right)={\int }_{\alpha =-\infty }^{V_{th}}{g}_{\pm }\left(a-y_0\left(t_S\right),t_S\right)d\alpha .$$

(8)

The statistical eye diagram with the ideal DFE is obtained with the equalized SBR [16]. The ideal DFE makes the correct bit decision; thus, the RC delay is always successfully attenuated by the DFE. Therefore, the effect of the DFE can be integrated by equalizing the SBR without any change to the statistical method. As a result, the statistical eye diagram has the equalized SBR:

$$y\left(t\right)={\mathcal{F}}^{-1}\left\{\mathcal{F}\left(rect\left({\displaystyle \frac{t-0.5\cdot UI}{UI}}\right)\right)\cdot S_{21}\left(f\right)\right\},$$

(9)

$$y_{eqzd}\left(t\right)=w_1\cdot y\left(t-1\cdot UI\right)+w_2\cdot y\left(t-2\cdot UI\right)+\cdots .$$

(10)

Equations (9) and (10) show the SBR and equalized SBR, respectively. The statistical eye diagram has the input with (9) without the DFE; further, the ideal DFE is considered with (10). The equalization of the ideal DFE is straightforward and simple to implement in the statistical eye diagram.

The nonideal DFE may have distorted amplitude PDFs by the wrong previous bits. Thus, the equalized SBR has an additional parameter of the threshold voltage:

$$y_{eqzd}\left(t,V_{th}\right)=w_1\left(t_S,V_{th}\right)\cdot y\left(t-1\cdot UI\right)+w_2\left(t_S,V_{th}\right)\cdot y\left(t-2\cdot UI\right)+\cdots ,$$

(11)

$$\cdots where{w}_N\left(t_S,V_{th}\right)=y\left(t_S\right)\cdot rect\left({\displaystyle \frac{t_S-\left(t_X+\left(N-1\right)+0.5\cdot UI\right)}{UI}}\right).$$

(12)

Then, the probability that the slicer makes the bit decision as ONE is as follows:

$$P\left(\widetilde{X_0}=1\right)=P\left(y_o\left(t\right)>V_{th}\right).$$

(13)

The nonideal DFE with 1-tap has the following amplitude PDF consisting of weighted delta functions:

$$g_0\left(\alpha ,t_S,V_{th}\right)=P\left(\widetilde{X_{-1}}=0\right)\cdot \delta \left(\alpha -y_0\left(t_S\right)\right)+P\left(\widetilde{X_{-1}}=1\right)\cdot \delta \left(\alpha -\left(y_0\left(t_S\right)-w_1\left(t_S,V_{th}\right)\right)\right)$$

(14)

4. Proposed Nonideal Latch Model

Equations (9)–(14) are under the assumption that the latch operates ideally, which means that the latch has no delay until it amplifies the received voltage to the rail voltage. However, as discussed earlier, the low-speed amplification at the dynamic latch may affect the accuracy of the bit decision in the R-S latch. The non-saturated signal to the rail voltages is unknown to the summer. Thus, the DFE’s taps are not fully applied to the received signal—that is, the DFE operates differently than intended. Therefore, the probability of the error propagation in the DFE becomes higher due to the nonideal latch.

In the DFE structures, the ONE’s probability is given by

$$P\left(X=1\right)={\int }_{V_{th}}^{\infty }f\left(\alpha \right)d\alpha$$

(15)

where $f\left(\alpha \right)$ is the PDF in the voltage domain.

Equation (15) is applied to the ISI’s PDF to estimate whether the DFE operates for the transmitted ZEROs. Although ZERO was transmitted, the slicer may perceive the signal as ONE if the signal is greater than the threshold voltage. The above case occurs by the nonideal DFE due to the significant amount of ISI noise. Likewise, the nonideal latch may be misleading when the signal is close to the threshold voltage, as introduced above.

In order to evaluate the effect of the nonideal latch in the DFE, the gray zone in Figure 6 is converted to a random process:

$$L\left(\alpha \right)=\mathcal{N}\left(\mu ,{\sigma }^2\right)={\displaystyle \frac{1}{\sqrt{2\pi {\sigma }^2}}}{e}^{-{\displaystyle \frac{{\left(\alpha -{\mu }_{\alpha }\right)}^2}{2{\sigma }^2}}}$$

(16)

The above Gaussian distribution is determined by the electrical characteristics of the DFE circuit. The threshold voltage determines the mean and the area of the gray zone determines the standard variation in Equation (16). Thus, the above random process for the gray zone is applied to Equation (15):

$$\tilde{P}\left(X=1\right)\triangleq P\left(X=1\right)+L\left(\alpha \right).$$

(17)

Figure 7 shows the main cursors with the threshold voltage to represent the gray zone by the latch model. When the bit decision is made at around the threshold voltage, the slicer has a gray zone, making it hard to clearly distinguish the logic level. The gray zone is applied to the ISI’s PDF and the ONE’s PDF; thus, the nonideal DFE with the nonideal latch model is integrated into the statistical eye diagram.

The statistical eye diagrams for the nonideal DFE with the nonideal latch are shown in Figure 8. The nonideal latch model significantly affects the transition area more than the hold area in the statistical eye diagrams. Also, as the threshold voltage moves towards the ground voltage, the DFE becomes more erroneous. Especially, the transition area is significantly distorted when the threshold voltage is close to ZERO.

5. Discussion

This paper introduces the gray zone to reflect the effect of the nonideal latch on the eye diagram. The gray zone is converted to the random process, which is the Gaussian distribution on the voltage domain. Previous research on the nonideal DFE on the statistical eye diagram was introduced with the modified DFE equations [16]. The introduced nonideal DFE represents the error propagation in the DFE, which is a significant problem in the SI analysis. The error propagation occurs recursively due to the principle of the DFE equalization; thus, the statistical eye diagram had to deal with the problem during the calculation.

The ISI noise and the nonideal latch model are dependent on the statistical eye diagram. The degradation by the ISI is determined by an insertion loss of a channel. The nonideal latch is determined by the dynamic latch and a feedback loop of the DFE circuit and the corresponding layout. By definition, the ISI and the nonideal latch seem independent. Because the dynamic latch needs time to amplify the given waveform, the amplification time is proportional to the amount of ISI noise. However, the above correlation is only effective for the first iteration of the dynamic latch. In other words, as the dynamic latch operates iteratively, the correlation between the ISI and the nonideal latch model becomes independent in terms of the PDF.

Another recursive problem in the DFE is the dynamic latch operation in the DFE. The introduced nonideal latch model represents the amplification of the dynamic latch in the slicer for the bit decision. The DFE equalization operation is based on the previous bits from the slicer. Hence, to achieve an accurate SI evaluation of the DFE, the slicer is also strictly investigated. The difference by introducing the nonideal latch model is distinguishable by comparing to the results in [18]. The nonideal DFE truncates the statistical eye diagram depending on the threshold voltage. The relationship between the main cursors and the threshold voltage determines which period in the sampling time is attenuated. The introduced latch model herein adds the uncertainty onto the statistical eye diagram with the Gaussian distribution.

The uncertainty from the nonideal latch model is determined by the characteristics of the CMOS. If the CMOS switches fast enough, then the gray zone will shrink dramatically. In other words, as the data rate increases, the nonideal latch model becomes important in the statistical SI analysis on the practical DFE.

The BER is another important metric in the high-speed system design. The statistical eye diagram is converted to the BER by cumulative summation to the given sampling time or threshold voltage. Thus, the obtained statistical eye diagram with the nonideal latch model is converted to the BER with the above procedure. The effect of the nonideal latch on the BER is hard to evaluate because the nonideal latch model represents the nonideality with a probability distribution function. Instead, the effect of the nonideal latch on the BER is identified by comparison of the statistical eye diagram depending on the introduced latch model.

6. Conclusions

This paper introduced the statistical SI analysis on the DFE with the nonideal latch model. A nonideal DFE propagates a bit error due to the significant amount of ISI noise. Likewise, a nonideal latch causes uncertainty when the voltage difference between the received voltage and the threshold voltage is not large enough. Thus, the proposed method approximates the uncertainty with the Gaussian distribution from the transfer function of the dynamic latch because the transfer function shows the electrical characteristics of the nonideal latch with the PVT variation. The dynamic latch has different transfer functions depending on the iteration. Hence, the feedback time and the SR latch determine which transfer function is approximated. The statistical eye diagram with the nonideal latch model has blurred PDFs depending on the threshold voltage because, when the sampling voltage is close to the threshold voltage, the probability of uncertainty increases. Therefore, the effect of the nonideal latch is modeled and reflected with the proposed method.

This research focuses on the nonideality of the DFE. Further research on the nonideality of the equalizers will be conducted in the future. The practical equalizers have defects that affect the statistical eye diagram. Currently, the statistical eye diagram has discrepancies to the measurements. Therefore, further work on the statistical eye diagram has to be continued for practical use.