A 12 μW 10 kHz BW 58.9 dB SNDR AC-Coupled Incremental ADC for Neural Recording

Abstract

This paper presents an AC-coupled, incremental analog-to-digital converter (ADC) based on two-step quantization for high-density implantable neural recording. It achieves a rail-to-rail electrode DC offset (EDO) rejection, low noise, a small area, and low power consumption. Fabricated in a 180 nm CMOS process, the prototype ADC achieves a high input impedance, 24 mVpp linear input range, and 58.9 dB signal-to-noise and distortion ratio (SNDR). Its core circuit has a power consumption of 12 μW and an area of 0.0192 mm². The referred-to-input (RTI) noise is 6.9 μVrms within the bandwidth of 1 Hz–10 kHz.

1. Introduction

In brain–computer interface (BCI) systems, implantable neural signals like local field potential (LFP) and action potential (AP) have been widely studied due to their good signal quality and spatial resolution [1]. However, limited by the number of channels that implantable neural recording chips record, research can only be conducted on a small number of neurons. The limited amount of neural information restricts further development in neuroscience. To obtain more accurate and abundant neural signal information, there is a great demand for high-density neural recording. However, for high-density neural recording chips, the design of recording unit circuits is crucial. Record unit circuits should have lower power consumption and smaller areas while meeting the requirements for noise.

Currently, there are multiple circuit design methods for neural recording chips [1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32]. The most commonly used design methods can be divided into two main categories. As shown in Figure 1a, the first approach involves amplifying the input signal with a low-noise instrumentation amplifier (IA), passing it through a programmable gain amplifier (PGA), and then quantifying it with a medium-accuracy (10–12 bit) low-power ADC [2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23]. There are two main implementation methods for low-noise IAs. The first method utilizes a capacitance amplifier, forming a high-pass filter with capacitance and pseudo-resistance, with a 3 dB cutoff frequency below 1 Hz, which is able to eliminate EDO rail-to-rail [2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18]. This amplifier structure is simple and widely used. However, the low-frequency noise performance of capacitive-coupled neural amplifiers is poor. Neural signals like LFP signals often have signal energy concentrated in the low-frequency range. The second implementation method uses an amplifier with a chopper-stabilized structure [19,20,21,22,23]. This design allows for chopping input and good low-frequency noise performance, addressing the aforementioned issue. Amplifiers designed with a chopper stabilization structure are complex, often nested with multiple loops to improve performance. For example, they require a DC servo loop (DSL) to eliminate EDO, and this kind of EDO cancellation has a limited range. Successive approximation register (SAR) ADCs are commonly used in the first approach because they have low power consumption and the accuracy can meet the requirements.

However, as the number of integrated channels increases, the first approach becomes limited by the complex signal processing chain, which restricts the area of the recording unit circuit. To address this issue, researchers have proposed a second solution, as shown in Figure 1b, which directly quantifies neural signals using low-noise ADC [24,25,26,27,28,29,30,31,32]. These ADCs are mostly oversampling-type ADCs, utilizing noise shaping to improve accuracy. Refs. [25,26,27] adopted the Δ-ΔΣ architecture, which adds a differentiator before the conventional ΔΣ to eliminate EDO by subtracting adjacent input signals. Refs. [28,29,30] utilized an incremental ΔΣ ADC architecture. The area of the recording unit in [28,29] is very small: less than 0.005 mm². Refs. [31,32] utilized a continuous time ΔΣ architecture, realizing a recording range of up to hundreds of mV. Ref. [31] used a VCO as the quantizer, which is currently a very popular design method.

There are many different architectures for neural recording ADCs. Among them, ref. [29] proposed an incremental ADC with two-step quantization, which has the advantages of a small area and low power consumption. However, due to its DC input, when EDO occurs, its performance, especially noise and linearity, will significantly decrease. The range of EDO it can cancel is limited to ±60 mV, severely restricting its application range. To address this issue, this paper proposes an AC-coupled two-step incremental ADC, which can eliminate EDO rail-to-rail without requiring additional power consumption, while retaining the performance advantages of this architecture. Through chip testing, the ADC was proven to function properly. The remaining sections of this paper are organized as follows: Section 2 provides a mathematical analysis of the working principle of ADC; Section 3 details the specific circuit implementation of ADC; Section 4 presents the measurement results, analysis, and performance comparison with other works. Finally, Section 5 concludes the paper.

2. System Architecture of the ADC

The system architecture adopted in this article is similar to the architecture proposed in reference [29]; both are two-step quantization incremental ADCs. The system diagram is shown in Figure 2. Each data conversion process is divided into three stages: resetting, coarse quantization, and fine quantization. In the 0th clock cycle, resetting is performed to clear the residual error from the previous data conversion cycle. From the 1st to the M1th clock cycle, coarse quantization is carried out. During this stage, the input signal $V_{in}$ and the feedback digital-to-analog converter (DAC, with DAC coefficient a₁) complete M₁-1 periods of integration separately. The result of integration is stored in the integrator, and then fine quantization is carried out. During the fine quantization stage, the input signal $V_{in}$ is set to 0, and only the feedback DAC (with reduced DAC coefficient a₂) is used to quantize the error from the previous stage. This stage lasts from the (M₁ + 1)th cycle to the (M₁ + M₂ − 1)th cycle. Finally, the comparison result at the rising edge of the (M₁ + M₂)th cycle is placed in the lowest bit of the output result, improving the precision by one bit. The control waveforms at key nodes in this process are shown in Figure 3. The waveform of the node voltage on the integrator during one data conversion process is shown in Figure 4. In this case, Vref represents the voltage value generated by the DAC current on the integrator capacitor during one clock cycle T when the input Vin is 0 and the DAC coefficient is a₁.

We perform a mathematical analysis in the time domain of the data conversion process of the above-mentioned ADC. Assume the oversampling rate is high enough so that the input signal Vin can be considered constant within one conversion period. Assume that the clock period T = 1; , the result of the integrator in the analog loop after the coarse quantization stage is

$$-{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}\le ({\mathrm{M}}_1-1){\mathrm{V}}_{\mathrm{i}\mathrm{n}}-\sum _{\mathrm{i}=2}^{{\mathrm{M}}_1}\mathrm{D}(\mathrm{i}){\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}\le {\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}$$

(1)

Similarly, after the fine quantization stage, the result of the integrator in the loop filter is

$$-\frac{{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{{\mathrm{M}}_2}\le ({\mathrm{M}}_1-1){\mathrm{V}}_{\mathrm{i}\mathrm{n}}-\sum _{\mathrm{i}=2}^{{\mathrm{M}}_1}\mathrm{D}(\mathrm{i}){\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}-\sum _{\mathrm{i}={\mathrm{M}}_1+1}^{{{\mathrm{M}}_1+\mathrm{M}}_2-1}\mathrm{D}(\mathrm{i})\frac{{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{{\mathrm{M}}_2}\le \frac{{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{{\mathrm{M}}_2}$$

(2)

Place the comparison result of the (M₁ + M₂)th rising edge of the clock at the least significant bit of the output of the digital reconfigurable filter, and then the result of the integrator can be equivalently represented as

$$-\frac{{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{2{\mathrm{M}}_2}\le ({\mathrm{M}}_1-1){\mathrm{V}}_{\mathrm{i}\mathrm{n}}-\sum _{\mathrm{i}=2}^{{\mathrm{M}}_1}\mathrm{D}(\mathrm{i}){\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}-\sum _{\mathrm{i}={\mathrm{M}}_1+1}^{{{\mathrm{M}}_1+\mathrm{M}}_2-1}\frac{\mathrm{D}(\mathrm{i}){\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{{\mathrm{M}}_2}-\frac{\mathrm{D}({\mathrm{M}}_1+{\mathrm{M}}_2){\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{2{\mathrm{M}}_2}\le \frac{{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{2{\mathrm{M}}_2}$$

(3)

After a data transformation cycle, the quantization error can be represented as

$$-\frac{{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{2{\mathrm{M}}_2({\mathrm{M}}_1-1)}\le {\mathrm{V}}_{\mathrm{i}\mathrm{n}}-{\hat{\mathrm{V}}}_{\mathrm{i}\mathrm{n}}\le \frac{{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{2{\mathrm{M}}_2({\mathrm{M}}_1-1)}$$

(4)

where ${\hat{V}}_{in}$ represents the estimate of input signal $V_{in}$, and the expression of ${\hat{V}}_{in}$ is

$${\hat{\mathrm{V}}}_{\mathrm{i}\mathrm{n}}=\sum _{\mathrm{i}=2}^{{\mathrm{M}}_1}\frac{\mathrm{D}(\mathrm{i}){\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{{\mathrm{M}}_1-1}+\sum _{\mathrm{i}={\mathrm{M}}_1+1}^{{{\mathrm{M}}_1+\mathrm{M}}_2-1}\frac{\mathrm{D}(\mathrm{i}){\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{{\mathrm{M}}_2({\mathrm{M}}_1-1)}+\frac{\mathrm{D}({\mathrm{M}}_1+{\mathrm{M}}_2){\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}}{2{\mathrm{M}}_2({\mathrm{M}}_1-1)}$$

(5)

where $D(i)$ represents the comparison result of the comparator when the rising edge of the i-th clock arrives. As shown in Figure 2, these comparison results can be summed according to the corresponding weighting coefficients c₁, c₂, and c₃ to obtain the data output Dout. According to Equation (5), we find that c₁ = M₂ × c₂ = 2 M₂ × c₃.

From Equation (4), it can be seen that the lowest bit of ADC is $V_{lsb}$ = $V_{ref}/(2M_2\left(M_1-1\right))$. Therefore, when the input signal is $V_{in}$, after one conversion, the achievable effective number of bits (ENOB) is

$$\mathrm{E}\mathrm{N}\mathrm{O}\mathrm{B}={\log }_2\left(\frac{2{\mathrm{V}}_{\mathrm{i}\mathrm{n}}}{{\mathrm{V}}_{\mathrm{l}\mathrm{s}\mathrm{b}}}\right)={\mathrm{l}\mathrm{o}\mathrm{g}}_2(\frac{{\mathrm{V}}_{\mathrm{i}\mathrm{n}}}{{\mathrm{V}}_{\mathrm{r}\mathrm{e}\mathrm{f}}})+{\mathrm{l}\mathrm{o}\mathrm{g}}_2({\mathrm{M}}_1-1)+{\mathrm{l}\mathrm{o}\mathrm{g}}_2({\mathrm{M}}_2)+1$$

(6)

In fact, in the above-mentioned time domain analysis, we assume that the input signal $V_{in}$ is a DC quantity that does not vary with time. In reality, the input signal $V_{in}$ is a function of time, so within M₁ − 1 clock periods, the integral of the input signal $V_{in}$ does not simply equal (M₁ − 1)T $V_{in}$, but, rather, the result of integrating $V_{in}$ with respect to time, which depends on the frequency of $V_{in}$. We assume $V_{in}$ is a complex exponential signal with an amplitude of A, a frequency of w, and an initial phase of φ. The result of the integration over a time duration of (M₁ − 1)T is

$${\int }_0^{({\mathrm{M}}_1-1)\mathrm{T}}\mathrm{A}{\mathrm{e}}^{\mathrm{j}(\mathrm{w}\mathrm{t}+\mathsf{\phi })}\mathrm{d}\mathrm{t}={\mathrm{e}}^{\mathrm{j}(\mathrm{w}(\frac{{\mathrm{M}}_1-1}{2})\mathrm{T}+\mathsf{\phi })}\frac{2\mathrm{A}\mathrm{s}\mathrm{i}\mathrm{n}(\mathrm{w}(\frac{{\mathrm{M}}_1-1}{2})\mathrm{T})}{\mathrm{w}}$$

(7)

We focus on its magnitude transfer function and normalize it. The normalization standard is as shown in Equation (1). Assuming that $V_{in}$ is a DC signal, with a signal magnitude of A and integrated over a time length of (M₁ − 1)T, the result of the integration is (M₁ − 1)TA. After normalization, the magnitude transfer function is obtained as

$$\mathrm{H}(\mathrm{w})=\frac{2\mathrm{s}\mathrm{i}\mathrm{n}(\mathrm{w}(\frac{{\mathrm{M}}_1-1}{2})\mathrm{T})}{\mathrm{w}({\mathrm{M}}_1-1)\mathrm{T}}$$

(8)

The magnitude of $H(w)$ varies with frequency as shown in Figure 5, where the frequency is normalized. Here, Fs represents the data output rate of the ADC. Since it is an incremental ADC, it belongs to the Nyquist ADC, with a data output rate that is twice the Nyquist frequency. It is noted that due to the use of a two-step quantization operation, in a complete conversion of M₁ + M₂ clock cycles, the input signal is active for M₁ − 1 clock cycles. This causes the zeros of $H(w)$ due to input signal integration not to occur at integer multiples of Fs, but rather at n(M₁ + M₂)/(M₁ − 1)Fs, where n is a positive integer.

Overall, the down-sampling process of the two-step incremental ADC can be completed by summing the results of different quantization stages’ comparators together according to the corresponding weights c₁, c₂, and c₃. Compared with traditional ΔΣ ADC, the down-sampling filter design of this structure is simpler. Additionally, compared with the traditional first-order incremental ADC [28], this structure can reduce the oversampling ratio, which is lower by M₁M₂/(M₁ + M₂) times. In this design, M₁ = 128 and M₂ = 8 are chosen. For a neural signal bandwidth of 10 kHz, the oversampling ratio is M₁ + M₂ = 136, the clock frequency F_clk is 2.72 MHz, and the ADC’s quantization bit number is 11 bits, which is sufficient to meet the requirements for neural recording.

3. Circuit Implementation

3.1. Circuit Implementation of the ADC

The schematic of the proposed ADC is shown in Figure 6. The entire ADC consists of a front-end high-pass filter, a transconductance–capacitance (Gm-C) integrator, a single-bit current DAC, a dynamic comparator, internal logic control circuitry, and the digital reconstruction filter. These modules are described separately below.

3.2. Design of Analog Front End

As shown in Figure 6, at the input of the ADC, a high-pass filter consisting of an input capacitor and pseudo-resistor is employed. The pseudo-resistor comprises a cut-off thick-oxide PMOS transistor, which achieves a resistance of TΩ. In combination with the input capacitor of 5 pF, the 3 dB cutoff frequency of the high-pass filter is lower than 0.1 Hz, which eliminates EDO without affecting the recording of neural signals.

The selection of the pseudo-resistor structure is very important for the implementation of the proposed ADC. As shown in Figure 7, two different structures of a pseudo-resistor are given, and we chose the structure in Figure 7a and explain why the structure in Figure 7b is not suitable. Using thick-oxide PMOS transistors to form pseudo-resistors, considering that the value of the pseudo-resistor is in the TΩ level and the current flowing through the equivalent resistor is in the pA level, the leakage current of the parasitic diode between Nwell and Psub must be considered. When using the structure in Figure 7a, the bias voltage V_bias is used to provide the reverse leakage current I_leak. Assuming that there is no leakage current at the gate of input PMOS transistor, it can be equivalent to an open circuit, so the voltage on R_1a is 0. The voltage at the gate of the input transistor V_Ga = V_bias. On the contrary, when the structure in Figure 7b is used, as two PMOS transistors are cascaded and their Nwell are connected, the potential of Nwell V_b is a floating potential. Due to the presence of I_leak of the parasitic diode, a voltage ΔV is generated across the equivalent resistor R_1b of one of the PMOS transistors, causing the voltage of Nwell in Figure 7b to be V_b = V_bias − ΔV. Similarly, assuming the gate terminal of the input PMOS transistor can be equivalent to an open circuit, there is no current flowing through R_2b, so we can obtain V_Gb = V_b = V_bias − ΔV. ΔV can be simply regarded as the voltage generated by the I_leak flow on R_1b, and since I_leak varies with temperature and light conditions [33], ΔV also varies. Since the proposed ADC has an open-loop architecture with an input range of only around 20 mVpp, this variation in ΔV will directly affect the input range of the ADC, causing the ADC to not function properly. Similar architectures of pseudo-resistors can be analyzed using the method proposed in this paper.

Due to the elimination of EDO, the input of the integrator only processes weak neural signals, reducing the requirement for the linearity of the integrator. Therefore, a Gm-C integrator was adopted. The schematic of the operational transconductance amplifier (OTA) is shown in Figure 8a. Thick-oxide PMOS transistors are used as inputs, and four input transistors are connected through two sets of switches controlled by SW0 and SW0N to realize the normal connection or short-circuit connection of signals [29]. In the coarse quantization stage, only the Chop_N switches are turned on with an operating frequency of 340 kHz, modulating the 1/f noise of the load NMOS transistors to a high frequency. In the fine quantization stage, both the Chop_N and Chop_P switches are turned on with an operating frequency of 2.72 MHz. The purpose is to prevent errors introduced by the mismatch of the input PMOS transistors and load NMOS transistors during the fine quantization stage. Notice that chopping only reduces the 1/f noise of the load NMOS transistors. For the input PMOS transistors, we reduce the impact of 1/f noise by appropriately increasing the size. The gate terminals of the NMOS load transistors are connected in an alternating pattern to output Von and Vop as a common-mode feedback (CMFB) loop. The current DAC feedback to IFBP or IFBN. During each clock cycle, only IFBP or IFBN is connected. The integrating capacitor has a value of about 400 fF, which allows the output voltage to change within a suitable range.

The single-bit current DAC is shown in Figure 8b. The current DAC selectively connects to IFBN or IFBP based on the comparison results labeled as FBP and FBN. SW1 controls the magnitude of the DAC current connected to the integrator. When SW1 is 0, it is in the coarse quantization stage, and when SW1 is 1, it is in the fine quantization stage. The ratio of the currents of the two stages is 8:1. Increasing the size of the DAC current source transistors can reduce mismatch and lower 1/f noise.

The RTI noise of the ADC is divided into two parts: one part is the quantization noise related to the bits of ADC, and the other part is the noise related to the circuit itself, including thermal noise, 1/f noise, etc.

First, consider the influence of quantization noise. The ADC in this design has 11 bits, and the theoretical SNR is 67.94 dB. The maximum input range of this design is V_FS = 24 mVpp. Therefore, the quantization noise of the ADC is

$${\mathrm{v}}_{\mathrm{n},\mathrm{q}}=\sqrt{\frac{{{\mathrm{V}}_{\mathrm{F}\mathrm{S}}}^2}{8{·10}^{\mathrm{S}\mathrm{N}\mathrm{R}}}}$$

(9)

The equivalent quantization noise is 3.4 μV rms.

By allowing the circuit noise to dominate the RTI noise, a higher energy efficiency can be achieved. The expression for circuit noise equivalent to the input end is

$$\overline{{\mathrm{V}}_{\mathrm{n}}^2}=\frac{8\mathrm{k}\mathrm{T}{\mathrm{R}}_{\mathrm{p}}}{{(1+\frac{\mathrm{f}}{{\mathrm{f}}_{\mathrm{H}\mathrm{P}}})}^2}+\frac{8\mathrm{k}\mathrm{T}\mathsf{\gamma }}{{\mathrm{g}}_{\mathrm{m},\mathrm{i}\mathrm{n}}}(1+\frac{{\mathrm{g}}_{\mathrm{m},\mathrm{n}\mathrm{l}}}{{\mathrm{g}}_{\mathrm{m},\mathrm{i}\mathrm{n}}}+\frac{{\mathrm{g}}_{\mathrm{m},\mathrm{D}\mathrm{A}\mathrm{C}}}{{2\mathrm{g}}_{\mathrm{m},\mathrm{i}\mathrm{n}}})+\frac{2{\mathrm{K}}_{\mathrm{p}}}{{\mathrm{C}}_{\mathrm{o}\mathrm{x}}{(\mathrm{W}\mathrm{L})}_{\mathrm{i}\mathrm{n}}}\frac{1}{\mathrm{f}}+\frac{{\mathrm{K}}_{\mathrm{n}}}{{\mathrm{C}}_{\mathrm{o}\mathrm{x}}{(\mathrm{W}\mathrm{L})}_{\mathrm{D}\mathrm{A}\mathrm{C}}}({\frac{{\mathrm{g}}_{\mathrm{m},\mathrm{D}\mathrm{A}\mathrm{C}}}{{\mathrm{g}}_{\mathrm{m},\mathrm{i}\mathrm{n}}})}^2\frac{1}{\mathrm{f}}$$

(10)

In this case, k represents the Boltzmann constant, T represents the absolute temperature, γ is the coefficient in the expression, generally around 2/3, K_n and K_p are constants related to the process, f_HP represents the cutoff frequency of the high-pass filter, f_HP = 1/(2πC_in∙R_P), where C_in represents the input capacitance, and R_P represents the pseudo-resistor. Adjusted R_P around 1.5TΩ to ensure that the noise contribution from R_P is below 20%. g_m,in represents the transconductance of the OTA, g_m,nl represents the transconductance of the load NMOS transistors of the OTA, and g_m,DAC represents the transconductance of the DAC current source transistor. The input pairs are biased in weak inversion for a higher g_m/i_d, while the load NMOS transistors and DAC current source transistors are biased in strong inversion to reduce their noise contribution. Since the current of the DAC is small, g_m,in:g_m,DAC > 10; therefore, the circuit noise contribution from the DAC can be ignored.

As shown in Figure 9a, the comparator used in this design adopts the structure from [34]. Figure 9b shows the control logic, and Figure 9c presents the circuitry for generating the corresponding control logic. Compared with traditional dynamic comparators, this comparator can save up to 33% of power [34].

3.3. Design of Digital Logic Control and Data Reconfiguration Circuits

The design of the digital logic control circuit is based on an 8-bit counter, using the asynchronous clear terminal of D flip-flops. Through logical operations, the timing sequence shown in Figure 3 is generated, and the specific circuit is shown in Figure 10. EN is the enable signal. The circuit starts to work when EN is high. CLK is the input clock with a frequency of 2.72 MHz.

According to Equation (5), it can be seen that when selecting M₁ = 128 and M₂ = 8, as shown in Figure 6, the data reconstruction circuit can be composed of a 7-bit up counter (used for summing the comparison results in the coarse quantization stage), a 3-bit up counter (used for summing the comparison results in the fine quantization stage), and an 11-bit result register. The 7-bit counter result is input to the high 7 bits of the result register, the 3-bit counter result is input to the 8th to 10th bits of the result register, and finally, the comparison result of the 136th clock rising edge of each conversion cycle is directly input to the lowest bit of the result register. The 11-bit result register is reset every 20 kHz, corresponding to twice the Nyquist frequency.

3.4. Design of Current Reference

The current reference circuit, as shown in Figure 11, is composed of transistors M1, M2, M3, and M4 and resistor R1. The startup circuit consists of transistors M5, M6, M7, and capacitor C1. The size (W/L) of M1 is 600 μm/2 μm, M2 is 60 μm/24 μm, and M3 and M4 are 8 μm/80 μm; and the value of R1 is about 75 kΩ. The reference current value is 2 μA.

As shown in Figure 11, the current DAC is generated by the reference current source. Considering that DAC is only added to one side of the circuit, the noise of the current reference will directly superimpose Gm through DAC. Assuming the transconductance of the input transistors is g_m,in, the contribution of thermal noise of the current reference circuit to the input-referred noise $V_{n,t}$ is

$${\mathrm{V}}_{\mathrm{n},\mathrm{t}}=\frac{\mathrm{k}\mathrm{T}\mathsf{\gamma }}{{\mathrm{N}}^2{\mathrm{g}}_{\mathrm{m},\mathrm{i}\mathrm{n}}^2}[\frac{{\mathrm{g}}_{\mathrm{m}1}}{(1+{\mathrm{g}}_{\mathrm{m}1}{\mathrm{R}}_1{)}^2}+\frac{{\mathrm{g}}_{\mathrm{m}1}^2{\mathrm{R}}_1}{\mathsf{\gamma }\cdot (1+{\mathrm{g}}_{\mathrm{m}1}{\mathrm{R}}_1{)}^2}+{\mathrm{g}}_{\mathrm{m}2}+{\mathrm{g}}_{\mathrm{m}3}+{\mathrm{g}}_{\mathrm{m}4}]$$

(11)

The contribution of the 1/f noise of the current reference circuit to the input-referred noise $V_{n,f}$ is

$${\mathrm{V}}_{\mathrm{n},\mathrm{f}}=\frac{1}{4{\mathrm{N}}^2{\mathrm{g}}_{\mathrm{m},\mathrm{i}\mathrm{n}}^2{\mathrm{C}}_{\mathrm{o}\mathrm{x}}}[\frac{{\mathrm{K}}_{\mathrm{p}}{\mathrm{g}}_{\mathrm{m}1}^2}{(1+{\mathrm{g}}_{\mathrm{m}1}{\mathrm{R}}_1{)}^2(\mathrm{W}\mathrm{L}{)}_1}+\frac{{\mathrm{K}}_{\mathrm{p}}{\mathrm{g}}_{\mathrm{m}2}^2}{(\mathrm{W}\mathrm{L}{)}_2}+\frac{{\mathrm{K}}_{\mathrm{n}}{\mathrm{g}}_{\mathrm{m}3}^2}{(\mathrm{W}\mathrm{L}{)}_3}+\frac{{\mathrm{K}}_{\mathrm{n}}{\mathrm{g}}_{\mathrm{m}4}^2}{(\mathrm{W}\mathrm{L}{)}_4}]$$

(12)

Taking N = 10 here, the noise of the current reference is greatly attenuated, and it does not affect the input reference noise.

4. Manufacture and Measurement

Manufactured using a 180 nm process, the die photo of the chip is shown in Figure 12. To validate different circuit architectures, we designed multiple versions. The ADC identified in Figure 12 corresponds to the one mentioned in this article. The area of the proposed ADC is 0.0192 mm². To save the number of PADs, a parallel-to-serial conversion interface circuit was designed to enable a serial output of ADC data, as shown by “Data_Out” in Figure 12. The PCB for chip testing is shown in Figure 13a, and the testing equipment and environment are shown in Figure 13b. We used LDOs to supply the power for the chip, with the model being TI’s LP5907. The waveform generator 33500B from Keysight generates a 2.72 MHz clock square wave signal, and the APx555B Series High-Performance Audio Analyzer generates the input signal source for testing.

At a voltage of 1.5 V, the core power consumption of the ADC is 12 μW, with an analog part power of 7.3 μW and a digital part power of 4.7 μW. Within the bandwidth of 1 Hz–10 kHz, the RTI noise is 6.9 μVrms. The RTI noise spectral density is shown in Figure 14. We tested the linearity with input signals of 15 mVpp and input frequencies ranging from 10 Hz to 1 kHz. The test results are shown in Figure 15. The linearity performs well when calculating THD with up to 10 harmonics included. When a 1 kHz test signal is input, the linearity is 0.036%, and the spectrum density is shown in Figure 16. The maximum input range is 24 mVpp. Under different input signal frequencies, the maximum ENOB that the ADC can achieve was tested. The test results are shown in Figure 17. At input signal frequencies of 100 Hz and 200 Hz, the maximum ENOB was 9.6 bits. At an input signal frequency of 1 kHz, the maximum SNDR was 58.9 dB, and the ENOB was 9.5 bit. The SNR/SNDR versus input range change at 1 kHz is shown in Figure 18. The test results for differential nonlinearity (DNL) and integral nonlinearity (INL) of the ADC are shown in Figure 19. In the vicinity of the full scale, the values of DNL are +1.8/−1 LSB, and the values of INL are +2/−1.8 LSB. The values of DNL and INL deteriorate when approaching the full scale as the least significant bit (LSB) of the ADC is completely dominated by thermal noise. And the ADC is affected by some non-ideal factors of the circuit, such as charge injection, digital interference, etc., leading to deviations between the logic implemented by the circuit and the ideal mathematical model, which results in the deterioration of DNL/INL.

The comparison between this work and other outstanding works is shown in

Table 1. Measured performance and comparison to prior art.

	JSSC [13]	TBCAS [14]	TBCAS [17]	JSSC [28] d	JSSC [29]	This Work
Architecture	AMP + ADC	AMP + ADC	AMP + ADC	ADC only	ADC only	ADC only
Process (μm)	0.18	0.13	0.13	0.18	0.18	0.18
Supply (V)	1.8	1.2/1.8	1.2	1.8	1.8	1.5
Power (μW) /Channel	16	49.06	95.1 c	39.14	14.94	12
Input Range (mVpp)	- a	- a	- a	22.5	14	24
RTI noise (μVrms)	2.4 (300–3 kHz) 3.6 (1–300 Hz)	6.36 (0.3 k–3 kHz)	7.44 (0.3 k–10 kHz) 7.65(0.5–1 kHz)	12 (1 Hz–10 kHz)	4.9 (1 Hz–10 kHz) e	6.9 (1 Hz–10 kHz)
THD	- b	0.4% (10 mVpp)	0.17% (10 mVpp)	0.22% (10 mVpp)	0.078% e (10 mVpp)	0.036% (15 mVpp)
Area (mm2) /Channel	>0.02	0.12	0.035	0.0049	0.00462	0.0192
EDO tolerance	Rail-to-Rail	Rail-to-Rail	Rail-to-Rail	22.5 mV	±60 mV	Rail-to-Rail

^a The recording chip with AMP + ADC architecture has an adjustable gain for its amplifier. When the gain is reduced, the amplitude of the input signal increases, but the noise performance deteriorates. This parameter is not mentioned in the corresponding article. ^b Ref. [13] is not mention THD in the paper. ^c Power management and digital power included. ^d The design proposed in ref. [28] allows for an adjustable input range, selecting the input range with the best noise performance for comparison. ^e These parameters are measured at EDO = 0 mV. When EDO increases, the performance parameters deteriorate.

. Compared with the traditional architecture of cascading amplifiers and ADC [13,14,17], our work has the smallest area and the lowest power consumption.

Compared to [28,29], this work can effectively eliminate EDO rail-to-rail and has the best power performance. Compared to [29], the performance of this work did not deteriorate with the increase in EDO.

5. Conclusions

An AC-coupled, two-step quantization incremental ADC for neural recording is proposed in this paper. It has low noise, a small area, and low power consumption, and it can reject EDO rail-to-rail. Under the manufacturing conditions of a 180 nm process, the proposed ADC has a total power consumption of 12 μW and an area of 0.0192 mm². Within the 1 Hz–10 kHz bandwidth, the input reference integrated noise of the ADC is 6.9 μVrms, meeting the requirements for recording neural signals. The full-scale input range is approximately 24 mVpp, and the highest SNDR is 58.9 dB. With advanced process nodes, the performance of the proposed ADC can be further improved. For high-density implantable neural recording chips, this is an attractive architecture choice.