Picowatt Dual-Output Voltage Reference Based on Leakage Current Compensation and Diode-Connected Voltage Divider

Abstract

A picowatt CMOS voltage reference with dual outputs is proposed and simulated in this paper based on a standard 65 nm process. To compensate for the leakage current caused by parasitic reverse-biased PN junctions, an approach employing gate leakage transistors is proposed. Maintaining a maximal temperature coefficient (TC) of 20.40 ppm/°C across an extended temperature range of −10∼155 °C is achieved. Additionally, a voltage divider consisting of diode-connected NMOS transistors is introduced to obtain a lower voltage output without shunting the original branch or utilizing operational amplifiers. Moreover, a novel trimming block is utilized to optimize TC across different process corners. Simulation results demonstrate that a minimum power consumption of only 53.83 pW is achieved and the line sensitivity is 0.077%/V with 0.45 V to 2.5 V supply. The power supply rejection ratio of −76.70 dB at 10 Hz and $V_{DD}$ = 1.8 V is obtained.

1. Introduction

Voltage references (VRs) are key modules in most analog and digital systems, playing a critical role in generating stable DC voltages that remain nearly independent of temperature, process, and supply voltage. With the development of energy harvesting (EH) technology, new design challenges for VRs in applications adopting it, such as wearable devices, the Internet of Things (IoT), mobile healthcare, and Wireless Sensor Networks (WSNs), have been introduced [1]. Given the unsteadiness and weakness of the energy collected by the EH, there is a pressing need to develop VRs with minimized supply voltage and low power consumption.

The high supply and power consumption in traditional bandgap voltage references (BGRs) render them impractical for applications like WSNs due to limitations imposed by BJTs [2,3,4]. Efforts have been made to explore alternative transistor-based solutions [5,6,7], yet achieving power consumption lower than the nW range has proven challenging. To further reduce power consumption and supply voltage, VRs based on transistors operating in the subthreshold region and the gate-source voltages of MOSFETs with different thresholds have been proposed [8,9,10]. Among them, the power consumption of VRs utilizing leakage current biasing can be as low as pW level [11,12,13]. However, the operating temperature of the circuit is limited due to its small biasing current at low temperatures and the large current of parasitic reverse-biased PN junctions at high temperatures [14,15,16]. Despite achieving supply voltage as low as 0.25 V in [16], the operational temperature range of this VR is limited to 0∼120 °C.

In order to maintain a low temperature coefficient (TC) across a wide temperature range, recent studies have proposed various methods to enhance temperature compensation [17,18,19]. In [17,18], an exponential current consumption is generated through the PTAT gate bias voltage of a transistor and then replicated in a diode-connected NMOS through a current mirror. This method effectively improves TC but increases current consumption to 9.6 nW. Ref. [19] utilizes reverse-biased PMOS transistors to generate exponentially higher currents at high temperatures for compensating leakage currents. However, the need to connect in parallel with the current mirror necessitates a similar nW-level current consumption.

Furthermore, as shown in Figure 1, to accommodate varying DC voltage value requirements across multiple modules in integrated systems while adhering to constraints of low supply voltage and minimal power consumption, the design of multi-output VRs integrating multiple outputs into a single reference circuit has been proposed. Conventional multi-output voltage references often rely on stacked MOS transistors, which typically mandate high supply voltage. Review of recent studies, ref. [20] proposes a voltage level shifter. However, it operates in the saturation region, requiring a minimum supply voltage of 1.2 V. Refs. [21,22] introduce a three-output voltage reference employing a specialized multi-loop active load. Ref. [21] achieves a minimum supply voltage of 0.45 V, but two of its output voltages are below 100 mV, limiting their load drive capability. Meanwhile, ref. [22] utilizes an operational amplifier. Ref. [23] successfully generates dual outputs of 320.5 mV and 281 mV, but at the expense of a larger area (0.012 mm²) for resistor usage.

This paper proposes a dual-output CMOS VR with a wide temperature range and low supply voltage, which employs a leakage current compensation technique and a diode-connected voltage divider. The leakage current compensation technique significantly improves TC to a maximum of 111.97 ppm/°C in this circuit and ensures its stability at different process corners by the trimming block. The diode-connected voltage divider achieves voltage level shift, eliminating the need for operational amplifiers and resistors. On the one hand, self-biased native transistors acting as a current source and the leakage current compensation technique ensure reliable operation at minimal power consumption and low supply voltage suitable for EH systems. On the other hand, by obtaining more outputs in a single VR circuit, the efficiency of the circuit can be improved.

In the rest of this paper, the operating principle of the proposed VR is discussed in Section 2. Section 3 describes the simulation results and comparisons with the state-of-the-art designs. Finally, Section 4 concludes.

2. Principle of the Proposed Voltage Reference

Figure 2a,b separately illustrate the block diagram and schematic of the dual-output voltage reference proposed in this paper. The design includes a leakage current compensation circuit with a trimming block, an active load, two self-biased current sources, and a diode-connected voltage divider.

Specifically, $M_1$ and $M_4$ are native thick-oxide NMOS transistors (2.5 V ZVT), which have near-zero threshold voltages. Their thick gate oxides enable them to support high $V_{DD}$ from batteries or I/O pads, in addition to harvesting environmental energy. $M_2$ and $M_3$ are standard-Vth thin-oxide NMOS transistors (1.2 V SVT), $M_5$ is native thin-oxide NMOS transistors (1.2 V ZVT), and $M_6$ is high-Vth thin-oxide PMOS transistor (1.2 V HVT). The threshold voltage difference between $M_5$ and $M_6$ generates voltage reference. By replacing $M_5$ and $M_6$ in the active load with transistors of other threshold voltages, output with different reference values can be generated. Additionally, $M_7$ is a low-Vth thin-oxide NMOS transistor (1.2 V LVT). To prevent substrate leakage currents leaking to ground resulting from voltage differences between the substrate, the drain, and the source, the substrate of $M_7$ is connected to its drain and source. Therefore, $M_7$ needs to be a DNW device to ensure that the substrate voltage of the p-well remains independent of the global substrate voltage.

2.1. Temperature Compensation without Leakage Current Compensation

The core idea of generating reference voltage is to utilize a diode-connected MOS transistor biased in the subthreshold region. When it satisfies $V_{DS}\ge 4V_T$, the influence of $V_{DS}$ on $I_{DS}$ can be ignored. This relationship is succinctly expressed as:

$$V_{GS}=V_{DS}=V_{TH}+m{V}_{T}ln\left[{\displaystyle \frac{I_D}{\mu C_{OX}K(m-1)V_T^2}}\right],$$

(1)

where m is the subthreshold slope factor, $V_T$ is the thermal voltage, K is the width and length ratio of the transistor, $\mu$ is the mobility, and $C_{OX}$ is the oxide capacitance.

The threshold voltage $V_{TH}$ of MOS transistors is given by:

$$V_{TH}=V_{TH0}+k_T\left({\displaystyle \frac{T}{T_0}}-1\right)=V_{TH0}-{\alpha }_T(T-T_0),$$

(2)

where $V_{TH0}$ is the threshold voltage independent of temperature, $k_T<0$ is the temperature coefficient of $V_{TH}$, and ${\alpha }_T$ is another coefficient indicating the temperature dependence of $V_{TH}$.

In addition, the threshold voltage affected by the body effect is:

$${V_{TH}}^{*}=V_{TH}+(m-1)V_{SB},$$

(3)

where $V_{SB}$ is the source-substrate voltage of transistors.

Therefore, $V_{TH}$ has a linear relationship with temperature, exhibiting a negative temperature coefficient (CTAT). And the thermal voltage $V_T={\displaystyle \frac{kT}{q}}$ shows a positive temperature coefficient (PTAT), where k is the Boltzmann constant, T is the absolute temperature, and q is the electron charge.

The zero temperature coefficient can be achieved by the linear weighted summation of $V_T$ (PTAT) and $V_{TH}$ (CTAT) [24]. From the second term of Equation (1), the current source needs to satisfy $I_D=A\mu T^2$ to achieve temperature compensation, where A is a constant.

Since the subthreshold current flowing through the transistor is:

$$I=\mu C_{OX}K(m-1)V_T^2\exp \left({\displaystyle \frac{V_{GS}-V_{TH}}{m{V}_T}}\right)\left[1-\exp \left(-{\displaystyle \frac{V_{DS}}{V_T}}\right)\right],$$

(4)

when $V_{DS}$ is sufficiently large, $\exp \left(-{\displaystyle \frac{V_{DS}}{V_T}}\right)$ is approximated to be 0, thus:

$$I=\mu C_{OX}K(m-1)V_T^2\exp \left({\displaystyle \frac{V_{GS}-V_{TH}}{m{V}_T}}\right).$$

(5)

It maintains a form akin to $A\mu T^2$. Hence, temperature compensation can be realized by ensuring that the current flowing through the diode-connected MOS transistor remains in the subthreshold region. In the proposed VR, the utilization of self-biased native transistors ($M_1$ and $M_4$) guarantees the circuit to operate in the subthreshold region for their $V_{GS}<V_{TH}$.

As depicted in Figure 2b, this is derived from the equal gate-source voltages of $M_5$ and $M_6$:

$$\begin{array}{c}\hfill {V_{TH5}}^{*}+m_5{V}_{T}ln\left[{\displaystyle \frac{I_{D5}}{{\mu }_5{C}_{OX5}{K}_5(m_5-1)V_T^2}}\right]=\left|V_{TH6}\right|+m_6{V}_{T}ln\left[{\displaystyle \frac{I_{D6}}{{\mu }_6{C}_{OX6}{K}_6(m_6-1)V_T^2}}\right],\end{array}$$

(6)

where the threshold voltages of two transistors can be expressed separately as:

$$\begin{array}{cc}\hfill {V_{TH5}}^{*}& =V_{TH0,5}-{\alpha }_{T5}(T-T_0)+(m_5-1)V_{REF1},\hfill \\ \hfill |V_{TH6}|& =\left|V_{TH0,6}\right|-{\alpha }_{T6}(T-T_0).\hfill \end{array}$$

(7)

Therefore, when the currents ($I_{D5}$ and $I_{D6}$) flowing through $M_5$ and $M_6$ are equal, assuming the same subthreshold swing for the two transistors ($m_5$ = $m_6$), $V_{REF1}$ can be expressed as:

$$V_{REF1}={\displaystyle \frac{1}{m-1}}\left[|V_{TH0,6}|-V_{TH0,5}+({\alpha }_{T5}-{\alpha }_{T6})(T-T_0)\right]+{\displaystyle \frac{m{V}_T}{m-1}}ln\left({\displaystyle \frac{{\mu }_5{C}_{OX5}{K}_5}{{\mu }_6{C}_{OX6}{K}_6}}\right).$$

(8)

To achieve zero TC of $V_{REF1}$, the first term can be compensated by the second term of Equation (8) through appropriate sizing of $M_5$ and $M_6$. By setting ${\displaystyle \frac{\partial V_{REF1}}{\partial T}}=0$, the optimum size of MOS transistors can be determined to minimize TC.

2.2. Temperature Compensation with Leakage Current Compensation

Two types of active loads with leakage current biasing in [25,26] are shown in Figure 3a,b. Since the body (P+) of the diode-connected NMOS is grounded and the drain (N+) is the output $V_{REF}$, a parasitic reverse-biased PN junction is formed between the transistor and ground. There is also a parasitic reverse-biased PN junction between the n-well and p-sub of the diode-connected PMOS. The current $I_{DIO}$ flowing through parasitic reverse-biased PN junction can be mathematically expressed as:

$$I_{DIO}\propto n_i^2\propto T^3\exp \left(-{\displaystyle \frac{E_B}{mkT}}\right),$$

(9)

where $n_i$ is the intrinsic carrier concentration and $E_B$ is the width of the energy gap.

Since $I_D=I_{DS}+I_{DIO}$, the existence of $I_{DIO}$ results in unequal subthreshold region current $I_D$ and the current $I_{DS}$ flowing through the diode-connected MOS, thereby deviating from the establishment of Equation (8). This discrepancy deteriorates the temperature performance of the output voltage $V_{REF}$. Especially in the high-temperature region, the extracted current by $I_{DIO}$ will increase significantly according to Equation (9).

In this paper, a leakage current compensation method based on gate leakage transistors is proposed, as shown in Figure 3c. The current $I_{GATE}$ in the gate leakage transistor is critical in this method, including gate-to-channel current ($I_{GC}$), gate-to-source/drain currents ($I_{GS}$ and $I_{GD}$) and gate-to-substrate current ($I_{GB}$). It is injected into the diode-connected MOS transistor to offset the current extracted by the parasitic reverse-biased PN junction, thereby equalizing $I_D$ and $I_{DS}$ and enhancing temperature compensation. According to the modeling results of the gate leakage transistor, when its gate applies a certain voltage, it can be seen as a huge resistor with resistance $R_G$ [27]. Consequently, the compensated current can be expressed as:

$$I_{GATE}={\displaystyle \frac{V_D-V_{REF1}}{R_G}},$$

(10)

where $V_D$ is the D-point voltage.

Given that the current flowing through $M_4$ and $M_6$ is equal, assuming the same subthreshold swing for them, it can be expressed as:

$${\mu }_4{C}_{OX4}{K}_4(m-1)V_T^2\exp \left({\displaystyle \frac{-V_D-V_{TH4}}{m{V}_T}}\right)={\mu }_6{C}_{OX6}{K}_6(m-1)V_T^2\exp \left({\displaystyle \frac{V_{REF1}-\left|V_{TH6}\right|}{m{V}_T}}\right).$$

(11)

The following equation is obtained for $V_D$:

$$V_D=V_{T}ln\left({\displaystyle \frac{{\mu }_4{C}_{OX4}{K}_4}{{\mu }_6{C}_{OX6}{K}_6}}\right)+{\displaystyle \frac{1}{m}}\left[|V_{TH0,6}|-V_{TH0,4}+({\alpha }_{T4}-{\alpha }_{T6})(T-T_0)-V_{REF1}\right].$$

(12)

Equivalent resistance $R_G$ of gate leakage transistor exhibits a CTAT characteristic [28]. Therefore, to achieve a temperature-compensated $I_{GATE}$, a CTAT voltage $V_D$ is obtained by adjusting the width and length ratio of $M_4$ and $M_6$.

The current $I_{GATE}$ flowing through the gate leakage transistor injects diode-connected MOS transistors to compensate for current $I_{DIO}$ drawn by parasitic reverse-biased PN junction. As a result, $I_{GATE}$ enhances temperature compensation effectively. Moreover, extracted from the self-biased current source $M_4$, it incurs no additional current consumption.

2.3. Voltage Level Shift of Diode-Connected Voltage Divider

Figure 4a illustrates a conventional voltage divider composed of two resistors connected in series. When a voltage drop occurs across a resistor with a certain resistance, current flows through the resistor. In the context of VR, it manifests as drawing current from the original branch. As a result, the poor TC of VR is caused adversely. Moreover, to minimize power consumption, resistors with higher resistance are typically chosen, necessitating a larger area.

To mitigate current shunting, operational amplifiers are often inserted between the original branch and the resistor divider. While this approach effectively reduces shunting due to the high input impedance of operational amplifiers, it significantly complicates and enlarges the circuit design.

Another approach involves employing diode-connected MOS transistors operating in the saturation region instead of resistors. As depicted in Figure 4b, neglecting the channel length modulation effect, the diode-connected MOS transistors can be seen as small-signal resistors with a resistance of ${\displaystyle \frac{1}{g_m}}$. According to the formula for the current of transistors in the saturation region, the transconductance $g_m$ can be obtained as follows:

$$g_m={\left.{\displaystyle \frac{\partial I_D}{\partial V_{GS}}}\right|}_{V_{DS,constant.}}=\mu C_{OX}K(V_{GS}-V_{TH}).$$

(13)

When equal currents flow through two series-connected and diode-connected MOS transistors of the same type, a divided voltage can be obtained. However, as depicted in Figure 4b, the drain and gate of the voltage divider are connected to the original branch, thus requiring an analog buffer to prevent shunting of the original branch.

This paper introduces an enhanced diode-connected NMOS voltage divider operating in the subthreshold region, capable of achieving voltage level shift for a voltage reference without using operational amplifiers and resistors. As depicted in Figure 4c, the current flowing through the diode-connected MOS transistors ($M_2$ and $M_3$) is supplied by a separate current source $M_1$, with only the gate of $M_2$ connected to the original branch. This configuration effectively prevents current extraction from the original branch, thereby successfully obtaining a voltage level converted voltage similar to the original output except for value.

The current flowing through $M_2$ and $M_3$ are equal. Therefore the following formula can be obtained:

$$\begin{array}{cc}\hfill {\mu }_2{C}_{OX2}{K}_2(m-1)V_T^2& \exp \left({\displaystyle \frac{V_{REF1}-V_{REF2}-V_{TH2}}{m{V}_T}}\right)\hfill \\ \hfill & ={\mu }_3{C}_{OX3}{K}_3(m-1)V_T^2\exp \left({\displaystyle \frac{V_{REF2}-V_{TH3}}{m{V}_T}}\right).\hfill \end{array}$$

(14)

Setting $K_2$ and $K_3$ equal, given that $M_2$ and $M_3$ are of the same transistor type, results in:

$$V_{REF2}={\displaystyle \frac{V_{REF1}}{1+m}}.$$

(15)

Furthermore, by substituting diode-connected transistors with different threshold voltages of varying types, different output voltages can be obtained through voltage dividers, as depicted in Figure 5.

2.4. Trimming Block for Leakage Current Compensation

In practical manufacturing, slight variations in production conditions are categorized as process variations, such as doping concentration, diffusion depth, and etching precision. These variations cause certain parameters of MOS transistors, like the threshold voltage $V_{TH0}$ at 0 K, to deviate from their theoretical values, thereby impacting the circuit’s performance.

To ensure the circuit operates within acceptable performance, five process corners are defined based on variations in channel ion implantation speed. These corners simulate deviations from theoretical values of MOS transistors for process variations.

The TC of VR usually deteriorates significantly across different process corners. To achieve theoretical zero TC for the reference voltage, the method of adjusting the width-to-length ratio between the MOS transistors of the active load has been proposed in the previous reports [30]. However, as shown in Equation (6), in addition to changing the width-to-length ratio of the transistors, the ratio of currents flowing through $M_5$ and $M_6$ in the active load can also be manipulated to achieve temperature compensation at each process corner. In this paper, as discussed in Section 2.2, the introduction of the gate leakage compensation current $I_{GATE}$ enables $I_{D5}=I_{D6}$ and also allows for an increase in the ratio of current through $M_6$ relative to $M_5$.

According to Equation (8), the temperature-compensated reference voltage varies at different process corners and can be expressed as:

$$V_{REF1}={\displaystyle \frac{1}{m-1}}\left[|V_{TH0,6}|\pm \Delta V_{TH0,6}-V_{TH0,5}\pm \Delta V_{TH0,5}-({\alpha }_{T5}-{\alpha }_{T6})T_0\right].$$

(16)

From Equation (12), $V_D$ can be expressed as the following formula after temperature compensation:

$$V_D={\displaystyle \frac{1}{m}}\left[\right|V_{TH0,6}|\pm \Delta V_{TH0,6}-V_{TH0,4}\pm \Delta V_{TH0,4}-({\alpha }_{T4}-{\alpha }_{T6})T_0-V_{REF1}].$$

(17)

At various process corners, the compensated current $I_{GATE}={\displaystyle \frac{V_D-V_{REF1}}{R_G}}$ varies due to different values of $V_D$ and $V_{REF1}$. Hence, it is necessary to adjust $R_G$ accordingly at each process corner to ensure the compensated current is suitable. This adjustment can be achieved by trimming the gate leakage transistor $M_7$.

As illustrated in Figure 6a, the compensated gate leakage current $I_{GATE}$ exhibits only minimal variation across the temperature range from −10 °C to 155 °C. However, the supply current displays an increasing trend with rising temperature, as depicted in Figure 6b. Specifically, the supply current remains below 81 pA across various process corners at $V_{DD}$ = 0.45 V and −10 °C, escalating to a maximum of 35 nA at 155 °C. At the same time, according to Equation (9), $I_{DIO}$ also rises with temperature, reaching approximately 200 pA at 155 °C.

Therefore, for enhanced temperature compensation, it is imperative to adjust the value of the gate leakage current at the appropriate temperature. At 155 °C, adjusting the compensated gate leakage current $I_{GATE}$ to be suitable for making $I_{D6}\ge I_{D5}$ needs it to be above 200 pA. However, $I_{GATE}$ in excess of 200 pA would have a great impact on the temperature compensation at low temperatures for the small current at low temperatures. Therefore, the compensated gate leakage current is suitable for adjustment and application at low temperatures.

In the temperature range selected for this circuit, since the temperature coefficient deterioration at high temperatures is the main cause of high TC at FF and SF corners, the proposed leakage current compensation technique is not fully applicable. Realizing this, we make the TC of the circuit at the FF and SF corners optimal by setting $I_{D5}=I_{D6}$ and resizing transistors $M_5$ and $M_6$ in the active load. Contrarily, the sharp deterioration of TC at a low temperature of −10 °C in the FS, TT, and SS corners is the cause of the high TC. Therefore, the appropriate compensated gate leakage current for FS, TT, and SS corners is adjusted by three-bit trimming so that $I_{D6}\ge I_{D5}$ at low temperatures is realized to enhance temperature compensation. Thus, the circuit is guaranteed to have the smallest possible TC at all process corners.

As depicted in Figure 7, the resistance adjustment of the gate leakage resistor $R_G$ is achieved by the three-bit trimming of gate leakage transistor $M_7$, where three NMOS switches ($M_{C0}$, $M_{C1}$, and $M_{C2}$) are controlled to select the conduction of the gate leakage transistors ($M_{T0}$, $M_{T1}$, and $M_{T2}$).

3. Simulation Results and Discussion

To verify the performance of the proposed voltage reference, a series of post-simulations have been implemented in a standard 65 nm process. The device parameters of the circuit are listed in

Table 1. Device parameters of the proposed CMOS voltage reference.

Component	W/L (μm/μm)	Component	W/L (μm/μm)
$M_1$	2.50/1.50	$M_4$	2 × 1.49/3.05
$M_2$	0.18/9.70	$M_5$	1.70/1.19
$M_3$	0.18/9.70	$M_6$	2.91/0.185

, and its layout is shown in Figure 8, with an area of 3481.28 μm² (86.47 μm × 40.26 μm).

Different from the traditional bandgap voltage reference, in the ideal case without process variations, the condition of subthreshold voltage reference theoretically achieving zero TC is $I_{D5}=I_{D6}$ at every corner, as described in Section 2.1. However, the current flowing through $M_5$ and $M_6$ is not equal due to the presence of the reverse-biased diode current. As shown in Figure 6b, the supply subthreshold current is small at −10 °C so that the reverse-biased diode current drawing from $I_{D5}$ causes a large deviation in $I_{D5}=I_{D6}$. Hence, as shown in Figure 9, Figure 10 and Figure 11, the performance of the voltage reference deteriorates sharply at temperatures lower than minus 10 °C.

The proposed leakage current compensation technique enhances VR’s temperature compensation at low temperatures, achieving a low TC across a wide temperature range of −10∼155 °C. As shown in

Table 2. The characteristics of $V_{REF1}$ at room temperature for different process corners.

Corner	TT	SS	FF	FS	SF
$V_{REF1}$	276	269	287	307	246
$T{C}_{max}$ w/o current compensation (ppm/°C)	74.59	184.71	33.11	103.35	71.62
$T{C}_{max}$ w/i current compensation (ppm/°C)	20.40	72.74	/	48.74	/
Power supply rejection ratio (PSRR)@$V_{DD}$ = 1.8 V and 10 Hz (dB)	−76.70	−67.80	−85.15	−80.97	−72.49
PSRR@$V_{DD}$ = 1.8 V and 1 MHz (dB)	−39.27	−38.97	−35.89	−38.46	−35.56
Line sensitivity (LS) from 0.45 to 2.5 V (%/V)	0.077	0.174	0.109	0.287	0.118
$Powe{r}_{min}$ of total circuit (pW)	53.83	17.42	203.17	102.32	33.53

, after making the temperature compensation of the circuit at the FF and SF corners optimal, the TC of $V_{REF1}$ is as high as 184.71 ppm/°C at the SS process corner and as low as 33.11 ppm/°C at the FF process corner without trimming. The temperature characteristics at TT, FS, and SS corners can be enhanced by trimming the leakage current compensation circuit.

Figure 9 shows the TCs of $V_{REF1}$ and $V_{REF2}$ at the TT process corner with and without the leakage current compensation. The results illustrate that the leakage current compensation technology proposed in this paper can effectively improve the TC of $V_{REF1}$ from 74.59 ppm/°C to 20.40 ppm/°C and the TC of $V_{REF2}$ from 70.81 ppm/°C to 42.15 ppm/°C after trimming, respectively. According to the figure, it has also been clearly demonstrated that the implemented leakage current compensation technique primarily enhances temperature compensation at low temperatures.

As shown in Figure 10 and Figure 11, the maximum TC at SS and FS corners is effectively decreased by 111.97 ppm/°C and 54.61 ppm/°C, respectively, so that the TC range of $V_{REF1}$ at different process corners is controlled within 20.40∼72.74 ppm/°C.

Figure 12 shows the fluctuation of $V_{REF1}$ and $V_{REF2}$ with the variation in supply voltage, where their LS are 0.077%/V and 0.103%/V, respectively. Moreover, the minimum supply voltage for the entire circuit is 0.45 V.

Figure 13 shows the start-up waveform of the circuit, which can start on its own due to the effect of leakage current biasing. The settling times of $V_{REF1}$ and $V_{REF2}$ at the TT process corner are 13.58 $\mu$s and 22.94 $\mu$s, respectively. Therefore, it has better startup performance.

In Figure 14, the current consumption of the proposed design from 0.45 V to 2.5 V at the TT corner and room temperature is shown. Under the minimum supply voltage of 0.45 V, the circuit can achieve an ultra-low power consumption of 53.83 pW. The supply current exhibits a linear increase of 3.7 pA/V with the supply voltage, indicating that the subthreshold current generated by the self-biased current sources $M_1$ and $M_4$ remains relatively constant with the variation in the supply voltage.

As depicted in Figure 15, the PSRR of $V_{REF1}$ and $V_{REF2}$ at 10 Hz is −76.70 dB and −80.46 dB, respectively. Without using output capacitance, the PSRR at 1 MHz is −39.27 dB and −56.13 dB, respectively.

Thermal noise constitutes a major noise source in this circuit due to the large channel resistance of MOS transistors biased in the subthreshold region. Moreover, the 1/f noise is also the dominant noise contribution for $V_{REF1}$, attributable to the use of small-size MOS transistors $M_6$. Figure 16 depicts the simulated power spectral density and output noise of two output voltages without any additional load capacitance. The integrated noises of $V_{REF1}$ and $V_{REF2}$ from 0.1 Hz to 100 Hz are 22.65 $\mu$V and 35.50 $\mu$V, respectively.

To explore the independence of $V_{REF1}$ and $V_{REF2}$ to process variations, post-simulation Monte Carlo simulations of 1000 samples are performed under process and mismatch. Figure 17a,b show their coefficient of variation $\sigma /\mu$ of 2.39% and 2.54%, demonstrating good stability.

Figure 17c shows that the average LSs of $V_{REF1}$ and $V_{REF2}$ are 0.103%/V and 0.144%/V, respectively, and each of their $\sigma /\mu$ are 45.63% and 39.58%. As shown in Figure 17d, the Monte Carlo simulation result of total power is 55.64 pW at room temperature, and its $\sigma /\mu$ is 34.67%.

Table 3. Comparison with state-of-the-art voltage references.

Paper	TCAS-I [30]	TCAS-I [31]	TVLSI [1]	CICC [32]	TCAS-II [33]	MDPI a [34]	This Work a
Year	2020	2022	2022	2022	2023	2024	2024
Technology (nm)	65	65	180	180	65	180	65
Active Area ($\mu$m2)	52,200	42,500	5379	16,900	8400	2358.8	3481.28 (1740.64 b)
$V_{DD,min}$ (V)	0.5	0.5	0.6	0.65	0.4	0.5	0.45
Temperature Range (°C)	−40∼120	−40∼120	−40∼80	0∼130	−20∼80	0∼100	−10∼155
Power (pW)	36,000	24,000	150	809	56,700	28.8	53.83 (26.92 c)
$V_{REF}$ (mV)	495	503	350	286	107.2	195.5	276    128
Average TC (ppm/°C)	42	32	72	19.29	79.4	26.7	15.86    34.07
LS (%/V)	0.64	0.66	0.093	0.08	0.54	NA	0.077    0.103
PSRR [≤100 Hz] (dB)	−50@DC	−50@DC	−39@100 Hz	NA	−66.50@10 Hz	−72 d@10 Hz	−76.70@10 Hz    −80.46@10 Hz
PSRR [≥1 kHz] (dB)	−50@DC	−50@DC	−35@1 kHz	NA	NA	−33.3 d@10 kHz	−39.27@1 MHz    −56.13@1 MHz
Integrated Noise ($\mu$V)	NA	NA	NA	NA	12.70@10∼100 Hz	41.80@0.1∼100 Hz	22.65@0.1∼100 Hz    35.50@0.1∼100 Hz

^a Post-simulation. ^b Average chip area for a single reference voltage. ^c Average power consumption of a single reference voltage. ^d Using decoupling capacitor.

presents the performance comparisons with state-of-the-art subthreshold voltage reference fabricated in 180 nm and 65 nm processes. In this study, the post-simulation Monte Carlo analyses are employed to ensure that the comparisons are made as fairly as possible.

4. Conclusions

In this paper, a picowatt and dual-output CMOS VR integrated with gate leakage current compensation and diode-connected voltage divider is proposed and simulated in a 65 nm CMOS process. Comprehensively presented are the circuit configuration, operational principles, and simulation results. Particular emphasis is placed on achieving a low TC across a wide temperature range through leakage current compensation technology, which is mainly used for enhanced temperature compensation at low temperatures. A voltage divider, comprising two series-connected and diode-connected MOS transistors supplied by a separate current source, is introduced. This configuration achieves voltage level shift without using analog buffers or shunting from the original branch. Moreover, a trimming block is proposed to ensure the voltage reference is practicable at different process corners. With its superiority of a wide temperature range, ultra-low power consumption, dual outputs, and low supply voltage, the proposed CMOS VR is well suited for applications requiring several stable DC sources in systems with energy harvesting technology.