A Monostable Physically Unclonable Function Based on Improved RCCMs with 0–1.56% Native Bit Instability at 0.6–1.2 V and 0–75 °C
Round 1
Reviewer 1 Report
Well written manuscript with high-quality figures and interesting proposal. One of the major strengths of this work is the validation through silicon measurements.
I have only two minor comments/suggestions:
1) Fig. 3b showing the logical speckle diagram over the 21 chips should be enlarged to improve its readability and the location of unstable cells could be indicated in this representation;
2) from what I understand, the comparison table (i.e., Table 3) reports results referred to 5 chips selected among the ones with lower BER in typical condition. The authors should better clarify and at least point out this aspect in Section 6 when discussing the comparison with the state of the art.
Comments for author File: 
Comments.pdf
Author Response
The paper is very interesting and well written. I've particulary appreciated the introduction that is a good overview of the possible approaches, issues and challenges for the non experts in PUF. Also the architecture is well presented and described; following some comments:
1 - Regarding the loop-gain (Ae) the 1/2 factor, i suppose is given by the impedance observed at the gate of Mpo2 (or Mn02) and, in particular, is due to the parallel of the equivalent resistances of the cascode Mpgb1 - Mpgb2 and the cascode Mnm2-Mnm1. The hypothesis is that the two resistances are more or less equal, is it correct? If yes, i suggest to include and comment this hypothesis in the paper to justify the 1/2 factor since the size of the transistors in the two cascode stages is different and consequently the value of the equivalent resistors.
Reply: We thank the reviewer for this comment. Yes the reviewer is right. We have better clarified this point in the revised manuscript with the following sentence: “It has to be noted that the factor 1/2 in Eq. 3 results from the assumption that the equivalent resistance of each one of the error amplifiers Mp_{gb1(2)} and Mn_{gb1(2)} is equal to the equivalent resistance of the respective biasing current source Mn_{m1(2)} or Mp_{m1(2)}.
2 - Always in the loop-gain, gmim1 in (3), is it correct? shouldn't be gmgb1?
Reply: We thank the reviewer for this comment, we have corrected the Eq. 3 in the revised manuscript.
3 - Pag. 5, row 154. It's not clear (to me) what does it mean "good bias", maybe is possible to explain it. In addition, would be interesting to comment how Iref has been implemented in the measurements.
Reply: We thank the reviewer for this comment which allowed us to better clarify the meaning of the word bias, which in this case has to be intended in a statistical sense. The following sentence has been added in the revised manuscript:
“The main metrics considered in this work to evaluate the performace of a generic n-bit PUF are: the bias of the response (i.e. the mean value in percentage of the number of 1s (0s) which ideally is 50%), the intra and inter Hamming Distance ( HD_{intra}) and (HD_{inter}) which respectively evaluate how many bits of the response in percentage varies with respect to a nominal value over different chip realizations [1].”
The current Iref is important to set the bias current of the circuit and determines its power consumption. Iref has been implemented as a NMOS transistors operating in the triode region, whose equivalent resistance is set through the gate voltage Vg. This allows to control Iref by using a feedback loop. For the measurements we have accurately set Iref by setting Vg through a Teledyne T3PS43203P programmable voltage source.
4 - Pag 12, row 250, "evuation" should be "evaluation" instead.
Reply: We thank the reviewer, we correct the typo in the revised manuscript.
Reviewer 2 Report
The paper is very interesting and well written. I've particulary appreciated the introduction that is a good overview of the possible approaches, issues and challenges for the non experts in PUF. Also the architecture is well presented and described; following some comments:
1 - Regarding the loop-gain (Ae) the 1/2 factor, i suppose is given by the impedance observed at the gate of Mpo2 (or Mn02) and, in particular, is due to the parallel of the equivalent resistances of the cascode Mpgb1 - Mpgb2 and the cascode Mnm2-Mnm1. The hypothesis is that the two resistances are more or less equal, is it correct? If yes, i suggest to include and comment this hypothesis in the paper to justify the 1/2 factor since the size of the transistors in the two cascode stages is different and consequently the value of the equivalent resistors.
2 - Always in the loop-gain, gmim1 in (3), is it correct? shoudn't be gmgb1?
3 - Pag. 5, row 154. It's not clear (to me) what does it mean "good bias", maybe is possible to explain it. In addition, would be interesting to comment how Iref has been implemented in the measurements.
4 - Pag 12, row 250, "evuation" should be "evaluation" instead.
Author Response
The manuscript describes a new implementation of a Physically Unclonable Function in 130m CMOS
technology. The idea is interesting and the results are good, but there are some weakness points that
should be corrected to improve the quality of the paper. Some comments and observations are reported in the following.
1 - “Uniqueness” and “Reliability”: please use always lowercase or uppercase format for these two quantities (row 52).
Reply: We thank the reviewer, we update the format of these words in the revised manuscript.
2 - “complimentary to absolute temperature” should be “complementary to absolute temperature” (row 65).
Reply: we corrected the typo in the revised manuscript.
3 - Correct “the the” on row 68.
Reply: we corrected the typo in the revised manuscript.
4 - Please, provide a definition for the entropy.
Reply: we consider the Shannon Entropy. This has been clarified in the revised manuscript.
5 - Using Blackman’s formula, with the controlled current source gmngb1vgsngb1 as a reference, the output resistance of the regulated cascode current mirror Routn is the output resistance of the dead network (the one with gmngb1vgsngb1), multiplied by the 1 plus the return ratio of the controlled current source, almost equal to AEn. Thus, we should have:
which does not correspond to eq. (2), where the terms rdsno2 and rdsno1 are not multiplied by (1+AE). I agree that this does not cause a large error in the evaluation of Routn, but the expression is not correct. Moreover, the gain of the boosting amplifier AEi (a cascoded common source with a cascode active load) must be necessarily dependent on the transconductance of the common source MOSFET Migb1: instead in eq. (3) gmigb1 does not appear at all, which is impossible. Thus, I think that the authors should check the correctness of these two equations. Furthermore, it is better to avoid subscripts in the expression gmi/gdsi ≈ Avi, since in eq. (5) only a generic Av has been used. I’d avoid also the factor 4 in the denominator of the expression in eq. (5), since the equation reports only a proportionality relationship between the two members and the factor 4, in my opinion, is not relevant.
- Reply: We thank the reviewer for this comment since it gave us the opportunity to revise all the formulas concerning the output resistance. For what concerns Eq. 3, the reviewer is right, there was a typo, which has been corrected in the revised manuscript. Coming to equation (2), we acknowledge that the expression was approximated (we neglected the factor 1 with repsect to Ae in deriving the small signal equivalent circuit), however also the expression using the Blacman’s formula results approximated. We have therefore performed the full node equations analysis on the complete small signal equivalent circuit and reported the correct formula in the revised manuscript. The reported expression has been also checked against a symbolic solver.
The factor 1/2 in equation (3) and the factor 1/4 in equation (5) are due to the assumption of considering equal to each other the resistances in parallel involved in the computations. This has been better explained in the revised manuscript.
6 - Furthermore, it is better to avoid subscripts in the expression gmi/gdsi ≈ Avi, since in eq. (5) only a generic Av has been used.
- Reply: we thank the reviewer, however, we believe that for what concerns Eq.2 and Eq. 3 it is better for the reader to see from which transistors this factor is given and if we delete subscripts this information will be lost.
7 - I’d avoid also the factor 4 in the denominator of the expression in eq. (5), since the equation reports only a proportionality relationship between the two members and the factor 4, in my opinion, is not relevant.
- Reply: the Eq. 5 with the factor 4 takes into account the parallel between NMOS and PMOS, we explained better this point in the revised manuscript.
8 - The nominal power supply voltage for the ST 130nm CMOS technology is 1.2V, to my knowledge. Here, it has been assumed to be 0.8V (row 151): is it a special flavor of the technology or there are different motivations for this assumption?
- Reply: we confirm that the nominal supply voltage is 1.2 V, however, since our aim was to minimize power consumption we designed the PUF at a lower supply voltage. Many other PUF designs make use of supply voltages lower than the nominal one as can be seen inspecting the comparison table at the end of the manuscript.
9 - To better appreciate the performance in terms of unstable cells and biasing, I propose to split Figure 3 in two different figures, so that the horizontal scales can be better defined in the two cases. The same can be done also for Figure 4.
- Reply: we thank the reviewer for this comment, we changed Fig. 3 and Fig. 4 in the revised manuscript to show more detail about the unstable cells and biasing.
10 - “The number of unstable cells in typical condition has been found to be about μ≈0.856% with σ≈1.533%” Please, specify explicitly that this mean value and this sigma refer to the number of the unstable cells per chip and that the mean and the sigma has been evaluated on the sample of 21 chips.
- Reply: we explicitly specified that the mean and the sigma have been evaluated referring to 21 chip samples.
11- Moreover, the definition of unstable cell has been given on row 206, after the concept has been used. Also, providing a clear definition of HDintra and HDinter can be useful.
- Reply: we introduce the definition of HD inter and HD intra in the revised manuscript.
12 - Maybe “Concerning the autocorrelation function” or “As far as the autocorrelation function is concerned” sounds better than “For what concern the autocorrelation function” on row 196.
- Reply: we thank the reviewer, we recognize the suggestion and we changed the sentence in the revised manuscript.
13 - What is “1-BER” on row 202? Please, define the acronym of BER when it is used for the first time.
-Reply: we thank the reviewer, in the revised manuscript we have defined the BER (Bit Error Rate) .
14 - The concept of “minimum area” for a technology is not clear to me: it is the size of the circuit when minimum size transistors are used everywhere and no interconnections have been considered? Please, give details about that.
- Reply: We thank the reviewer for this comment since it gave us the opportunity to better clarify this aspect in the revised manuscript. In order to normalize the area across different technology nodes and different feature sizes, we refer to the minimum area as the square of the minimum feature size of the technology node. For example in a 130 nm technology the minimum area is (130nm)^2.
15 - Correct “evuation” on row 250.
- Reply: we corrected the typo in the revised manuscript.
16 - In Table II there are symbols undefined or that need explanation: for instance, “F++ @130nm”, “Area/bit normalized”, “⊛”, “+”. Moreover, there are numbers reported in bold: why? Last, correct [# of evaluations].
- Reply: we better clarified these symbols in the revised manuscript.
Reviewer 3 Report
Please, see the attached file "Comments.pdf"
Comments for author File: Comments.pdf
Author Response
1 - Fig. 3b showing the logical speckle diagram over the 21 chips should be enlarged to improve its
readability and the location of unstable cells could be indicated in this representation.
- Reply: we thank the reviewer for this comment, we updated Fig. 3b in the revised manuscript;
2 - from what I understand, the comparison table (i.e., Table 3) reports results referred to 5 chips
selected among the ones with lower BER in typical condition. The authors should better clarify and
at least point out this aspect in Section 6 when discussing the comparison with the state of the art.
- Reply: We have better explained the reason of our choice and the focus of the analysis in the revised manuscript. For what concerns the comparison table, we used results according to other works. Furthermore, in order to make a fair comparison, we used the mean value of the Bit Error Rate taken from 21 chips and also the mean value of Unstable Cells taken from 21 chips. FOMber and FOMub have been re-computed by considering all the 21 chip samples, and are still the best in literature, outperforming all other works. Also this point has been better clarified in the revised manuscript.
Round 2
Reviewer 3 Report
I would like to thank the authors for addressing all the comments and observations made in the first round of revision. By the way, I just would like to acknowledge the correctness of equation (2). Blackman's formula provides exactly the same result for the output resistance: in the formula I wrote in the previous revision round, the return ratio of the circuit (referred to the dependent voltage source which represents the amplifier Aen) must contain also the gain between the voltages on the source and on the gate of Mio2, which is not unity. If one takes into account the gain of this non-ideal source follower in the gain boosting loop, the results is exactly the one reported in eq. (2).
