Reduced-Complexity Tracking Algorithms on Chip for Real-Time Location Estimation
Abstract
:1. Introduction
2. Kalman Filtering Algorithm
3. Alpha-Beta (α-β) Filtering Algorithm
- (1)
- Prediction step (Time update phase):
- (2)
- Estimation step (Measurement update phase):
4. The Proposed Filtering Algorithm Based on Chip
4.1. DKF and PKF Filtering Algorithm
4.2. Revise Covariance R and Q in Different Environments
4.3. Judgment-Standard for Conditional Equation
5. The Proposed VLSI Architecture and Implementation
5.1. The Algorithm Implementation and Pipeline Architecture
5.2. Computation of Kalman Gain and α-β Module
5.3. Update State Module
5.4. Predicted State Module
5.5. Input Table Module
6. The Implementation of Chip Results and Measurement
6.1. Data Comparison with FPGA Approach
6.2. Simulation on FPGA DE2-115
6.3. Implementation of Chip
6.4. Measurement of Chip
7. Conclusions
Author Contributions
Funding
Acknowledgments
Conflicts of Interest
References
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DKF (Difference Kalman Filter) | PKF (Percentage Kalman Filter) | |
---|---|---|
Method of judgment | Using differences to make judgment | Using percentages to make judgment |
Using situation | Smaller KG in the environment | Larger KG in the environment |
Variance V | Steady KG of KF | KG of 4.0/ Iteration Times | KG of 8.0/ Iteration Times | KG of 16.0/ Iteration Times | KG of 32.0/ Iteration Times |
---|---|---|---|---|---|
5 | 5830 | 5830/26 | 5830/25 | 5830/22 | 5826/21 |
10 | 5053 | 5053/29 | 5053/28 | 5053/23 | 5013/20 |
15 | 4638 | 4638/32 | 4638/30 | 4638/24 | 4584/19 |
Number of Slice Registers | Number of Slice LUTs | Number of IOBs | Processing Time (One Clock) | |
---|---|---|---|---|
Bai’s Approach [20] | 36,689/149,760 (24%) | 28,367/149,760 (18%) | 391/680 (57%) | 0.00468 ns |
Rawal’s Approach [37] | 2696/393,600 (1%) | 17,335/196,800 (8%) | 166/600 (27%) | - |
The Proposed Approach | 8739/114,480 (8%) | 9365/117,053 (8%) | 102/529 (19%) | 0.003007 ns |
Logic Element Usage by Number of LUT Inputs | Total Registers | Total I/O Pins | Embedded Multiplier 9-Bit Elements | |
---|---|---|---|---|
Chen’s Approach [18] | 18,650/114,480 (16%) | 2178 | 120/529 (23%) | 192/532 (36%) |
Zhang’s Approach [18,19] | 22,176/114,480 (20%) | 1687 | 102/529 (19%) | 144/532 (27%) |
The Proposed Approach | 8739/114,480 (8 %) | 929 | 102/529 (19%) | 60/532 (11%) |
Processing Time (One Clock) | Stage | Points | Cycles | Total Processing Time (One Cycle) | |
---|---|---|---|---|---|
Chen’s Approach [18] | 0.002772 ns | 6 | 1800 | 10,800 | 29.9376 ns |
Zhang’s Approach [18,19] | 0.002800 ns | 6 | 1800 | 10,800 | 30.2400 ns |
The Proposed Approach | 0.003007 ns | 4 | 1800 | 1804 | 5.4246 ns |
Traditional Software Program (CPU i3/Ram 8 GB) | Traditional Software Program (CPU i7/Ram 16 GB) | The Proposed Approach (Hardware Design and FPGA) | ||||
---|---|---|---|---|---|---|
Algorithm | KF | α-β | KF | α-β | KF | α-β |
Executing Time | 0.8235 ns | 0.07358 ns | 0.05115 ns | 0.009521 ns | 0.03407 ns | 0.003007 ns |
Method | KF Approach | α-β Approach Based on KF Coeff. | α-β Approach α= 1 β = 1 | α-β Approach α= 0.75 β = 0.75 | α-β Approach α= 0.5 β = 0.5 | α-β Approach α= 0.25 β = 0.25 | |
---|---|---|---|---|---|---|---|
CDF | |||||||
90% | 3.65 m | 3.66 m | 6.82 m | 6.02 m | 5.42 m | 5.21 m | |
50% | 2.00 m | 2.01 m | 3.71 m | 3.19 m | 2.92 m | 2.81 m |
Specification | Spec. |
---|---|
Technology | TSMC 0.18 um CMOS Mixed Signal RF General Purpose Standard Process FSG AI 1P6M1.8&3.3 V |
Process (μm) | 0.18 |
Gate Counts | 22.84 k |
Frequency (Hz) | 83.33 M |
Chip Size (μm2) | 582.63 × 580.23 |
Power Supply (Volts) | 1.8 |
Operation Temperature (°C) | 0~125 |
Power Consumption (W) | 3.86 m |
Packing Type | 32 S/B |
Chip Pads | GPIO |
---|---|
Clk | [0] |
Reset | [4] |
Delta_k | [8] |
X_Hat[12:0] | [11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35] |
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Chiou, Y.-S.; Chen, S.-L.; Chen, W.-T. Reduced-Complexity Tracking Algorithms on Chip for Real-Time Location Estimation. Electronics 2023, 12, 739. https://doi.org/10.3390/electronics12030739
Chiou Y-S, Chen S-L, Chen W-T. Reduced-Complexity Tracking Algorithms on Chip for Real-Time Location Estimation. Electronics. 2023; 12(3):739. https://doi.org/10.3390/electronics12030739
Chicago/Turabian StyleChiou, Yih-Shyh, Shih-Lun Chen, and Wei-Ting Chen. 2023. "Reduced-Complexity Tracking Algorithms on Chip for Real-Time Location Estimation" Electronics 12, no. 3: 739. https://doi.org/10.3390/electronics12030739
APA StyleChiou, Y.-S., Chen, S.-L., & Chen, W.-T. (2023). Reduced-Complexity Tracking Algorithms on Chip for Real-Time Location Estimation. Electronics, 12(3), 739. https://doi.org/10.3390/electronics12030739