Study of Single Event Latch-Up Hardness for CMOS Devices with a Resistor in Front of DC-DC Converter

Round 1

Reviewer 1 Report (Previous Reviewer 2)

The article seems better, and my comments have been addressed, please only review Figure 3, in a traditional buck converter the ground (in R2) is the same as the reference of the input voltage. 

Author Response

We sincerely appreciate the reviewers for their time to read our manuscript and provide valuable suggestions. We have carefully considered all comments from the reviewers and revised our manuscript accordingly.Please see the attachment below for detailed responses.

Author Response File: Author Response.pdf

Reviewer 2 Report (Previous Reviewer 4)

The proposed method is interesting. The grammar can be checked to improve the quality of the manuscript.

Author Response

我们衷心感谢审稿人抽出宝贵时间阅读我们的稿件并提供宝贵的建议。我们仔细考虑了审稿人的所有意见，并相应地修改了我们的稿件。有关详细答复，请参阅下面的附件。

Author Response File: Author Response.pdf

Reviewer 3 Report (Previous Reviewer 1)

1. Confirm that all the references listed have been sequentially and incrementally cited in the text.

2. In Fig. 1, is Rt in parallel or series connection to the devices? why?

3. The latch-up event generally presents in CMOS devices. However, the proposed method is to add an buck converter to COMS devices. Is it possible that the latch-up event in current is suppressed by the buck converter? If yes, how to do in practical applications (always a buck converter required)? If not, explain it.

4. How about the power of the pulsed Laser for the experiments?

Author Response

我们衷心感谢审稿人抽出宝贵时间阅读我们的稿件并提供宝贵的建议。我们仔细考虑了审稿人的所有意见，并相应地修改了我们的稿件。有关详细答复，请参阅下面的附件。

Author Response File: Author Response.pdf

Round 2

Reviewer 3 Report (Previous Reviewer 1)

This version can be acceptable for publication.

This manuscript is a resubmission of an earlier submission. The following is a list of the peer review reports and author responses from that submission.

Round 1

Reviewer 1 Report

1. The main idea behind this paper is not clear. Many questions in the following should be answered.

a) What is Rt in (2)? What is Rp1 in (4)? Why to define them?

b) In (3), how to define the conversion efficiency u? Is D controllable by authors? how?

c) I really don't know how to obtain equations (3)-(6) and (8)-(9).

d) From Fig. 2, what do we find? what do the different zones represent?

2. There is a serious problem in the design of Fig. 1(b). The input voltage of the DC converter is varied with changes in current (power) Id. This ususally gives a large fluctuation in output voltage of the DC converter. Then, the devices get an ripple DC voltage and perform in a bad condition.

3. It is difficult for readers to know what Figs. 5 and 6, and Table 3 give.

4. Line #113, [45]-[48] are not listed in References.

Author Response

We appreciate the time and effort that you dedicated to providing feedback on our manuscript and is grateful for the insightful comments on and valuable improvements to our paper. We have incorporated most of the suggestions made by the reviewer. Please see the attachment. If there are any other modifications we could make, we would like very much to modify them and we really appreciate your help. We hope that our manuscript could be considered for publication in the journal. Thank you very much for your help.

Author Response File: Author Response.pdf

Reviewer 2 Report

You are dealing with a very particular topic in circuits. The introduction must be improved; because due to imperfect English and very short explanations, some questions arise; you introduce several concepts without explaining them. Please explain in the introduction what is the single event effect from the circuit point of view (does a transistor get suddenly closed?), and also the solutions. You mentioned the in a few lines with some references, but please explain the meaning of each of them from the circuit point of view.

Please introduce a Figure indicating the way to connect the resistor, with a schematic diagram (Figure 1 is very poor). Please also mentioned the references that use this resistor in that way, or please clarify if the resistor interconnection is a proposal of this manuscript.

I must confess that the article is not clear. Please help us to understand your contribution; is it just increasing the value of a resistor? Why is it not obvious for people that work with those circuits? The mathematical analysis seems elementary.

Please also discussed the effects of that resistor on the efficiency of the system, which is very important from the energy point of view.

Why did you choose the particular experiment with the laser? And please describe how did you get the measurements, including the equipment used.

The English grammar is acceptable. Still, I have included some particular suggestions. Some are not incorrect but uncommon (the English revision is not exhaustive).

On page 1, line 9, it says:

“have distinct single event latch-up (SEL) problem in aerospace.”

- I suggest changing it for:

“have distinct single event latch-up (SEL) problems in aerospace.”

On page 1, line 11, it says:

“due to reduction of latching current”

- I suggest changing it for:

“due to the reduction of latching current”

On page 1, line 12, it says:

“In the circuit containing DC-DC buck converter”

- I suggest changing it for:

“In circuits containing a DC-DC buck converter”

On page 1, line 35, it says:

“for CMOS devices in the aerospace application”

- I suggest changing it for:

“for CMOS devices in aerospace applications”

On page 1, line 51, it says:

“according to devices operating characteristic”

- I suggest changing it for:

“according to the devices operating characteristics”

On page 1, line 52, it says:

“the resistor does not interfere with normal operation of devices”

- I suggest changing it for:

“the resistor does not interfere with the normal operation of devices”

On page 1, line 53, it says:

“when devices occurs the SEL”

- I suggest changing it for:

“when devices occur the SEL”

On page 1, line 55, it says:

“effectively reduce the latch-up hazard of devices by limiting devices current.”

- I suggest changing it for:

“effectively reduces the latch-up hazard of devices by limiting the devices' current.”

On page 1, line 58, it says:

“Conventional method result in a small range of resistor due to the constraint of small voltage tolerance in condition 1, which may lead to the resistor that satisfy condition 2 not being present.”

- I suggest changing it for:

“The conventional method results in a small range of resistors due to the constraint of small voltage tolerance in condition 1, which may lead to the resistor that satisfies condition two not being present.”

On page 1, line 58, it says:

“In view of the problem that conventional method fail”

- I suggest changing it for:

“In view of the problem that the conventional method fails”

Author Response

我们感谢您为我们的稿件提供反馈所付出的时间和精力，并感谢您对我们论文的深刻评论和有价值的改进。我们采纳了审稿人提出的大部分建议。请参阅附件。如果我们可以进行任何其他修改，我们非常希望对其进行修改，我们非常感谢您的帮助。我们希望我们的手稿可以考虑在期刊上发表。非常感谢您的帮助。

Author Response File: Author Response.pdf

Reviewer 3 Report

The paper presents a circuit-level Event Latch-up hardness by placing the limiting resistor in front of a DC-DC buck converter.

Besides the analysis of the voltage tolerance, the authors carried out laser experiments to validate the concept.

Author Response

我们感谢您为我们的稿件提供反馈所付出的时间和精力，并感谢您对我们论文的深刻评论和有价值的改进。我们采纳了审稿人提出的大部分建议。请参阅附件。如果我们可以进行任何其他修改，我们非常希望对其进行修改，我们非常感谢您的帮助。我们希望我们的手稿可以考虑在期刊上发表。非常感谢您的帮助。

Author Response File: Author Response.pdf

Reviewer 4 Report

I have some comments that are expected to be addressed in the manuscript as follows

1. The overview in the introduction should be extended.   

2. It will be better to prove the performance of the proposed method, the comparison between the proposed method and existing methods can be given.

Author Response

我们感谢您为我们的稿件提供反馈所付出的时间和精力，并感谢您对我们论文的深刻评论和有价值的改进。我们采纳了审稿人提出的大部分建议。请参阅附件。如果我们可以进行任何其他修改，我们非常希望对其进行修改，我们非常感谢您的帮助。我们希望我们的手稿可以考虑在期刊上发表。非常感谢您的帮助。