On-Chip Bus Protection against Soft Errors

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

This paper conducts a review on the topic of on-chip bus protection against soft errors. The paper is well-written and well-organized. It is informative and lets readers and other researchers have a great overview of the existing methods and their characteristics. To this reviewer, such a review paper is worthy of publication. However, I have still a couple of comments to the authors:

1- (Suggestion): The paper would be more comprehensive if it included some more protection techniques. Could the authors add other conventional or state-of-the-art methods to their comparison list?

2- Table 1 provides detailed information about the properties of each method. However, it seems that the paper lacks some quantitative analyses to reach a more concrete conclusion. It is expected that such a review paper gives a deeper insight into the usefulness of each method by presenting more comparative charts and diagrams.

Author Response

Thank you very much for your positive feedback and for your effort and time spent reviewing our paper.

1 - We added a reference to a recently published article (35) about monitoring memory errors with a brief description. Unfortunately, we have not found any other published bus-protection approach.

2 - We agree that a comparison based on quantitative analysis would be more informative, but it is very complicated to make such a comparison that would be fair and not apples to oranges comparison. All these approaches depend on many design targets (operating frequency, performance,...) and implementation details (number of pipeline stages, bus protocol, instruction set,...). Our goal was to provide a high-level big picture without going into too much detail. This review should serve as a starting point, where the designer/architect has the pros and cons summary.

Reviewer 2 Report

Comments and Suggestions for Authors

This paper presents a comprehensive review of the bus protection method against soft errors, specifically addressing information redundancy, temporal redundancy, and spatial redundancy. The study is well-structured and effectively presented. However, there are a few recommendations that could enhance this paper:

1. Figure 3 appears to lack coherence; it may be advisable to remove this figure.

2. Some CPU and memory protection mechanisms, such as memory integrity at the CPU end, can help to protect and monitor the bus security/faults. More review is required to focus on these works.

Author Response

Thank you very much for your positive feedback and for your effort and time spent reviewing our paper.

1 - We removed Figure 3.

2 - We added a reference to a recently published article (35) about monitoring memory errors with a brief description. The paragraph following the new Figure 3 explains why additional monitoring components may not be the correct approach.

Reviewer 3 Report

Comments and Suggestions for Authors

  This article includes a review of the different methods of protection against soft errors. This reviewer has the following comments:   A section of previous literature is necessary.   Figures must be vectorized.   What are the latest proposals for protection against errors, mention more new literature.   When you mention "authors" it seems like you are talking about yourselves.   Make an introductory paragraph for section 4   I would like to see the comparison table of the different protection techniques focused on the resources used and power consumed.   Last paragraph is not a conclusion of this paper

Author Response

Thank you very much for your feedback and for your effort and time spent reviewing our paper.

1 - As the article progresses, we try to reference appropriate techniques for bus/memory protections and already published comparisons. We think a separate literature review would break the article's structure.

2 - We added a reference to a recently published article (35) about monitoring memory errors with a brief description. We have not found other published protection approaches that would benefit this article. 

3 - The sentences were reformulated not to contain the word "authors". 

4 - The last paragraph of section 4.0 has been moved to the beginning of section 4.0.

5 - We agree that a comparison based on quantitative analysis would be more informative, but it is very complicated to make such a comparison that would be fair and not apples to oranges comparison. All these approaches depend on many design targets (operating frequency, performance,...) and implementation details (number of pipeline stages, bus protocol, instruction set,...). Our goal was to provide a high-level big picture without going into too much detail. This review should serve as a starting point, where the designer/architect has the pros and cons summary.

6 - We have moved this paragraph to a separate "Future Directions" section.

Reviewer 4 Report

Comments and Suggestions for Authors

This paper reviews the main existing bus-protection approaches and summarizes them according to the individual approaches. Different processors should choose the appropriate protection approaches due to the usage, surroundings, and potential possibilities.

1.       Can you elaborate the different function of figure 2 tables? How do they perform on their own end?

 

2.       In terms of the figure 4, what is the block underneath the decoder? Is it a mux? And what’s the purpose for “Subordinate” block?

Author Response

Thank you very much for your feedback and for your effort and time spent reviewing our paper.

1 - We have simplified the Figure 2. The purpose of bit-interleaving/scrambling is to prevent the upset of multiple bits by a single particle hit. The figure shows that the bits of the same code word are not physically adjacent.

2 - Yes, that it is a multiplexor. We have redesigned the Figures and better described individual modules. The subordinates are modules that receive requests from the manager and provide responses.

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

The quality of the paper has been improved. The authors' responses are also convincing. So, to this reviewer, the paper can be accepted.

Reviewer 3 Report

Comments and Suggestions for Authors

The authors have addressed all my comments. So, it can be published in the form.