A Survey of Ultra-Low-Power Amplifiers for Internet of Things Nodes

Abstract

This paper investigates CMOS operational transconductance amplifier (OTA) design methodologies suitable for Internet of Things nodes. The use of MOS transistors in the subthreshold of the body terminal for signal input or bias, as well as newer inverter- and digital-based techniques, is considered. Solutions from the authors’ work are utilized as main case examples. State-of-the-art ultra-low-power OTAs are then thoroughly compared using a data-driven approach. According to the findings, digital- and inverter-based solutions have the lowest area occupation and superior small-signal performance but are inherently susceptible to process, supply, and temperature (PVT) variations. The only “analog” approach suitable for a sub-0.6 V supply is body driving in conjunction with subthreshold bias. It offers competitive large-signal performance and, more importantly, is less sensitive to PVT variations at the expense of silicon area.

1. Introduction

The Internet of Things (IoT) has wide-ranging potential applications with expected significant impacts across various industries, including agriculture, healthcare, automotive, and industrial manufacturing. A conservative projection estimates that the number of interconnected IoT devices will reach approximately 29 billion by 2030 from 9.7 billion in 2020, indicating a substantial growth in the use of this technology in the coming years [1].

Among the most important characteristics of IoT nodes are computing, wireless communication, and sensor capabilities [2]. Indeed, IoT node implementation requires circuits that connect the digital processing domain with physical signals received from the analog world via sensors such as temperature, CO₂, light, humidity, displacement, pressure, and acceleration. As a result, analog interfaces are critical elements in the IoT paradigm [3] because IoT nodes are commonly wireless and energy-autonomous and hence have a very limited power budget that often relies on small primary batteries or area-constrained energy harvesters, with the optional support of secondary batteries. As a result, there is an urgent need to heavily reduce the power consumption of digital cores and analog frontends, and, for this purpose, efficient IoT nodes must exploit ultra-low-voltage design techniques with an operating voltage of 1 V or less. Furthermore, the utilization of sub-100 nm CMOS technologies is required to improve the power-delay product of digital circuits, which constitute the bulk of an IoT device [2]. However, the scaling of CMOS technology, the low supply voltage available, and the limited allowed power consumption lead to deleterious effects in the analog domain, such as a drop in output resistance, dynamic range, and signal-to-noise ratio. Consequently, designing the analog front end becomes a challenging task that can seriously impact the overall IoT node performance [4].

In this framework, the operational transconductance amplifier (OTA) is one of the fundamental building blocks of the analog front end. Various design techniques are today available to enable efficient OTA performance at low power, including weak inversion (or subthreshold) operation [5,6,7,8,9,10,11], bulk-driving (or body-driving) [12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30], body-biasing [31,32,33], inverter-based [34,35,36,37,38,39,40,41,42,43], and fully digital approaches [44,45,46,47,48,49,50,51]. Floating-gate and quasi-floating-gate techniques can also be mentioned [52,53]. However, the latter ones employ custom transistors that are not included in commercial design kits. In addition, the temperature dependence of the pseudo-resistor adopted (not adequately modeled in CAD tools) limits the use of this approach. Furthermore, a relevant limitation is leakage currents, which can make this technique unfeasible in sub-100 nm CMOS processes. As a result, we will not investigate floating-gate and quasi-floating-gate transistor solutions by limiting our analysis to techniques appropriate for conventional CMOS technologies and acceptable by the industry standards.

The aim of this paper is hence to review the main design techniques suitable for ultra-low-power, ultra-low-voltage OTAs, highlighting their advantages and trade-offs. In this field, the authors have decades of expertise and have devised several solutions, some of which will be discussed in the next sections and will be chosen as design examples. A data-driven analysis of the state of the art is also performed to offer the designer some guidance for selecting the best OTA solution based on the specified design parameters and system needs.

The paper is organized as follows. Section 2, Section 3, Section 4, Section 5 and Section 6 provide a succinct examination of the working principles of the CMOS subthreshold, body-driving, body-biasing, inverter-based, and digital techniques, as well as selected example designs. Section 7 compares the key solutions acquired from the state of the art and that exploit the preceding methodologies. A quantitative, data-driven comparison is performed by considering the primary performance parameters and evaluating specific figures of merit often used in the literature. Section 8 summarizes the authors’ conclusions.

2. Subthreshold Approach

Operating transistors in the weak inversion (or subthreshold, SUB) region has been the primary technique for low-voltage and low-power analog design in MOS technology since the 1970s [5].

It is worth noting that in the subthreshold, the saturation condition is reached when $V_{DS}\cong 4V_T$, where V_T is the thermal voltage. In this region, an exponential behavior between the drain current and the gate-source voltage is found. The second column of

Table 1. Small-signal parameters of an N-channel MOS transistor (saturation region).

	Subthreshold		Above Threshold Bulk-Driven
$g_m=\frac{\partial I_D}{\partial V_{GS}}$	$\frac{I_D}{n{V}_T}$	(1a)	$\sqrt{\frac{2KW{I}_D}{L}}$	(1b)
$g_{mb}=\frac{\partial I_D}{\partial V_{BS}}$	${\lambda }_B{g}_m$	(2a)	$\frac{C_{BC}}{C_{GC}}{g}_m$	(2b)
$g_{ds}=\frac{\partial I_D}{\partial V_{DS}}$	$\lambda I_D$	(3a)	$\lambda I_D$	(3b)
$f_T$	$\frac{g_m}{2\pi \left(C_{GS}+C_{GD}+C_{GB}\right)}$	(4a)	$\frac{g_{mb}}{2\pi \left(C_{SB}+C_{DB}+C_{b-sub}\right)}$	(4b)

g_m: gate-source transconductance, g_mb: body-source transconductance, g_ds: drain-source conductance, f_T: transition frequency, I_D: drain current; W: transistor channel width, L: transistor channel length, V_T: thermal voltage, n: subthreshold slope, μ_n: electron mobility, C_OX specific gate capacitance, K = μ_nC_OX: transconductance factor, λ_B: body effect coefficient, λ: channel-length modulation coefficient, C_GS: gate-to-source capacitance; C_GD: gate-to-drain capacitance; C_GB: gate-to-bulk capacitance; C_SB: source-to-bulk capacitance; C_DB: drain-to-bulk capacitance; C_B-sub: bulk-to-substrate capacitance, C_BC: bulk-to-channel capacitance; C_GC: gate-to-channel capacitance.

shows the small-signal parameters of a gate-driven n-MOS transistor operating in the subthreshold region and in saturation. A bipolar-like behavior is apparent from the linear dependence of the transconductance g_m on the drain current I_D (1a). Subthreshold devices also show the highest transconductance efficiency (g_m/I_D) [4], while the intrinsic voltage gain, A_v, = g_m/g_ds, is equal to the reciprocal of nλV_T (which is strictly related to the channel length), resulting in a minimization of distortion [6].

The main drawback of the approach is a larger drain current error between two otherwise ideally matched transistors, which, in the implementation of an OTA, tends to increase the offset and noise and to reduce the common-mode rejection ratio, CMRR.

Overcoming this issue may result in a complex design [54]. Moreover, since subthreshold operation implies very low standby currents, the reduced transconductance leads to limited bandwidth (4a), which is only partially compensated by the lower MOS parasitic capacitances provided by the scaled technologies. However, this is not a main issue because most of the sensor node applications, such as monitoring pressure, temperature, humidity, acceleration, or bio-signals, usually involve frequencies around the kilohertz [3]. For these reasons, the subthreshold region is popular in the implementation of analog building blocks, including OTAs supplied from 1 V under very limited current budgets [7,8,9,10,11,15].

As an example, a solution operating at 1 V and proposed in [11] is shown in Figure 1. The OTA clearly illustrates that conventional circuit configurations are employed. In this case, we have a folded-cascode differential stage M₁–M₈, followed by a common-source stage M₉–M₁₀, and as a final non-inverting stage, a common-source M₁₁ transistor with a current mirror-load M₁₂–M₁₃. The subthreshold biasing point of the transistors here is the key aspect, and, in addition, the use of three gain stages is to compensate for the diminished intrinsic stage gain. Nested Miller frequency compensation capacitors C₁ and C₂ provide closed-loop stability.

The DC gain and the gain–bandwidth product (GBW) are

$$A=g_{m1,2}{g}_{m9}{g}_{m11}{r}_{o1}{r}_{o2}{r}_{o3}$$

(5)

$$GBW=\frac{g_{m1,2}}{C_1}$$

(6)

where r_oi is the equivalent small-signal resistance at the output of the i-th stage (r_o1 ≈ r_d8, r_o2 = r_d9//r_d10, and r_o3 = r_d13//r_d14). The DC gain is found to be greater than 120 dB, and the GBW is 20 kHz. The solution allows the driving of high capacitive loads up to 200 pF, with only 170 nA of standby current.

3. Body-Driven Approach

Traditional gate-driven approaches, either above or below the threshold, control the conductivity of the channel and, consequently, the drain current, I_D, via the gate-source voltage. In contrast, in the bulk- or body-driven (BD) approach, I_D is controlled by the bulk-source voltage, V_BS. Figure 2a,b shows two different ways to implement a p-channel differential pair, one through the usual gate-driven approach and the other through the alternative bulk-driven approach. In the latter case, the differential input signal is applied to the bulk terminals of the transistors couple M_2B–M_3B, while the gate terminals are kept to a reference voltage (V_SS in this case) [17].

Removing the limitation given by the threshold voltage associated with the gate terminal, the input common-mode range of the BD pair is maximized, since the input voltages can span from V_SS to V_DD. The main advantage of this approach is, indeed, the ability to achieve rail-to-rail input operation under supply voltages comparable to or even less than the threshold voltage. It is, of course, mandatory that the bulk-source junction is not turned on. Otherwise, the bulk source junction starts to draw a non-negligible current. For rail-to-rail operation, the approach is hence particularly profitable for supplies (V_DD–V_SS) below 0.5 V, just below the junction threshold.

Returning to Figure 2b, we observe that the gates of M_2B–M_3B, connected to V_SS, can be instead used to set the standby current of M_2B–M_3B through a conventional current mirror and by eliminating the tail current generator M_1B. In this manner supply demand is further reduced at the cost of a lower power supply rejection ratio, PSRR [55]. It is also noteworthy that the BD approach requires the use of a triple-well technology if the body terminal of both p- and n-channel MOS devices must be exploited. As a drawback, this results in greater area occupation.

The third column of Table 1 shows the small-signal parameters of a body-driven transistor operating in saturation above the threshold region. Since the bulk transconductance g_mb is only about 10% to 20% of g_m, as highlighted by (2b), bulk-driven configurations are characterized by reduced values of the intrinsic gain A_v and transition frequency f_T.

Several bulk-driven OTAs have been proposed in literature [12,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30]. Most of these solutions also operate transistors in the subthreshold to minimize the supply voltage requirements. Moreover, multistage architectures are often utilized to overcome the lower value of the DC gain. Positive feedback is also exploited to increase both the input transconductance and the gain–bandwidth product. To give an example, the schematic of the OTA proposed in [29] is shown in Figure 3. The resulting differential gain and gain–bandwidth product can be expressed as follows:

$$A=\frac{\beta }{1-\alpha }{g}_{mb1,2}{r}_o$$

(7)

$$GBW=\frac{\beta }{1-\alpha }\frac{g_{mb1,2}}{C_L}$$

(8)

where the effect of the positive feedback is displayed by factor (1 − a) at the denominator. Of course, parameter a must be close but lower than 1 to preserve stability. With a = 0.83, and b= 15, we obtain a DC gain slightly lower than 40 dB and a GBW equal to 5 kHz, with a power consumption of around 32 nW. It is noteworthy that because of the absence of the tail current generator, M1–M2 is a pseudo-differential pair, but thanks to the action of M7 and M8, the whole OTA provides a quasi-differential behavior, as shown in [29].

For the same purpose of increasing input transconductance, the combination of the body-driven and AC-coupled gate-driven approaches has also been proposed in [56]. As it was already stated, this solution is not considered in this discussion due to the QFG technique limitation in the CMOS process.

4. Body-Biased Approach

The body-biased (BB) approach is aimed at overcoming the limitations of the CMOS technology and/or of the conventional OTA topologies through threshold lowering [8,14], level shifting [16], body-driven gain boosting [19], and non-tailed differential pairs [33,55]. These techniques can also be combined together.

The body-biased approach followed in [31] exploits a gate-driven differential pair, thus providing a high gate transconductance, but (1) the tail current source is eliminated, leaving extra room for the input swing; additionally, (2) the body terminals of the pair are used both to control the common-mode (and hence also the DC) current and to reduce the threshold voltage through the body effect. Figure 4a,b, shows, respectively, the minimum-supply gate-driven differential pair and the simplified schematic of the common-mode control circuit. The common-mode control voltage V_b is generated in the circuit of Figure 4b, forcing I_B/2 to flow in M_1R (M_2R) when V_in+ = V_in− = V_icm. Then, V_b is applied to the main circuit of Figure 4a. It is apparent that the quiescent (and common-mode) current in M₁–M₂ is mirrored from that of M_1R–M_2R, and hence, M₁–M₂ acts as a differential pair but without the tail current source. Moreover, under suitable values of W/L)_1R–_2R and I_B, the voltage V_b is less than V_DD, and the threshold voltage of M_1R–M_2R is diminished.

The gain of the circuit in Figure 4a can be expressed as

$$A\approx \frac{g_{m1,2}}{2}{R}_{1,2}$$

(9)

where the output resistance of transistors is neglected.

Based on this approach, an optimized solution that provides relatively low noise around 65 nV/$\sqrt{H_z}$ and a total current consumption of 27 µA with a good trade-off between DC gain (65 dB) and gain–bandwidth product (1 MHz) has been experimentally validated in [33].

5. Inverter-Based Approach

All the previous OTAs require manual design flow from the schematic level to the layout and routing. Moreover, the BD and BB approaches especially result in considerable area occupation because separate wells must be used. In other words, unlike digital designs, the previous OTAs do not take advantage of design automation and technology scaling.

The inverter-based (INV) approach exploits CMOS inverters as transconductance stage elements, as said, in an attempt to extend the digital design flow to the analog domain, keep low the design effort, and provide portability across technologies. An early implementation of this approach is the so-called Nauta transconductor and further derivations [34,35,36,37,38,39,40,41,42].

As an introduction, consider the inverter M1–M2 in Figure 5 and neglect, for the moment, resistor RF. It can be seen that the inverter works as an amplifier, provided that it is biased in its switching threshold so that both transistors are in saturation. Under this biasing condition, the small-signal transconductance of the inverter is equal to the sum of the transconductances of both the nMOS and pMOS transistors, i.e., g_m = g_m1 + g_m2.

The bias point can be obtained through self-biasing using the resistive feedback provided by R_F, as shown in Figure 5, or with more complex, higher-efficiency topologies [40], even exploiting the body terminal [37]. In conclusion, the circuit in Figure 5 can be used as a transimpedance amplifier because it has a relatively low input resistance.

To obtain a transconductance amplifier, we can return to a conventional single-stage OTA, as exemplified in Figure 6a. The key concept here is to replace each transistor in the signal path (M₁–M₄) with an inverter. The gate and the drain of the original transistors correspond to the input and output of the associated inverter, respectively. The source terminal is not important, as it is kept at a fixed potential. This is true for active load transistors M₃ and M₄ but also for the pair M₁ and M₂, since, as is well known, the common source is at the virtual ground, provided that the input signal is purely differential. As a result, the circuit in Figure 6b is derived, which represents the basic inverter-based single-stage OTA. Indicating with G_mi and R_oi the transconductance and output resistance of the i-th inverter, the output voltage is given by V_out = (G_m1G_m4/G_m3 V_in+ − G_m2 V_in−)R_o4. If G_m1 = G_m2 = G_m1,2, and G_m3 = G_m4, then the gain can be expressed as

$$A=G_{m1,2}{R}_{o4}$$

(10)

The expression of GBW is as in (6) by replacing g_m1,2 with G_m1,2 and C₁ with C_L. (In this case, dominant pole compensation is adopted.)

While this circuit can be designed using standard cells and automated place and route, it has several drawbacks, such as low DC gain and CMRR (due to the unavoidable mismatches between G_m1 and G_m2 and between G_m3 and G_m4), it implements only a pseudo-differential OTA, and it does not offer DC current control [42]. The latter limitation is fundamental for applications with a limited power budget. Moreover, it makes the solution very sensitive to process, supply, and temperature (PVT) variations.

A four-stage inverter-based OTA that uses the bulk terminals of both the p-channel and n-channel MOS transistors of the standard-cell inverter as current and voltage control inputs was proposed in [43]. The body-control approach is similar to that used in digital applications to handle process variations. All the standard-cell inverters used for analog functions are connected to an analog building block generator, which provides the bulk voltages and which, in turn, enables each cell’s static output voltage to be adjusted to half the supply voltage and the quiescent current to be set to a multiple of a reference current. The simplified schematic of the OTA proposed in [43] is shown in Figure 7, where inverters 1–5 are simple inverters (×1), inverter 6 is made up of two parallel inverters (×2), and inverter 7 is made up of four parallel inverters (×4). The body-control section is not shown for simplicity, but the interested reader can refer to [43] for further details.

In summary, this solution operates at a 0.5 V supply and provides a DC gain of around 70 dB, a gain–bandwidth product around of 7 MHz, and a slew rate of 1.51 V/µs, with a power consumption of only 0.88 µW.

6. Digital Approach

Analog processing requires a well-defined biasing point for the active devices, which, in turn, require a well-defined quiescent current, setting the lower limit for the DC power consumption. With the digital-based approach, it is possible to eliminate any quiescent bias current and to ensure low power consumption, low area occupation, and low complexity at the cost of weak control over current consumption and hence performance across PVT variations.

Several fully digital OTAs (DIGOTA) with a sub-1 V supply and nanowatt power consumption have been presented in literature [43,44,45,46,47,48,49,50,51]. These solutions do not require a DC current, as they are essentially digital standard cell-based OTAs and share with the inverter-based approach the advantages of both simple design and portability over technologies.

In this context, a passive-less fully-digital operational transconductance amplifier (DIGOTA) that employs time-domain processing, zero bias current, and passive-less self-oscillation common-mode compensation was proposed in [45,46] and finally improved in [51].

The principle of operation of the DIGOTA is the same as the NOT approach and relies on the observation that a simple pair of digital inverters, as shown in Figure 8a, under an input differential signal (V_IN+ − V_IN−) > 0 ((V_IN+ − V_IN−) < 0) generates a high (low) output differential voltage, provided that the input common-mode voltage, V_CM, is close to the inverter trip point, V_trip. If V_CM is away from V_trip, the digital outputs of the inverters are equal and cannot discriminate whether (V_IN+ − V_IN−) > 0, or (V_IN+ − V_IN−) < 0. However, the information related to the signal V_CM < V_trip or V_CM > V_trip still provides useful information that can be exploited to correct the common-mode input signal and enforce the desired condition, V_CM = V_trip, through a negative feedback loop.

The schematic of the DIGOTA recently introduced in [51] is shown in Figure 8b. The compensation of the common-mode voltage is implemented by adopting an input stage based on the Muller C-element driven by the two input voltages, V_IN+ and V_IN−, and by the signal V_PD. The differential-to-single-ended (D2S) output stage is implemented in this work by inverters 1B and 2B (constituting an inverting voltage buffer), with inverters 1A and 3B acting as transconductance amplifiers. As a result, the DIGOTA is made up of three gain stages, namely the Muller C-element, the inverter, and the output stage. Remarkably, it has been demonstrated in [51] that the equivalent small-signal model can be reduced to that of a conventional three-stage OTA, as shown in Figure 8c. Assuming that V_PD is almost constant, the small-signal parameters in Figure 8c can be expressed as (Note that a more accurate evaluation of g_m,N1 and g_m,P1 includes the body transconductance of the transistors M_N2 and M_P2, as detailed in [51]):

$$G_{m1}=g_{m,N1}+g_{m,P1}$$

(11)

$$G_{m2}=g_{m,N3}+g_{m,P3}$$

(12)

$$G_{m3}=2\left(g_{mN,1A}+g_{mP,3B}\right)$$

(13)

$$C_{O1}=C_{par1}+C_M$$

(14)

$$C_{O2}=C_{par2}+C_{MUL}$$

(15)

$$C_{O3}=C_{par3}+C_L$$

(16)

$$R_{O1}=R_{O1,N}‖R_{O1,P}$$

(17)

$$R_{O2}=r_{d,N3}‖r_{d,P3}$$

(18)

$$R_{O3}=r_{d,N3}‖r_{d,P3}$$

(19)

with C_pari being the parasitic capacitance at the output of the i-th stage. R_O1,N and R_O1,P are the resistances of the cascode gain stage. The voltage gain and the GBW are, therefore, equal to

$$A=G_{m1}{G}_{m2}{G}_{m3}{R}_{O1}{R}_{O2}{R}_{O3}$$

(20)

$$GBW=\frac{G_{m1}{G}_{m2}{G}_{m3}{R}_{O1}{R}_{O2}}{C_L}$$

(21)

Under a 0.3 V supply and a load of 250 pF (and at 27 °C), the power consumption of the OTA is 44.2 nW, while the occupied area is 625 μm². DC gain is 66 dB, and GBW is 12.3 kHz. Power dissipation ad GBW increases to 198.6nW and 59 kHz at 70 °C, just to give and idea of the sensitivity of temperature.

7. Comparison and Discussion

With a view of making a more detailed comparison among the examined approaches, we will consider only the ultra-low power OTAs with a supply equal to or less than 0.7 V, which are summarized in

Table 2. Comparison of ultra-low-power OTAs (* simulated).

	[8]	[9]	[10]	[18]	[22]	[23]	[24]	[26]	[28]	[27]	[29]	[30]	[33]	[25] *	[41] *	[39] *	[43]	[42] *	[45]	[47]	[46]	[49]
Year	2005	2014	2016	2007	2014	2015	2016	2018	2020	2020	2022	2023	2017	2017	2020	2020	2022	2022	2020	2021	2021	2021
Tech. [μm]	0.18	0.18	0.18	0.35	0.13	0.065	0.18	0.18	0.18	0.065	0.18	0.065	0.35	0.18	0.18	0.18	0.065	0.13	0.18	0.18	0.18	0.13
Op. modeb	SUB	SUB	SUB	SUB, BD	SUB, BD	SUB, BD	BD	SUB, BD	SUB, BD	SUB, BD	SUB, BD	BD	BB	INV	INV	INV	INV	INV	DIG	DIG	DIG	DIG
Area [mm2] × 10−2	1.7	5.7	3.6	6	8.3	0.5	2	0.8	1	0.2	0.9	0.11	1.4	-	0.08	0.07	0.02	0.02	0.1	0.1	0.1	0.01
Supply [V]	0.5	0.5	0.5	0.6	0.25	0.5	0.7	0.3	0.3	0.25	0.4	0.3	0.7	0.5	0.5	0.3	0.5	0.3	0.3	0.3	0.5	0.55
CL [pF]	20	30	40	15	15	3	20	20	30	15	150	50	10	20	10	10	0.5	2	150	80	150	250
DC gain [dB]	62	70	77	69	60	46	57	63	98.1	70	37	38	65	91	25.2	51	64	34.97	30	30	73	87
IT [μA]	150	0.15	0.14	0.9	0.072	366	36	0.056	0.043	0.104	0.081	8.5	27	26	0.558	0.002	1.75	20.3	0.008	0.002	0.215	14.9
Power [μW]	75	0.075	0.07	0.54	0.018	183	25.2	0.017	0.013	0.026	0.033	2.55	18.9	13	0.279	0.001	0.875	6.1	0.002	0.001	0.108	8.2
GBW [kHz]	0.01	18	4	11	2	38,000	3000	3	3	10	6	1650	1000	394	132	0.74	6850	12,700	0.2	4	60	3150
PM [°]	60	55	56	65	53	57	60	61	54	88	79	70.3	60	59	87	90	62	62	-	54	-	65
SR [V/ms)	2000	3	2	15	0.7	43,000	2800	7	9	2	7.9	180	250	-	-	-	1510	5680	0.1	0.2	19	2.7
Noise [nV/sqrt(Hz)]	280	310	-	290	3300	926	100	1850 *	1800 *	-	-	250	65	31.8	-	809	-	-	21,000	-	-	175
CMRR (dB)	65	-	55	74.5	-	35	19	72	60	62.5	36	39.8	45	-	-	37	-	27	41	-	65	46
PSRR [dB]	43	-	52	-	-	37	52	62	61	38	30	44.7	50	122.3	76.8	41	-	-	30	-	50	39
# stages	2	2	2	2	2	3	3	2	3	3	1	3	2	-	-	-	4	-	-	-	-	-
FOMS [MHz·pF/μW]	2.67	7.20	2.29	0.31	1.67	0.62	2.38	3.33	7.15	5.48	25.6	32.35	0.53	0.61	4.73	14.8	3.91	4.16	15.6	598	80.2	96.0
FOML [(V/μs)·pF/μW]	0.53	1.20	1.14	0.42	0.58	0.7	2.22	8.45	21	1.15	34.1	3.53	0.13	-	-	-	0.86	1.86	5.31	28.96	26.5	0.08
IFOMS [MHz·pF/μA]	1.33	3.60	1.14	0.18	0.42	0.31	1.67	1	2.15	1.37	10.3	9.71	0.37	0.30	2.37	4.44	1.96	1.25	4.69	179	40.1	52.8
IFOML [(V/μs)·pF/μA]	0.27	0.60	0.57	0.25	0.15	0.35	1.56	2.54	6.3	0.29	13.64	1.06	0.09	-	-	-	0.43	0.56	1.59	8.69	13.3	0.05
IFOMAS [MHz·pF/μA·mm2]	78.43	63.16	31.75	3	5	63	84	122	219	685	11,838	9156	26.5	-	2957	6107	9786	5730	4773	122,627	40,852	598,189
IFOMAL [[(V/μs)·pF/μA·mm2]	15.69	10.53	15.87	4.2	1.8	71.2	78.6	309.2	642.9	144.2	15,745	999	6.6	-	-	-	2150	2565	1623	5943	13,499	513

. Note that simulated INV solutions have also been considered, due to the lack of fabricated examples. The main OTA parameters such as DC gain, gain–bandwidth product (GBW), phase margin (PM), slew rate (SR), noise, common-mode rejection ratio (CMRR), and power supply rejection ratio (PSRR), together with the well-known figures of merit, FOM_S, FOM_L, IFOM_S, and IFOM_L [10,11,21,22,23,26,27,51], defined in (18) and (19), are evaluated.

$$FO{M}_S=\frac{GBW}{Power}{C}_L$$

(22)

$$FO{M}_L=\frac{SR}{Power}{C}_L$$

(23)

$$IFO{M}_S=\frac{GBW}{I_T}{C}_L$$

(24)

$$IFO{M}_L=\frac{SR}{I_T}{C}_L$$

(25)

where I_T is the total bias current.

For a specified capacitance load, (22)–(25) show a trade-off between small-signal and large-signal parameters and total power/bias current consumption.

If we also consider the area occupation, we can define the following two additional figures of merit (IFOM_AS and IFOM_AL) in (24) and (25) [30,46,51]

$$IFO{M}_{AS}=\frac{GBW}{Area·I_T}{C}_L$$

(26)

$$IFO{M}_{AL}=\frac{SR}{Area·I_T}{C}_L$$

(27)

From the inspection of Table 2, the lowest value of power consumption, which was around 1 nW, was achieved by [39,47], which used a DIG and an INV approach, respectively. The highest value of the DC gain was 98 dB and was achieved by [28], which combined the BD and the SUB approach, while the highest GBW was achieved by [23] (with minimum C_L of 3pF), which exploited an INV approach.

The highest IFOM_S was achieved by the INV OTA proposed in [47], while the highest IFOM_L was achieved by the BD + SUB OTA proposed in [29]. It is also apparent that the DIG and INV approach resulted in the lowest area occupation.

Figure 9 and Figure 10 show the plots of IFOM_S and IFOM_L (on a semilogarithmic scale) for the different OTAs as functions of the technology node. Additionally, IFOM_S and IFOM_L reached the maximum in the 0.18 mm technology node, and the best small-signal performance was achieved by the DIG approach, whereas DIG and SUB + BD shared the best large-signal performance. Interestingly, SUB + BD was still the best in the minimum technology node implementations (i.e., 65-nm), though no DIG implementations here are available for comparison.

Figure 11 and Figure 12 also show IFOM_AS and IFOM_AL as functions of the technology node. In general, the highest values of IFOM_AS were achieved by the DIG and INV approaches, thanks to their inherent reduced area occupation. SUB + BD was competitive for the large-signal performance.

Another comparison was carried out considering the effect of the supply voltage reduction, as illustrated in Figure 13 and Figure 14, showing the IFOM_S and IFOM_L as functions of V_DD, respectively. Below 0.6 V, DIG approaches provided the best IFOM_S, which were greater up to one order of magnitude with respect to INV and SUB-BD counterparts. IFOM_L were dominated by SUB-BD and DIG approaches, which provided similar values.

Considering also the area occupation, Figure 15 and Figure 16 show the IFOM_AS and IFOM_AL achieved by the OTAs as functions of the supply voltage. Similar considerations for Figure 13 and Figure 14 can be derived.

8. Conclusions

This paper describes OTA solutions amenable for IoT applications that require low-voltage and low-current capabilities together with reduced area occupation. After providing a succinct examination of the working principles of the CMOS subthreshold, body-driving, body-biasing, inverter-based, and digital techniques by the utilization of exemplifying solutions proposed by the authors, a comparison of cutting-edge CMOS OTA designs suitable for IoT applications was performed. The comparison was carried out by taking into account small-signal and large-signal performances, as well as area occupation and robustness against PVT variations. According to the findings, only the SUB + BD, DIG, and INV approaches are suitable for supply voltages less than 0.6 V. Furthermore, DIG and INV require the least amount of silicon area, provide design portability across multiple technologies, and support automated design. SUB + BD, on the other hand, which is an ‘analog’ approach, necessitates a custom design and a larger area but maintains performance across technology scaling, providing competitive large-signal performance. It was noted that the SUB + BD approach continues to provide the best results in the smallest technology node implementations available, namely 65 nm (although this may be due to a lack of DIG implementations in this technology). More importantly, with a well-defined bias point, it allows for better control over power dissipation (and thus small- and large-signal performances) in the face of PVT variations.

In summary, applications requiring reliable current control must prefer SUB + BD or at the very least, INV, with current control solutions if silicon area is a major concern. DIG solutions, while promising, will require further study and development.