Design-Aware Parasitic-Aware Simulation Based Automation and Optimization of Highly Linear RF CMOS Power Amplifiers

Abstract

In this paper, a parasitic-design-aware simulation-based design tool is proposed for highly linear RF power amplifiers. The main aim of the proposed tool is to speed up the design process of RF power amplifiers. In addition, it provides accurate final designs taking into consideration the effect of parasitic components of both active and passive devices. The proposed tool relies on the knowledge of designing highly linear RF power amplifiers. Both the optimization steps and design methodology are presented in this paper. The proposed tool is verified by designing a highly linear RF power amplifier at three different frequencies (7 GHz, 10 GHz, and 13 GHz) using 65 nm technology node. The results show that an OP1 dB higher than 18 dBm, gain/S21 higher than 7 dB, and OIP3 higher than 24 dBm at 6 dB back-off power can be obtained.

1. Introduction

Today, for any wireless transceiver, the RF power amplifier (PA) is considered one of the important building blocks. This is because RF power amplifiers determine the maximum transmitted power. Designing CMOS RF power amplifiers is challenging due to several factors: First, the different performance specifications of a power amplifier, such as Gain, output 1 dB compression point (OP1 dB), efficiency, and output linearity are dependable on each other. Second, those performance specifications are limited by the existing layout parasitic components of both active and passive devices. Finally, it takes several, time consuming design iterations to account for the electromagnetic interaction between the various passive components within the design [1,2,3,4,5,6,7,8].

Design automation could help to reduce this design time and to reach an optimum design that meets the design targets [9,10]. However, the aforementioned challenges present a limitation even if design automation is used. Design automation approaches that overcome these challenges (trade-offs, effect of parasitic components, and electromagnetic interactions), while reducing time consuming electromagnetic (EM) simulations and layout parasitic extraction, are required.

The design automation of RF circuits, applied for the optimization of a low noise amplifier (LNA), was introduced in [11] where a Pareto-optimal front (POF) of EM-simulated inductors was obtained prior to the optimization. This approach is an offline design methodology where the inductor pareto-optimal fronts are independent of the circuit. Another design automation approach, used for the optimization of a folded cascode operational transconductance amplifier (OTA), was presented in [12], where a simulation-based circuit sizing tool with a template-based layout generation tool were shown. The simulated-annealing-based optimization of a class C CMOS RF power amplifier (operating at a frequency of 900 MHz) was introduced in [13]. The effect of the inductors was taken in consideration by introducing a compact model including some of the parasitic components of the inductor. However, simulated-annealing optimization has slow convergence rates. A simulation-based optimization of RF amplifiers (operating at frequencies less than 10 GHz) was presented in [14], where an online inductor surrogate model was built using machine learning techniques. The main challenge of this approach was that the quality of the surrogate model is not always good, and it depends on the available training data. Evolutionary algorithms were used in the optimization of an LNA in [15], but no inductance modelling was included. Metaheuristics were used in the optimization of an LC voltage-controlled oscillator (VCO) and a CMOS current feedback operational amplifier (operating at a frequency of 1.5–2.5 GHz), using 2п inductance modelling [16]. Evolutionary algorithms were also used in the optimization of an operational amplifier (OPAMP) and an LNA, where the inductance modelling was carried out using linear behavior into performance models [17]. Evolutionary algorithms and simulated-annealing were used in the optimization of single ended LNA and CMOS differential cross coupled oscillator operating at 2.4 GHz frequency [18].

In this paper, a simulation based, design-aware, parasitic-aware optimization tool is introduced for the design of highly linear RF CMOS power amplifiers. The introduced tool overcomes the previously mentioned design challenges by integrating the design experience within the optimization loop to speed up the design process. This design experience has to be programmed once and can be used later for all other designs at different frequencies and using different technology nodes. In addition, parasitic components are estimated such that the outcome of the design tool is close to the final design. The proposed design-aware tool does not require the design space exploration and/or the lengthy global optimization algorithms that were presented in the previous publications [11,14,15,16,17,18]. The tool uses BFGS optimization algorithm, implemented within the virtuoso environment [19], as the core optimizer, and Spectre RF [20] as the simulation engine. The paper is organized as follows: An overview of the proposed design tool and an illustration of the PA architecture adopted in the tool are introduced in Section 2. Section 3 discusses the parasitic modelling approach adapted within the tool. In Section 4, the details of the design-aware optimization and the design flow are explained where the knowledge of the designer is integrated within the tool. Test cases and the results of the optimization are shown in Section 5. A discussion is found in Section 6. Finally, the paper is concluded in Section 7.

2. The Proposed Design Tool for RF Power Amplifiers

The core of the introduced design tool is made up of four main parts; the web interface, the CAD RF circuit simulator, the Parasitic Model Generator, and the Optimizer. Figure 1 shows a simplified diagram of the core of the introduced design tool. The user enters the required performance specifications of the RF power amplifier to the web interface. The web interface is developed using PHP, HTML, CSS, and Java scripting. The communication between the web interface and the RF circuit simulator (cadence-virtuoso) is established through shell scripting and ocean scripting. The CAD RF Circuit Simulator (cadence-virtuoso) is updated by the required performance specifications from the web interface. Then, it invokes the cadence built-in optimizer, which updates the netlist of the adopted highly linear RF power amplifier schematic. Multi-objective optimization is carried out by the hybridization of design-aware optimization flow and the BFGS optimization algorithm [21,22], which is employed in cadence built-in optimizer. The BFGS algorithm is used for finding the best values of the design parameters that can meet the required constraints. The parasitic models are priorly constructed within the parasitic model generator and their values are updated by the optimizer. The new values are included in the updated netlist. The optimization process continues till reaching the best achieved design point. The resulting design parameters are then returned to the user along with the achieved performance. The highly linear PA architecture, adopted as an application for the proposed tool, is explained below.

The Adopted Highly Linear PA Architecture

Figure 2a shows the highly linear power efficient RF CMOS power amplifier architecture adopted by the introduced tool. The architecture is based on achieving high linearity by using parallel cascoded configuration (PCC) topology introduced in [23]. Figure 2b shows the PCC amplifier topology that improves the linearity of RF power amplifiers through transconductance linearization. The topology is made up of two parallel-connected cascode branches. The common source (CS) amplifier, used in the main branch, is biased to operate as a class-AB power amplifier carrying most of the consumed current. while the auxiliary amplifier is biased to operate as a class B amplifier. Transconductance linearization is achieved by choosing the biasing voltages and sizes of the main and auxiliary common source amplifiers such that the non-linearities of both branches are partially cancelled out when added together. If the biasing and sizing of both branches are chosen such that the nth-order transconductances of the main and auxiliary amplifiers, G_{n_main} and G_{n_auxiliary}, have almost similar magnitudes and 180 degrees phase shift, their summation at the output node results in their partial cancellation.

Based on (1), (2), and (3), the partial cancellation of transconductance non-linearities results in the cancellation of third-order and fifth-order intermodulation distortion (IMD3 and IMD5) as well as the cancellation of third order harmonic distortion (HD3) [23].

$${\mathrm{i}}_{\mathrm{DS}\_3}=\frac{3}{4} {\mathrm{A}}^3 ({\mathrm{G}}_{3\_\mathrm{main}}+{\mathrm{G}}_{3\_\mathrm{auxiliary}})+\frac{25}{8} {\mathrm{A}}^5 ({\mathrm{G}}_{5\_\mathrm{main}}+{\mathrm{G}}_{5\_\mathrm{auxiliary}}),$$

(1)

$${\mathrm{i}}_{\mathrm{DS}\_5}=\frac{5}{8} {\mathrm{A}}^5 ({\mathrm{G}}_{5\_\mathrm{main}}+{\mathrm{G}}_{5\_\mathrm{auxiliary}}),$$

(2)

$${\mathrm{i}}_{\mathrm{DS}\_3\mathrm{fo}}=\frac{1}{4} {\mathrm{A}}^3 ({\mathrm{G}}_{3\_\mathrm{main}}+{\mathrm{G}}_{3\_\mathrm{auxiliary}})+\frac{25}{16} {\mathrm{A}}^5 ({\mathrm{G}}_{5\_\mathrm{main}}+{\mathrm{G}}_{5\_\mathrm{auxiliary}}),$$

(3)

where i_{DS_3}, i_{DS_5} and i_{DS_3fo} are the third, fifth-order intermodulation components (IMD3 and IMD5) of drain current, i_DS, and third-order harmonic distortion (HD3), respectively. The cancellation of non-linearities at back-off power results in better linearity and higher efficiency.

As shown in Figure 2a, the main and auxiliary common source devices have separate DC gate biasing. This gives an extra degree of freedom in having different combinations of biasing voltages and sizes of both branches to achieve the required linearization. The input matching network used has a slight modification from the commonly used pi-matching network, where C₃ and C₄ are added to be part of the input matching network to allow both branches to have a single input matching network. The Cascoded configuration is used to overcome breakdown voltage limitations of CMOS devices. The differential configuration reduces the bond-wire effect of source grounding [23] and even-order intermodulation distortion components (e.g., IMD2 and IMD4). Stability is maintained in the circuit by using negative feedback loops made up of series RC networks. These negative feedback loop components are optimized to maintain stability without causing a severe gain decrease. C₇ and C₈ are placed at the gates of the cascode devices of both the main and auxiliary amplifiers and optimized to maintain equal V_DS swings across the common source and the common gate devices of each branch despite any change in input power. The output matching networks are pi-matching networks where a center-tapped inductance is used as shown in Figure 2a.

3. Parasitic Modelling

Including the layout parasitic components in the design process saves a lot of time and effort. It results in accurate designs whose performance specifications are the same before and after post layout simulations.

3.1. Parasitic Modelling for Passive Devices

The inductances and capacitances used in the optimization process are the foundry process design kit (PDK) devices, their corresponding parasitic components are included within the design kit models. The optimization of the physical parameters of passive devices is carried out. The physical parameters of the inductance that are to be optimized are the inner radius and the number of turns, while those of the capacitance are the length and width.

3.2. Parasitic Modelling for Active Devices

The modelling of the parasitic capacitances arising from transistor layout and its interconnects when operating at gigahertz frequencies is carried out and included in the schematic to be taken in consideration during optimization.

Figure 3 shows the parasitic-aware MOSFET model used within the proposed tool. Using S-parameter simulations of the parasitic extracted view of the PDK transistor taking in consideration parasitic components arising from its interconnects, the impedance values seen from its three terminals are plotted with respect to frequency. Thus, the excess capacitances of Cgs, Cgd, and Cds resulting from the layout are estimated. These values are calculated at different values of channel width. Figure 4 shows the excess capacitances of Cgs, Cgd, and Cds versus the width of the transistor. As depicted, as the width of the transistor increases, those capacitances increase linearly. Polynomial expressions of the parasitic capacitances as functions of the number of fingers of the transistor are obtained using least-mean squares curve-fitting method. Equations (4)–(6) show the resulting expressions of the parasitic capacitances after taking the number of multipliers (M) of transistor in consideration.

C_gs (in fF) = (1.1 N + 1.5) ∗ M

(4)

C_gd (in fF) = (1.1 N + 0.4) ∗ M

(5)

C_ds (in fF) = (1.59 N + 1.69) ∗ M

(6)

where N is the number of fingers and M is the number of multipliers of transistors. The finger width is fixed to 2 µm.

4. Design- Aware Optimization and the Proposed Design Flow

4.1. Design Trade-Offs and Sensitivity Analysis

The key component of the proposed design-aware optimization is to combine the knowledge of the designer along with the optimization. For the power amplifier shown in Figure 2a, almost all the design parameters are affecting all the performance specifications. Those specifications include the output 1 dB compression point (OP1 dB), Gain, output third order intercept point (OIP3) at the operating power, power added efficiency (PAE), and input/output matching. The sensitivity of each performance specification to each design parameter (width, biasing, capacitances, and inductances) is different. For the proposed design-aware optimization, those sensitivities are identified and taken in consideration to speed up the design time. Trade-offs are also understood from this sensitivity test.

Below, some examples showing the sensitivity of the performance specifications to the various design parameters are discussed and verified with simulations.

Table 1. Values of all the design parameters in Figure 2a.

Design Parameters		Design Values
Length of all transistors		60 nm
Width of M1 and M3		100 µm
Width of M2 and M4		300 µm
Biasing	Vm (Main)	370 mv
	Va (auxiliary)	370 mv
	Vcas (cascode)	1.55 v
Input Matching Network	Lin	430 pH
	C1	700 fF
	C2	250 fF
	C3, C4	1 pF
Output Matching Network	Cout	400 fF
	Lout	850 pH
	L_CT	1 nH
Feedback Stability Loops	R	2 kΩ
	C	100 fF
Gate Capacitances	C7	365 fF
	C8	365 fF

lists typical values of the design parameters that are used for the sensitivity analysis/simulation. Figure 5a shows the simulation results of the OIP3 versus the output power for different channel widths of the transistors of the main and auxiliary amplifiers. As depicted, the OIP3 depends significantly on the width of the channel of both the main and auxiliary branches. This is because the OIP3 relies on the non-linearities cancellation between these two branches.

It is important to note that the highest OIP3 values are achieved when both sizes are equal to 300 µm, yet the corresponding PAE is the worst as shown in Figure 5b. The best efficiency is achieved when both transistors have sizes equal to 100 µm, while the OIP3 shows a peaking around 10 dBm. The dependency of OP1 dB on the width of the channel is shown in Figure 6, and as expected the larger the width, the higher the achieved OP1 dB. Those simulations indicate that the channel width of both the main and auxiliary branches determine the OIP3, OP1 dB, and efficiency. There is also a tradeoff between those performance parameters (efficiency and OP1 dB/OIP3). Thus, reaching the required design targets could be time consuming task.

Figure 7 shows the dependency of OIP3 on the biasing voltages of both main and auxiliary amplifiers. As shown, OIP3 at backed off power increases with increasing the biasing voltage of one of the two amplifiers. However, the best efficiency, as shown in Figure 8, is achieved when Vm = Va = 370 mv which corresponds to an OIP3 peaking around 10 dBm output power (as shown in Figure 7). Thus, from Figure 7 and Figure 8, it is noted that the best non-linearities cancellation provided by the architecture is achieved for this design when Vm = Va = 370 mv. The OP1 dB is determined by the biasing voltage of the main amplifier, as shown in Figure 9. From Figure 5, Figure 6, Figure 7, Figure 8 and Figure 9, it is indicated that the channel widths of the transistors and their biasing affect the OP1 dB, OIP3, and efficiency, and there is an optimum set of design parameters that leads to the optimum solution to satisfy the design requirements. The dependence of OP1 dB on the values of the output matching network is simulated in Figure 10 and Figure 11. As expected, the output matching network affects significantly the OP1 dB. This is because the values of those passive components determine the optimum impedance for power matching.

Figure 12 and Figure 13 show the changes in OP1 dB and S21 versus the value of the cascode gate capacitor, Cgate. As depicted, the value of Cgate affects the OP1 dB. This is because the voltage swings at the drain of the cascode devices are divided equally between the voltages across the drain and source terminals of the main and cascode transistors using Cgate. However, the gain is reduced as the value of this capacitance decreases (another trade-off). Figure 14 and Figure 15 show the effect of changing cascode gate biasing voltage on OP1 dB and OIP3. Both OP1 dB and OIP3 are affected because they depend on the non-linear output impedance of the main device.

The sensitivity analysis is summarized in

Table 2. Performance specifications and their corresponding design parameters.

Performance Specifications	Design Parameters
OP1 dB	Cout, Lout, and L_CT Wm, Wa, Vm, Va, and Cgate
OIP3	Vm, Va, Wm, and Wa
Gain (S21)	Cout, Lout, and L_CT Lin, C1, C2, C3, and C4 Wm, Wa, Vm, Va, and Cgate
PAE	Wm and Wa Vm and Va

, which shows the performance specifications and their corresponding design parameters to which they are most sensitive. Based on the above sensitivity analysis and the understanding of the trade-offs between the performance specifications, the proposed design-aware optimization is created.

4.2. The Optimization Flow

The proposed optimization flow used within the tool is presented in Figure 16. The optimization engine uses the BFGS optimization algorithm implemented within the virtuoso environment. The flow relies on five main steps. Below is the explanation of each step and how it is integrated within the tool:

• The user enters the frequency of operation and the required specifications (minimum OP1 dB, minimum OIP3 at 6 dB back off power, minimum OIP3 at 10 dB back-off power and minimum gain (S21)) to the tool web interface. The minimum value of OIP3 at 6/10 dB back-off power will determine the efficiency of the power amplifier. In addition, weights for each targeted design specification are defined.
• The stability of the amplifier is considered as a hard constraint that needs to be met regardless of the performance specifications.
• The initial values of the design parameters need to be defined at the beginning of the optimization. Table 1 shows typical values for those parameters.
• Step 1 in Figure 16: the optimization of the input matching network parameters (C₁, C₂, C₃, C₄, and Lin) is carried out. The input to this step is the frequency and performance specifications entered by the user. The optimized values are input to steps 2, 3, 4, and 5.
• Step 2 in Figure 16: the optimization of the output matching network parameters (Cout, Lout, and L_CT) is carried out. The input to this step is the frequency, performance specifications entered by the user, and the optimized parameters from step 1. The optimized values are input to steps 3, 4, and 5.
• Step 3 in Figure 16: the optimization of the biasing and sizing of transistors (Vm, Va, Wm, and Wa) is carried out. The input to this step is the frequency, performance specifications entered by the user, and the optimized parameters from steps 1 and 2. At the end of this step, the modelled parasitic capacitances arising from the transistor layout and its interconnects (Cgs, Cgd, and Cds) are updated corresponding to the optimized widths of the transistors (Wm and Wa). The optimized values are input to steps 4 and 5.
• Step 4 in Figure 16: the optimization of the gate capacitance (C₇ and C₈) and the cascode gate DC biasing voltage (Vcas) are carried out. The input to this step is the frequency, performance specifications entered by the user, and the optimized parameters from steps 1, 2, and 3. The optimized values are input to step 5.
• Step 5 in Figure 16: it is considered an evaluation point, which determines the next step in the optimization flow.
• If all the specifications (OP1 dB, S21, and OIP3) or (OP1 dB and S21) or (OIP3 and S21) or S21 failed, then the optimization flow is directed to step 1, where the values of the input matching network parameters are being optimized again, then all the rest of the steps will follow in succession. It is to be noted that when step 1 is carried out this time, all the other design parameters have new optimized values that differ from their previous values when step 1 was visited for the first time.
• If (OP1 dB and OIP3) or OP1 dB failed, then the optimization flow is directed to step 2, then all the rest of the steps (3, 4, and 5) will follow.
• If OIP3 failed, the optimization flow is directed to step 3, and then steps 4 and 5 will follow.
• The optimization flow stops when the best achieved design point is obtained based on the pre-defined weighting factors.
• The tool will return back to the web interface: the achieved values for all the required performance specifications, the consumed DC power, PAE at OP1 dB and at 6 dB back-off power, the values of the optimized design parameters, the circuit schematic, a template of the layout of the circuit, and a GDSII file for further modifications.

5. Automation and Test Cases Results

The proposed design tool of the power amplifier is used for automatic sizing. Three test cases are applied at three different frequencies (7, 10, 13 GHz). The 65 nm technology node is used for these test cases. Initially, the user specifies the required performance specifications: frequency of operation, OP1 dB, Gain, and OIP3 at 6 dB back off and 10 dB back off power to the web interface. Weights for different performance specifications are also defined by the user. At the end of the automatic sizing, values of the different design parameters, as well as the achieved performance specifications, are displayed as output. A GDSII layout template for the adopted architecture is also generated.

Figure 17, Figure 18, Figure 19, Figure 20 and Figure 21 show the achieved Pout, OIP3, PAE, AM-AM, and AM-PM distortions and S21 for the three different frequencies (7,10, and 13 GHz). The targeted OP1 dB is higher than 18 dBm, gain is higher than 7 dB, OIP3 is higher than 24 dBm at 6 dB back-off power. As depicted from Figure 17, Figure 18, Figure 19, Figure 20 and Figure 21, the targeted performance specifications are achieved.

Table 3. The required and achieved performance specifications.

Performance Specifications	Required	Achieved
		7 GHz	10 GHz	13 GHz
OP1 dB	>18 dBm	19 dBm	18.2 dBm	18.1 dBm
OIP3 at 6 dB back-off power	>24 dBm	26 dBm	25.2 dBm	24.7 dBm
S21	>7 dB	8.7 dB	7.1 dB	7.3 dB
DC Consumed Power	-	89.5 mw	89.52 mw	55 mw
PAE at OP1 dB	-	27%	22 %	29%
PAE at 6 dB back-off	-	22%	9%	15%

show the required and achieved performance specifications. Finally, Figure 22 shows the layout template of the amplifier which is provided by the proposed design automation tool. A computer with an Intel core i₇ processor with 12 GB RAM is used to run this tool.

6. Discussion

The four main aspects that are used in the comparison of the different approaches of RF design optimization and automation are: performance evaluators, inductance modelling, included layout parasitic components and the used optimizers.

Table 4. Summary of the recent approaches in the sizing and optimization of RF circuits.

Work	Performance Evaluator	Inductor Modelling	Layout Included Parasitic Components	Optimizer
[15], 2000	Circuit Simulator and Performance Models	Not Included	Device and interconnect C and CC	Evolutionary Algorithms
[13], 2001	Parametric Equations	Parasitic-included compact model	Not Included	Simulated-Annealing based
[24], 2002	Circuit Simulator	In-the-loop EM simulation	Not Included	Simulated-Annealing based
[25], 2004	Performance Models	Linear behavior into PMs	Not specified	Simulation-based
[14], 2012	Circuit Simulator	EM-based surrogate model built in the loop	Not Included	Evolutionary Algorithms
[18], 2016	Circuit Simulator	2-п model	Other passive components	Evolutionary Algorithms and simulated-Annealing
[11], 2017	Circuit Simulator	EM-Simulated Pareto-Optimal Front (POF) obtained a priori	Not Included	Particle Swarm Optimization (PSO)
[17], 2017	Performance Models	Linear behavior into PMs	Device and interconnect C, CC, and R	Evolutionary Algorithm based
[16], 2022	Circuit Simulator	2-п model	Not Included	Meta-heuristics algorithms
This Work	Circuit Simulator	Foundry process design kit (PDK) model	Device and interconnect C and CC	BFGS algorithm

shows a summary of the recent approaches in the sizing and optimization of RF circuits [9].

The performance evaluation is carried out either by using performance models, parametric equations, or circuit simulators. Performance models are inaccurate and must be varied with the variation of circuit topologies [9]. Circuit simulators are the most accurate performance evaluators.

The inductance modelling differs from one approach to another, as shown in Table 4. In the proposed tool, the inductance used is the foundry process design kit (PDK) inductance, modelling the inductance layout parasitic components with high accuracy. Using the PDK inductance model allows the optimization of the physical parameters of the inductance, such as the inner radius and the number of turns to reach the required performance specifications. This results in good estimation of the results of post layout simulations.

Including layout parasitic components in the optimization process differs from one approach to another, as shown in Table 4. In the proposed tool, the post layout simulations of the parasitic extracted view of the transistor along with its interconnects was carried out prior to the optimization process and the resulting parasitic capacitances were included in the optimization process as functions of the sizes of the transistors.

The optimization process differs according to the optimization algorithm used as shown in Table 4. The proposed tool uses BFGS optimizer that is employed by cadence-virtuoso. The BFGS optimizer is used to select the best values of the design parameters that can achieve the required specifications.

7. Conclusions

A parasitic-design-aware simulation-based design tool was proposed for highly linear RF power amplifiers within this paper. Both the optimization steps and design methodology were explained and they rely on the knowledge of the circuit to obtain the design parameters. The proposed tool does not need lengthy simulations when compared to the existing approaches. With parasitic modelling, the design point is close to the final design after layout. The proposed tool was verified to design a highly linear RF power amplifier at three different frequencies (7 GHz, 10 GHz, and 13 GHz) using 65 nm technology node. The results showed that an OP1 dB higher than 18 dBm, gain/S21 higher than 7 dB, and OIP3 higher than 24 dBm at 6 dB back-off power are obtained.