Low Computing Leakage, Wide-Swing Output Compensation Circuit for Linearity Improvement in SRAM Multi-Row Read Computing-in-Memory

Round 1

Reviewer 1 Report

1.The authors should clearly mention the challenges in the abstract. Mention a few recent techniques and highlight what are the challenges faced by the systems and then present the proposed objective. Objectives and challenges are quite different from each other.

2. Introduction and Literature work should be in separate section for clear understanding.

3. Why the author have used the simple bitline feedback?

4. What is the novelty in this research work?

5. How will you calculate the integral nonlinearity (INL) values? How will you obtain the tested value and ideal value?

6.  Experimental section needs detailed explanation for the results obtained.

7.  Grammar errors should be taken care throughout the manuscript.

8. Cite some suitable references are listed below:

Bansal, Malti, Harmandeep Singh, and Gaurav Sharma. "A Taxonomical Review of Multiplexer Designs for Electronic Circuits & Devices." Journal of Electronics 3, no. 02 (2021): 77-88.

 

Author Response

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Author Response File: Author Response.pdf

Reviewer 2 Report

The manuscript (electronics-1641981), Low Computing Leakage, Wide-Swing Output Compensation Circuit for Linearity Improvement in SRAM Multi-Row Read Computing-In-Memory, shows quite interesting proposed results in SRAM multi-row read for potential computing-in-memory applications. Authors presented quite comprehensive analysis electrically.

One comment this referee would like to provide here for authors' reference here is that, in Table 2, can authors provide the total chip area, power consumption, speed as well in the Table? Also, can authors add some recent works in terms of the using 14 or 10nm technology nodes in this demonstration? Did we see the benefit of the technology scaling or not as compared in Table 2?

Due to the above comments, this referee would like to put the manuscript status as "Major Revision" in the current phase. 

Author Response

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Author Response File: Author Response.pdf

Reviewer 3 Report

The authors present a compensation circuit to improve Computing in Memory performance. The work is well written and the comparison with existing work shows signficant improvement in performance for several key metrics.

Author Response

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Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Satisfied with the revised version. Recommended for final acceptance. 

Reviewer 2 Report

Authors have replied to this referee in detail. No further comments from this referee.