A Novel Carrier Scheme Combined with DPWM Technique in a ZVS Grid-Connected Three-Phase Inverter

Abstract

In this paper, a novel switching scheme using discontinuous pulse-width modulation (DPWM) for a zero-voltage switching (ZVS) grid-connected three-phase inverter is proposed. ZVS in the main and auxiliary switches was achieved. Moreover, the reverse recovery currents of the anti-parallel diodes in the main switches were suppressed. A circuit analysis was performed, and a simulation was carried out. Furthermore, a prototype of the ZVS grid-connected three-phase inverter was constructed to verify the effectiveness of the proposed PWM control scheme. Both the simulation and experimental results verified the validity of the proposed PWM control scheme.

1. Introduction

Three-phase inverters are widely utilized in PV systems, wind power generation, electrical vehicles, and uninterruptible power systems, etc. Especially, distributed grid-connected inverters play an important role in renewable energy generation systems as the interface between the renewable energy and the grid. The conventional six-switch three-phase inverter is a preferred topology with several advantages such as lower current stress and higher efficiency. However, the anti-parallel diodes of the six switches have a reverse recovery problem that causes many switching loss and electromagnetic interference problems.

Over the past few years, various soft-switching techniques for three-phase inverters have been studied [1,2,3,4,5,6,7,8,9,10,11,12]. Generally, the voltage of the DC link is periodically resonated to a zero voltage level to create soft-switching conditions, which causes the three-phase six switches achieve zero-voltage switching at the corresponding time. The typical method to achieve ZVS is by adding an auxiliary resonant circuit in the inverter [2]. According to the different locations of the auxiliary circuit, the soft-switching method of DC–AC voltage-source inverters can be classified into two categories: DC-side auxiliary circuit topologies [1,2,3,4,5,6,7] and AC-side auxiliary circuit topologies [8,9,10,11]. In DC-side auxiliary circuit topologies, an auxiliary circuit is inserted between the DC voltage source and the main six-switch bridge to achieve the zero-voltage condition. Generally speaking, according to the clamp capacitor location, the clamp capacitor can be in series with resonant inductance [1,2] or in series with the auxiliary switch [3,4,5,6,7] to achieve ZVS. If the clamp capacitor is in series with the auxiliary switch, the reverse recovery current of the anti-parallel diodes can be easily suppressed, but the switch voltage stress is high. If the clamp capacitor is in series with the resonant inductor, the switch voltage stress is equal to the DC link voltage. In addition, different PWM strategies for ZVS have been developed. The space-vector pulse-width modulation (SVPWM) control strategy has been utilized for ZVS in the literature [1,2,3,7], and the discontinuous pulse-width modulation (DPWM) control strategy has also been studied to achieve ZVS in the literature [12,13]. However, although there is no additional component added in the circuit [12], the inverter-side current is larger and the current stress on the main switches is higher than that in the literature [1,2,3,4,5,6,7]. In addition, the filter design is more complicated due to the variable switching frequency operation. In [13], in order to unify the PWM methods for soft-switching active-clamping three-phase power converters, the edge-aligned PWM (EA-PWM) was proposed to simplify the control method. Nevertheless, the EA-PWM needs three-phase current sensors to obtain information on the filter’s current polarities to achieve ZVS in the active switches. Moreover, the soft-switching condition is affected by the modulation index, which may reduce the ability to achieve ZVS in any modulation index.

In the DPWM control strategy, only two of three legs are switching at any time. Therefore, the switching loss and electromagnetic interference (EMI) can be reduced. In order to reduce the switching loss, in this paper, a carrier-based ZVS DPWM (CB-DPWM) control strategy was studied for grid-connected three-phase inverters. A simple saw-tooth carrier waveform with positive and negative slope rates was developed to achieve ZVS in both the main and auxiliary switches. Using this method, the auxiliary switch, $S_7$, control signal can be generated more easily compared with the literature [1,2]. In addition, the ZVS of the main and auxiliary switches can be obtained. Moreover, the reverse recovery current of the anti-parallel diodes in the main switches can also be reduced in the proposed modulation scheme. Furthermore, the voltage stress of main and the auxiliary switches was still equal to DC bus voltage.

The remaining contents of this paper are organized as follows. First, the circuit configuration and the operating principle of the proposed ZVS DPWM control strategy are described in Section 2 and Section 3. Based on the proposed ZVS DPWM control strategy, simulation and experimental results are offered in Section 4 to verify the validity of the proposed control strategy for a ZVS grid-connected three-phase six-switch inverter. Finally, some conclusions are offered in Section 5.

2. Proposed Modulation Scheme

The circuit of the ZVS inverter is shown in Figure 1 [1,2]. The circuit topology is composed of a standard six-switch grid-connected inverter and an auxiliary resonant circuit that is connected with the distributed energy resources (DERs) in the DC side. In the auxiliary circuit, the auxiliary switch, $S_7$, is conducted most of the time during the switching period. While the auxiliary switch, $S_7$, is turned ON, the resonant inductor, $L_r$, is charged. While the auxiliary switch, $S_7$, is turned OFF, the energy stored in the resonant inductor, $L_r$, releases energy to the parasitic capacitors of the main switches. When the auxiliary switch, S₇, is switched once in a PWM period, both the main and auxiliary switches can achieve ZVS. In addition, the reverse recovery current of the main switches can be suppressed. Thus, the system’s conversion efficiency can be increased.

The proposed DPWM control strategy and corresponding carrier waveform are shown in Figure 2. In order to achieve zero-voltage switching and decrease the switching numbers of the main and auxiliary switches, a ZVS carrier-based PWM is proposed to reduce switching loss and improve energy conversion efficiency. The proposed control strategy judges three-phase DPWM control signals to determine the slope of the saw-tooth carrier waveform. When one of the three-phase DPWM control signals reaches high level (i.e., ${\mathrm{V}}_{dc}$/2), the slope of the saw-tooth waveform is negative, and when one of the three-phase DPWM control signals reaches low level (i.e., $-{\mathrm{V}}_{dc}$/2), the slope of the saw-tooth carrier waveform is positive.

In the proposed control scheme, the zero vectors, $V_0$ and $V_7$, were selected as shown in Figure 3, and the auxiliary switch, $S_7$, control signal is determined to achieve ZVS in the main $S_1$–$S_6$ and $S_7$ switches. The generation of the $S_7$ signal is mainly based on the dead-time among the three legs in the three-phase inverter as shown in Figure 4. Take sector I and sector II as an example. In the control signal in sector I, one of the three-phase DPWM control signals reaches high level, i.e., DPWMa. Then, the negative slope of the saw-tooth waveform is utilized, and the control signals are generated as shown in Figure 4a. In the meantime, the zero vector, $V_7$, is naturally selected. If the dead-time of any two legs occur at the same time, the $S_7$control signal is established. In the same manner, the corresponding control signals in sector II are shown in Figure 4b, and the positive slope of the saw-tooth waveform is utilized, the zero vector, $V_0$, is naturally selected, and $S_7$control signal is also established.

3. Analysis of DPWM Grid-Connected Inverter

According to the proposed DPWM method and the zero vector selection in Figure 2, Figure 3 and Figure 4, there are twelve sectors in a line-cycle period. The twelve-sector modulation can be operated in sequence. Take sector I as an example and assume a three-phase current: $i_a>0>i_b>i_c$. For a convenient explanation of how the proposed modulation scheme works, the following assumptions were made to simplify the analysis of the grid-connected ZVS inverter;

(1)

The main switches, $S_1$–$S_6$, and auxiliary switch, $S_7$, were considered to be ideal switches connected with corresponding anti-parallel diodes;

(2)

All of the parasitic capacitances, $C_{r1}$–$C_{r7}$, paralleled the switches $S_1$–$S_7$, respectively;

(3)

In this architecture, the current ripple of $i_a, i_b,$ and $i_c$ in grid-side inductor was small, and$i_a, i_b,$ and $i_c$ were considered as constant current sources in a switching period;

(4)

The capacitance of the clamping capacitor, $C_c$, was so large that the voltage ripple across it was relatively small; thus,$v_{Cc}$ can be regarded as a voltage source;

(5)

The resonant frequency of $C_c$ and $L_r$ was much lower than the operation frequency of the inverter. In this paper, the filter resonant frequency was 707 Hz, and the operation switching frequency was 18 kHz;

(6)

In order to explain the reverse recovery current of switch body diode, i_cex, x ∈ {1, 2, …, 7} denotes the switch current including the parasitic capacitor current, and i_sx, x ∈ {1, 2, …, 7} denotes the switch current except the parasitic capacitor current.

The circuit operation, equivalent circuit, and theoretical waveform are illustrated in Figure 5, Figure 6 and Figure 7, respectively. The following are the working stages of the proposed ZVS DPWM control strategy for grid-connected three-phase inverters.

State 1 (${\mathit{t}}_{\mathbf{0}}~{\mathit{t}}_{\mathbf{1}}$):

The circuit is operated at vector state 111. The main switch, $S_1$, auxiliary switch, $S_7$, and the anti-parallel diodes,$D_3$ and $D_5$, are ON. The inverter is operated at zero vector. The resonant inductor, $L_r$, is charged by the clamping voltage,$v_{Cc}$. The equivalent circuit is shown in Figure 6a, and the relationship between $L_r$ and$C_c$ is obtained as follows:

$$v_{Lr}=L_r\frac{\mathrm{d}{i}_{Lr}}{\mathrm{d}t}=-v_{Cc}$$

(1)

State 2 (${\mathit{t}}_{\mathbf{1}}~{\mathit{t}}_{\mathbf{2}}$):

The resonant inductor, $L_r$, resonates with $C_{r2},C_{r4},C_{r6},$ and $C_{r7}$. The auxiliary switch, $S_7$, is turned OFF at $t_1$ under the ZVS condition due to the resonance where$C_{r2},C_{r4}, \mathrm{and} C_{r6}$ is discharging and $C_{r7}$ is charging in this moment. During this state, switches S₃ and S₅ are turned OFF. The energy stored in inductor, $L_r$, is returned to the DC capacitor. The equivalent circuit is shown in Figure 6b, and the relationship between$C_c$, $C_r$, and $L_r$ is expressed as follows:

$$v_{Lr}=L_r\frac{\mathrm{d}{i}_{Lr}}{\mathrm{d}t}=(-v_{Cc}+V_{dc}-v_{Cr})$$

(2)

$$-3C_r\frac{\mathrm{d}{v}_{Cr}}{\mathrm{d}t}+C_{r7}\frac{\mathrm{d}(V_{dc}-v_{Cr})}{\mathrm{d}t}=-i_{Lr}$$

(3)

State 3 (${\mathit{t}}_{\mathbf{2}}~{\mathit{t}}_{\mathbf{3}}$):

At this time, the circuit is operated at vector state 100. The voltages of $C_{r2},C_{r4},\mathrm{and} C_{r6}$ are discharged to zero, and the voltage of $C_{r7}$ is charged to $V_{dc}.$ The anti-parallel diodes $D_2,D_3,D_4,D_5,\mathrm{and} D_6$ are ON. The switches S₄ and S₆ are turned ON under ZVS conditions at instant time t₂, and the resonant inductor, $L_r$, suppresses the reverse recovery current of the anti-parallel diode, $D_3$. The equivalent circuit is shown in Figure 6c, and the relationship between $i_{Lr}$ and $v_{Cc}$ is derived as follows:

$$v_{Lr}=L_r\frac{\mathrm{d}{i}_{Lr}}{\mathrm{d}t}=-(v_{Cc}-{\mathrm{V}}_{dc})$$

(4)

State 4 (${\mathit{t}}_{\mathbf{3}}~{\mathit{t}}_{\mathbf{4}}$):

The main switches $S_1$, $S_4$, and $S_6$ remain ON, and the resonant inductor, $L_r$, suppresses the reverse recovery current of the anti-parallel diodes, $D_2$ and $D_5$. The power flows from the DC side to the AC side. The equivalent circuit is shown in Figure 6d, and the relationship between $i_{Lr}$ and $v_{Cc}$ is expressed as follows:

$$v_{Lr}=L_r\frac{\mathrm{d}{i}_{Lr}}{\mathrm{d}t}=-(v_{Cc}-{\mathrm{V}}_{dc})$$

(5)

State 5 (${\mathit{t}}_{\mathbf{4}}~{\mathit{t}}_{\mathbf{5}}$):

The resonant inductor, $L_r$, resonates with $C_{r2},C_{r3},C_{r5}, \mathrm{and}$ $C_{r7}$, and the anti-parallel diode, $D_7$, is ready to be turned ON. During this state, $C_{r2},C_{r3}, \mathrm{and} C_{r5}$ are charged, and $C_{r7}$ is discharged. The power still flows from the DC side to the AC side. The equivalent circuit is shown in Figure 6e, and the relationship between the voltage and current can be obtained as follows:

$$v_{Lr}=L_r\frac{\mathrm{d}{i}_{Lr}}{\mathrm{d}t}=(-v_{Cc}+V_{dc}-v_{Cr})$$

(6)

$$3C_r\frac{\mathrm{d}{v}_{Cr}}{\mathrm{d}t}+i_{La}=C_{r7}\frac{\mathrm{d}(V_{dc}-v_{Cr})}{\mathrm{d}t}+i_{Lr}$$

(7)

State 6 (${\mathit{t}}_{\mathbf{5}}~{\mathit{t}}_{\mathbf{6}}$):

At this state, the circuit is still operated at vector state 100, and the main switches,$S_1$, $S_4$, and $S_6$, are ON. The auxiliary switch, $S_7$, is turned ON under the ZVS condition. The voltage of the clamping capacitor, $v_{Cc}$, is charged by the resonant inductor current, $i_{Lr}$, and the power flows from the DC side to the AC side. The equivalent circuit is shown in Figure 6f, and the relationship between $i_{Lr}$ and $v_{Cc}$ is as follows:

$$v_{Lr}=L_r\frac{\mathrm{d}{i}_{Lr}}{\mathrm{d}t}=-v_{Cc}$$

(8)

State 7 (${\mathit{t}}_{\mathbf{6}}~{\mathit{t}}_{\mathbf{7}}$):

At this state, the circuit is operated at vector state 100. The phase current $i_b$ discharges voltage $v_{Cr3}$ and charges voltage $v_{Cr4}$. The main switch, $S_4$, is turned OFF under the ZVS condition, and the power flows from the DC side to the AC side. The equivalent circuit is shown in Figure 6g, and the relationship between the voltage and current can be derived as follows:

$$v_{Lr}=L_r\frac{\mathrm{d}{i}_{Lr}}{\mathrm{d}t}=-v_{Cc}$$

(9)

$$i_{Lb}=-C_{r3}\frac{\mathrm{d}{v}_{Cr3}}{\mathrm{d}t}+C_{r4}\frac{\mathrm{d}{v}_{Cr4}}{\mathrm{d}t}$$

(10)

State 8 (${\mathit{t}}_{\mathbf{7}}~{\mathit{t}}_{\mathbf{8}}$):

At this state, the circuit is operated at vector state 110. The main switches, $S_1$ and $S_6$, the auxiliary switch, $S_7$, and the anti-parallel diode, $D_3$, are in the conducting state. The power flows from the DC side to the AC side. The equivalent circuit is shown in Figure 6h, and the relationship between$i_{Lr}$ and $v_{Cc}$ is expressed as follows:

$$v_{Lr}=L_r\frac{\mathrm{d}{i}_{Lr}}{\mathrm{d}t}=-v_{Cc}$$

(11)

State 9 (${\mathit{t}}_{\mathbf{8}}~{\mathit{t}}_{\mathbf{9}}$):

At this state, the circuit is still operated at vector state 110. The phase current$i_c$ discharges voltage $v_{Cr5}$ and charges voltage $v_{Cr6}$. The main switch, $S_6$, is turned OFF under the ZVS condition, and the power flows from the DC side to the AC side. The equivalent circuit is shown in Figure 6i. After this stage, the circuit operation returns to the first stage and starts a new cycle. The relationship between the voltage and current can be obtained as follows:

$$v_{Lr}=L_r\frac{\mathrm{d}{i}_{Lr}}{\mathrm{d}t}=-v_{Cc}$$

(12)

$$i_{Lc}=-C_{r5}\frac{\mathrm{d}{v}_{Cr5}}{\mathrm{d}t}+C_{r6}\frac{\mathrm{d}{v}_{Cr6}}{\mathrm{d}t}$$

(13)

4. Simulation and Experimental Results

After the explanation of the theoretical analysis of the proposed ZVS PWM control scheme, the simulation and experiment were carried out to verify the validity the proposed ZVS PWM control scheme. Hence, the system parameters of the grid-connected ZVS inverter are listed in

Table 1. System parameters for the simulation and experiment.

Symbol	Description	Value
Va, Vb, Vc	AC grid phase/line voltage	127/220 Vrms
Vbus Cdc fs La, Lb, Lc Cga, Cgb, Cgc Lr Cr Cc	DERs DC voltage DC-side capacitor Switching frequency Filter inductor Filter capacitor Resonant inductor Parasitic/resonant capacitor Clamping capacitor	450 V 2200 µF 18 kHz 2.3 mH 22 µF 40 µH 2 nF 100 µF

for the simulation and experiment.

The system control block of the grid-connected ZVS inverter is shown in Figure 8. The grid voltage and inverter output current were sensed and fed into the controller. The three-phase voltages and currents were transferred from nature reference frame to the synchronous reference frame. There exist three control loops in the proposed system. The first, second, and third control loops were the droop control, voltage control, and current control, respectively, as shown in Figure 8. The ZVS voltage source inverter was operated at a grid-supporting condition. In this paper, a 3 kW system was constructed for the simulation and experiment to verify the validity of the proposed ZVS PWM control scheme. The software PSIM version 9.1 was adopted for the simulation. In the experiment, the adopted active switches, $S_1–S_7$, were with an insulated-gate bipolar transistor (Fuji 2MBI100VA-060-50) that had a parasitic capacitor of 2 nF. The system controller was realized using DSP (TMS320F28335) manufactured by Texas Instruments and FPGA (Cmod-A7-35T) manufactured by Digilent, Inc. The design parameters of the circuit are listed in Table 1.

Figure 9a,b show the simulation and experimental results of grid-connected voltage $v_a$, $v_b$, $v_c$ and output phase current $i_c$ respectively. As can be observed from Figure 9, inverter output current $i_c$ is phase shifted by 180 degrees from grid-connected voltage $v_c$. That means the power flows from the DC side to grid side.

The simulation and experimental waveforms of the voltage, $v_{ce}$, and current, $i_{ce},$of the main switch, $S_4$, operated in sector I are shown in Figure 10a,b, respectively. As can be observed form Figure 10, the ZVS ON was achieved in the switch$S_4$ and, at this time, the reverse recovery current in body diode $D_3$ of switch S₃ was suppressed as shown in Figure 11a,b for the simulation and experimental results, respectively. As can be seen from the simulation in Figure 11a, the current i_S3, which flowed through the body diode of switch S₃, was successfully suppressed when the switch S₃ was turned OFF. It should be noticed that in Figure 11b, the measured waveform can only show the current i_ce3, which is the total current flowing through the switch and the parasitic capacitor. The simulation and experimental waveforms of voltage $v_{ce7}$ and current $i_{ce7}$ of the $S_7$ are shown in Figure 12a,b, respectively. It follows from Figure 12 that ZVS ON was indeed achieved in the $S_7$. The simulation and experimental waveforms of the $v_{Cc}$ and the $i_{Lr}$ in the auxiliary circuit are shown in Figure 13a,b, respectively. The $v_{Cc}$ was at a low voltage level, and $L_r$ was magnetized and demagnetized via control by the S₇. From Figure 9, Figure 10, Figure 11, Figure 12 and Figure 13, one can see that the simulation and experimental results were in close agreement. The ZVS in both the main and auxiliary switches were indeed achieved. In addition, the reverse recovery current of the main switches was suppressed in the proposed ZVS DPWM control strategy.

The conversion efficiency of the implementation is shown in Figure 14 in the comparison between the traditional sinusoidal pulse-width modulation (SPWM) without auxiliary circuit and the proposed ZVS DPWM control scheme. From a light load to a full load, the proposed ZVS DPWM control scheme had higher efficiency than the SPWM operation. The efficiency was significantly improved and reached a conversion efficiency of 97.1% at a load of 3 kW.

Finally, to further reveal the potential merits of the proposed PWM control scheme,

Table 2. Comparison of the different ZVS methods for inverters.

-	Extra Elements	Soft Switching Range	Switching Frequency (fs)	Control Complexity	Switch Voltage Stress	Switch Current Stress	Filter Design
[2]	LC+ switch	Full ZVS range	Fixed	Normal	Vdc	Low	LC
[3]	LC+ switch	Full ZVS range	Fixed	Difficult (leg-short operation)	Vdc + Vcc	Low	LC
[12]	None	Full ZVS range	Variable	Normal	Vdc	High	LCL
[13]	LC+ switch	Full ZVS range	Fixed	Simple (three carrier signals)	Vdc + Vcc	Low	LC
CB-DPWM	LC+ switch	Full ZVS range	Fixed	Simple (one carrier signal)	Vdc	Low	LC

is provided to summarize the comparisons of the extra elements, soft switching range, switching frequency, control complexity, switch voltage stress, and current stress as well as the filter design of the literature [2,3,12,13] and the proposed PWM control scheme.

5. Conclusions

In this article, a ZVS DPWM strategy for a grid-connected three-phase inverter was proposed. The saw-tooth carrier waveform with positive and negative slopes was utilized to generate the control signal of $S_7$, and it achieved ZVS in both the main and auxiliary switches. In addition, the reverse recovery current in the anti-parallel diodes of the main switches were suppressed. The circuit operation was clearly explained. Finally, a prototype was constructed. Both the simulation and experimental results verified the validity of the proposed ZVS DPWM strategy for the grid-connected three-phase inverter.