L_g = 50 nm Gate-All-Around In_0.53Ga_0.47As Nanosheet MOSFETs with Regrown In_0.53Ga_0.47As Contacts

Abstract

In this paper, we report the fabrication and characterization of L_g = 50 nm Gate-All-Around (GAA) In_0.53Ga_0.47As nanosheet (NS) metal-oxide-semiconductor field-effect transistors (MOSFETs) with sub-20 nm nanosheet thickness that were fabricated through an S/D regrowth process. The fabricated GAA In_0.53Ga_0.47As NS MOSFETs feature a bi-layer high-k dielectric layer of Al₂O₃/HfO₂, together with an ALD-grown TiN metal-gate in a cross-coupled manner. The device with L_g = 50 nm, W_NS = 200 nm and t_NS = 10 nm exhibited an excellent combination of subthreshold-swing behavior (S < 80 mV/dec.) and carrier transport properties (g_{m_max} = 1.86 mS/μm and I_ON = 0.4 mA/μm) at V_DS = 0.5 V. To the best of our knowledge, this is the first demonstration of In_xGa_1-xAs GAA NS MOSFETs that would be directly applicable for their use in future multi-bridged channel (MBC) devices.

1. Introduction

Non-planar and multi-gate architectures are the backbone of improved electrostatics in Si MOSFETs, together with the use of high-mobility channel materials [1,2,3,4,5,6,7]. In this dimensional range, only a high aspect ratio (AR) 3D configuration with a fin or nanowire (NW) architecture can meet the scaling requirements. Recently, 3D MOSFETs with sub-10nm physical dimensions have been extensively demonstrated in various material systems, including Si, SiGe and In_xGa_1−xAs [1,2,3,4,5]. Among these advancements, the Gate-All-Around (GAA) nanosheet (NS) FET architecture is believed to be the final evolutionary step for Moore’s law [8,9,10].

In_xGa_1-xAs is a promising channel material for beyond-CMOS logic scaling and memory applications, due to its extraordinary electron’s carrier transport properties including very high injection velocity (v_inj) [11]. Indeed, there have been many impressive demonstrations on planar In_xGa_1-xAs MOSFETs, FinFETs, NW-MOSFETs and NS-MOSFETs [3,4,12,13,14,15]. As in [8], it is of great importance to develop an NS MOSFET technology that would be compatible with a multi-level stacked NS, namely multi-bridged-channel FET (MBCFET). In this paper, we demonstrate GAA In_xGa_1-xAs NS MOSFETs on a 3-inch InP substrate with selectively regrown n+ In_0.53Ga_0.47As S/D contacts that were obtained via a metal-organic chemical vapor deposition (MOCVD) technique, where as-grown In_0.53Ga_0.47As and In_0.52Al_0.48As layers act as a nanosheet channel and a sacrificial layer, respectively. Here, we choose an In_0.53Ga_0.47As/In_0.52Al_0.48As quantum-well (QW) structure, where the In_0.52Al_0.48As sacrificial layers are selectively etched against the In_0.53Ga_0.47As nanosheets using an HCl-based wet etchant solution. A unique combination of process integration and epitaxial layer design enables the demonstration of the functionality of L_g = 50 nm GAA In_0.53Ga_0.47As NS MOSFETs with excellent ON/OFF switching characteristics that would be directly extensible to future MBCFETs.

2. Experimental Procedure

Figure 1 illustrates the cross-sectional schematic of a GAA In_0.53Ga_0.47As NS MOSFET that is in this work. At its heart is a single In_0.53Ga_0.47As nanosheet layer that is electrically connected to both n+ In_0.53Ga_0.47As S/D contact layers. Geometrical definitions of W_NS (width of a unit NS) and t_NS (thickness of a unit NS) are also provided in Figure 1. For a choice of the sacrificial layer, we selected an In_0.52Al_0.48As layer to avoid an intermixing problem during the growth of the In_0.53Ga_0.47As/InP QW layer that was achieved via MOCVD technique that prevented the InP sacrificial layers from being removed isotropically. Both sidewalls of the In_0.53Ga_0.47As NS channel layer along the 011 direction were electrically in contact with the n+ In_0.53Ga_0.47As layers that were regrown selectively using a MOCVD technique with a Te concentration of 5 × 10¹⁹ cm⁻³, at a relatively high growth temperature of 600 °C. This growth condition helped to not only enable selective epitaxy of the regrown n+ In_0.53Ga_0.47As layers, except for an SiO₂ dummy active area, but also effectively remove the native oxides on the exposed sidewall surfaces of the In_0.53Ga_0.47As/In_0.52Al_0.48As QW along the 011 direction and the exposed surface of an InP etch-stopper along the 100 direction, respectively.

Next, this section explains in detail the fabrication procedure to demonstrate the GAA In_0.53Ga_0.47As NS MOSFETs that are proposed in this work. Figure 2 highlights a process flow and key unit process steps. From bottom to top, the epitaxial layer structure that was used for the device fabrication consisted of a 50-nm-thick bottom In_0.52Al_0.48As sacrificial layer, a 10 nm-thick-In_0.53Ga_0.47As nanosheet channel layer and a 50-nm-thick upper In_0.52Al_0.48As sacrificial layer. First, line and space patterns were defined using a positive photo-resist (PR) on a plasma-enhanced-chemical-vapor-deposition (PECVD)-grown SiO₂ layer, where the opened SiO₂ area was etched by CF₄/Ar-based plasma and the remaining PR was stripped. Subsequently, the exposed In_0.52Al_0.48As/In_0.53Ga_0.47As epilayers were etched vertically by BCl₃/SiCl₄-based ICP at 200 °C, and heavily-doped In_0.53Ga_0.47As epilayers were regrown in the MOCVD chamber at 600 °C. After the MESA isolation and ohmic contact formation process, both upper and lower In_0.52Al_0.48As sacrificial layers were exposed through the same BCl₃/SiCl₄-based ICP process. Then, the exposed upper and bottom In_0.52Al_0.48As sacrificial layers were etched with a mixture of HCl:DI, releasing the In_0.53Ga_0.47As nanosheet. Finally, the device fabrication was completed with the deposition of a bi-layer dielectric stack of Al₂O₃/HfO_x that was 1/4 nm and a 30-nm thick TiN metal gate by ALD, in a cross-coupled manner. Figure 3 shows the cross-sectional and top-down TEM/SEM images for the fabricated GAA In_0.53Ga_0.47As NS MOSFET along the gate-width (W_g, x-direction) and S/D directions (y-direction).

3. Results and Discussion

Figure 4 exhibits two types of transmission line method (TLM) test structures: one TLM structure was used to evaluate the sheet resistance of the regrown n+ InGaAs layer (R_{RG_sh}) and the contact resistance (R_c) between the non-alloyed ohmic of a Ti/Mo/Ti/Pt/Au metal stack and the regrown n+ In_0.53Ga_0.47As layer (Figure 4a), and the other TLM structure was used to evaluate the actual source resistance (R_s) for the fabricated GAA In_0.53Ga_0.47As NS MOSFET (Figure 4b) with a dimension of L_GS = 0.5 μm. The TLM structure shown in Figure 4b was effective in characterizing the regrown contact resistance of R_c-NS. Here, R_c-NS stands for a contact resistance between the regrown n+ In_0.53Ga_0.47As layer and the In_0.53Ga_0.47As NS along the 011 direction. Figure 4c plots the measured total resistance of both structures for various temperatures. Here, half of the y-intercept in the TLM structure shown in Figure 4b corresponds to the sum of R_c, R_acc and R_c-NS. Note that both R_c and R_{RG_sh} were obtained from the TLM structure shown in Figure 4a, whereas R_acc was calculated by using a formula of R_acc = R_{RG_sh} × L_GS. Figure 4d shows the extracted R_acc and R_c-NS as a function of temperature, where both R_c and R_c-NS are independent of temperature. As in [16], R_c-NS is given by as follows:

$$R_{c-NS}\cong \frac{1}{2}\frac{h}{q^2}\frac{1}{\sqrt{n_{2-DEG}}} \cdots$$

(1)

Note that R_c-NS is a function of only two-dimensional electron gas density (n_2-DEG) in the In_0.53Ga_0.47As NS and a measured value of R_c-NS = 45 Ω⋅μm is the same as the theoretical calculation of 45 Ω⋅μm with n_2-DEG of 3.3 × 10¹² cm⁻².

Figure 5a shows the DC output characteristics of the fabricated L_g = 50 nm GAA In_0.53Ga_0.47As NS MOSFET with W_NS = 200 nm and t_NS = 10 nm. Here, the device characteristics were normalized by the footprint of the NS channel, as is suggested in [8]. The device exhibited a small value of R_ON = 206 Ω⋅μm, and excellent pinch-off and saturation behavior. Figure 5b–d exhibit transfer/transconductance, subthreshold characteristics and subthreshold-swing (S) as a function of I_D for the same device, respectively. The device delivers a maximum transconductance (g_{m_max}) of 1.86 mS/μm and a subthreshold-swing (S) of 78 mV/dec at V_DS = 0.5 V. The ON-current (I_ON) was extracted using a criteria of V_DD = 0.5 V and I_OFF = 100 nA/μm. This is a unique figure-of-merit (FOM) that integrates short-channel effects, the parasitic resistance portion and carrier transport of the channel material. The GAA In_0.53GA_0.47As NS MOSFET that is in this work delivers I_ON as high as 0.4 mA/μm at V_DD = 0.5 V.

Figure 6a–c, respectively, benchmark g_{m_max} vs. minimum dimension, I_ON vs. L_g and g_{m_max} vs. S, in comparison to those of previously reported non-planar In_xGa_1-xAs Fin or NW MOSFETs [5,14,15,17,18,19,20,21,22,23,24,25]. Q was defined as g_{m_max}/S, which integrates carrier transport property and electrostatic integrity, as proposed is in [26]. The GAA In_0.53Ga_0.47As NS MOSFET that is in this work exhibits excellent balance of g_{m_max}, S and I_ON. In particular, the device in this work displays the highest Q value in any non-planar In_xGa_1-xAs MOSFET technology.

4. Conclusions

In this paper, we reported a fabrication and electrical characterization of a GAA In_0.53Ga_0.47As NS MOSFET. The fabricated device with L_g = 50 nm, W_NS = 200 nm and t_NS = 10 nm exhibited a fairly steep subthreshold-swing of 78 mV/decade, g_{m_max} of 1.86 mS/μm, I_ON = 0.4 mA/μm and Q = 23 at V_DS = 0.5 V. To the best of our knowledge, these metrics represent the best balance of S, g_{m_max} and I_ON among any In_xGa_1-xAs-based non-planar MOSFET technology that would be directly applicable to future MBCFETs.