Fault Diagnosis and Tolerant Control for Three-Level T-Type Inverters

Abstract

This paper proposes a fault diagnosis system for inverters based on a cerebellar model articulation controller (CMAC). First, a three-level T-type inverter was implemented and used to create a three-level T-type inverter test environment for measuring the output voltage waveforms of faulty power transistors on the main inverter circuit under different output frequencies. The measured waveforms were processed using a fast Fourier transform (FFT) algorithm to create frequency spectrum diagrams and extract the characteristic spectra of corresponding faulty switches. Then, the associations of the spectra were determined and applied as training data for the CMAC to detect the positions of the faulty power transistors. The test results demonstrated that the proposed induction motor fault diagnosis system is capable of fast algorithm, requires less data to train, and has excellent accuracy of identification, with an error margin of ±5%. The detection results were then processed using a fault-tolerant controller (FTC) to enhance the reliability of the proposed system. Finally, some simulations and experimental results were conducted and analyzed to validate the feasibility of the proposed FTC system.

1. Introduction

Compared with two-level inverters, multi-level inverters [1,2,3,4,5] demonstrate reduced voltage stress on the switches and change in output voltage (dv/dt). They are suitable for high-power applications, and their cascaded arrangement of power transistors facilitate the formation of step-shaped wavelets in the output line-to-neutral point voltage waveform, creating trapezoidal voltage waveforms (similar to sine waveforms) that reduce harmonic content. Multi-level inverters can be categorized into diode-clamped, T-type, cascaded h-bridge (CHB), and flying capacitor inverters. Among these categories, the three-level, diode-clamped inverter is a widely applied inverter that is simple and easy to control [6]. This type of inverter is equipped with a capacitor that evenly divides the voltage from the direct current (DC) side into three voltage levels (+V_dc/2, 0, and −V_dc/2). Therefore, the output voltage comprises three states and requires diodes and switches to clamp the output voltage of the inverter to the neutral-point voltage of the DC side. The three-level T-type inverter proposed by Schweizer and Kolar [7], which is an inverter that does not require diode clamping, was examined in this paper. This inverter adopts common emitter-cascaded power transistors to achieve neutral-point voltage clamping rather than the use of additional diodes by diode-clamped inverters. The three-level T-type inverter effectively enhances the reliability and reduces the cost of the system. However, factors such as extended overcurrent (high temperature) operations, component aging, and drive circuit malfunction may damage the switches and hinder normal operations. To resolve these issues, multi-level inverter designs must take into account fault detection mechanisms and fault-tolerant control (FTC) capabilities to ensure that the inverter can maintain normal operations when a fault occurs [8,9,10].

Number or waveforms were directly used to represent the fault diagnosis information produced by early measuring instruments for the motor drive system. Fault points can be detected quickly and easily using these results. However, experienced personnel must be present to interpret the diagnostic information, detect the fault type, and engage in the maintenance or replacement of relevant components. This traditional fault diagnosis method has often led to detection error and waste of time and manpower for unnecessary maintenance and replacement [11,12,13]. Therefore, developing new techniques to diagnose system faults has been a longstanding focus of research. A number of scholars in Taiwan and other countries have centered their efforts on developing new diagnostic techniques [14,15,16,17]. Extant fault detection and diagnosis methods can be characterized into three major types, specifically, model-based techniques, expert system, and artificial intelligence (AI) algorithms. Model-based techniques are effective diagnostic methods. However, assumptions and limitations are unavoidable in model-based techniques due to the difficulty of building inverter models (including snubber capacitance and balance resistors) and the parasitic nature of inverters. Expert systems are often used in large systems. They effectively adjust systems but require experts to construct the entire system, which can be extremely costly. By comparison, AI algorithms require neither models nor expert knowledge [18,19,20,21]. Rather, they rely on the initial training data of normal and abnormal conditions, making them extremely versatile. A variety of AI algorithms is available, including the fuzzy method [22,23] and the neuro-fuzzy method [24]. These methods can be used to establish a fault diagnosis system solely based on the associations between input and output. However, the accuracy of algorithms increases over time. They are also limited to diagnosing single datasets at a given time and rely on expert experience. To overcome these limitations, this paper proposes a CMAC-based fault diagnosis method that adopts fast-learning and highly responsive AI algorithms.

A three-level T-type inverter was used to test the performance of the proposed system in detecting the positions of faulty power transistors. Subsequently, an FTC was used to maintain the operation reliability of the inverter. The CMAC-based fault diagnosis system for inverters architecture is illustrated in Figure 1.

2. Fault Characteristics of Three-Level Inverters

The three-level T-type inverter circuit illustrated in Figure 2 was used to analyze the fault diagnosis system. The time command pulse width modulation (PWM) scheme of switches is generated using the comparison between the three-phase balanced sinusoidal waves (v_{sin_a}, v_{sin_b}, and v_{sin_c}) and triangular waves (v_{tri_1} and v_{tri_2}) as shown in Figure 3. In addition, the S_X1⁺ and S_X1⁻, and S_X2⁺ and S_X2⁻ must be controlled into a complementary state. Take a-phase as an example: when v_{sin_a} > v_{tri_1}, let the power transistors S_a1⁺ and S_a2⁺ be turned on and S_a1⁻ and S_a2⁻ be turned off. If v_{tri_1} > v_{sin_a} > v_{tri_2}, let the power transistors S_a2⁺ and S_a1⁻ be turned on and S_a1⁺ and S_a2⁻ be turned off. However, if v_{sin_a} < v_{tri_2}, then let the power transistors S_a1⁻ and S_a2⁻ be turned on and S_a1⁺ and S_a2⁺ be turned off. The power transistors of b-phase and c-phase can be controlled with the same control strategy. Generally, inverter faults can largely be categorized into three types, namely, short-circuit fault, open-circuit fault, and trigger signal mistransmission. Short-circuit faults occur when an excessive electrical voltage travels through a switch without resistance. Open-circuit faults occur when power transistors fail to transmit trigger signals to the appropriate channels. Trigger signal mistransmission occurred when switches received erroneous trigger commands.

A practical three-level T-type inverter was implemented and used to create a test environment. A switch fault at a random point in time was tested. Measured outcomes indicated that the waveforms produced by the inverter achieved three-phase balance during normal operation. When the inverter operated at a working frequency of 60 Hz without faulty power transistors, the inverter produced output waveforms and frequency spectra similar to those illustrated in Figure 4 and Figure 5. Figure 4 shows that the size and shape of the various phase voltage waveforms were similar with a mutual phase difference of 120°. These are typical three-phase balance characteristics. When a fault occurs in any of the switches in the inverter, the characteristics in Figure 4 would change. For example, when a fault occurred in switch S_a1⁺, the waveform of the a-phase output voltage (v_ao) distorted (Figure 6). Figure 7 illustrates the waveform of the b-phase voltage (v_bo) when a fault occurred in switch S_b2⁻. The figure clearly shows a significant difference between the waveform of the voltage (v_bo) during normal and faulty conditions. Figure 8 illustrates the waveform of the c-phase voltage (v_co) when a fault occurred in switch S_c1⁺. The figure clearly shows waveform distortion in the output phase voltage of the c arm (v_co). The waveform of the a-phase output voltage (v_ao) of the inverter with a fault in switch S_a1⁺ shown in Figure 6 is same as the waveform of the c-phase output voltage (v_co) of the inverter with a fault in switch S_c1⁺ shown in Figure 8, but the phase difference is 120°.

The preceding analysis confirmed the presence of abnormalities in the voltage frequency spectra of the inverter during the occurrence of a fault. Figure 9 illustrates the frequency spectra of the various phase voltages when a fault occurs in switch S_c1⁺ at a working frequency of 60 Hz. A comparison between the frequency spectra of Figure 9 and those of the inverter during normal operation (Figure 5) revealed increased variance at (m_f − 1)th and (m_f + 1)th order of the frequency spectra for phase voltage v_co. Therefore, the spectral values at a working frequency of 60 Hz were adopted as the characteristic spectra for faults. Subsequently, $m_f$ was defined as the frequency modulation index. The index can be expressed as follows:

$$m_f\stackrel{\Delta }{=}\frac{f_{carrier}}{f_{reference}}=\frac{f_{tri}}{f_{sin}}$$

(1)

where, f_tri represents the frequency of the triangular carrier wave (or the switching frequency of the inverter), and f_sin represents the frequency of the sine wave (or the working frequency of the inverter). Parameter data concerning power transistor faults can be retrieved from the measured and analysis results. A CMAC was used to create a fault diagnosis system for inverters to detect faults in the main three-level T-type inverter circuit during switching.

3. The Cerebellar Model Articulation Controller

The CMAC was introduced by J. S. Albus in 1970 [25]. The CMAC model mimics the cerebellar neural structure of a human to achieve rapid learning and response characteristics. The CMAC framework is illustrated in Figure 10. The input signals undergo quantization, binary coding, and excitation address coding in the CMAC. The excitation addresses are then summed to generate an output value. The size of the value is analyzed to determine the type of switch fault. Training samples only excite or train their corresponding memory units. For example, the ith (i = 1–6) training sample only excites, trains, or tunes the ith layer. Therefore, overall training time is drastically reduced [26].

3.1. Quantization

A number of equal quantization levels were categorized between the highest and lowest values of the input signals. Quantization levels with higher resolutions are able to produce more detailed quantization codes but demand more free memory. In this paper, the input signals were divided into 255 levels. Levels higher than the maximum value were allocated a quantization value of 255. Levels lower than the minimum value were allocated a value of 0. A corresponding quantization value was allocated to the quantization levels between the maximum and minimum values.

3.2. Excitation Address Coding and CMAC Output Calculation

According to the corresponding quantization levels of the input signals, the values were converted into binary codes. The coded values were then combined and re-coded. Finally, the clusters were provided with a cluster code and an excitation address. For example, the input signals are the voltages at (m_f − 1)th and (m_f + 1)th orders in the three-phase frequency spectrum. Nine difference values are present between the two voltages. Assuming that the levels after quantization were 209, 200, 10, 5, 3, 10, 5, 6, and 5, they are first converted into binary codes (11010001b, 11001000b, 00001010b, 00000101b, 00000011b, 00001010b, 00000101b, 00000110b, and 00000101b) and then combined and re-coded (110100011100100000001010000001010000001100001010000001010000011000000101b) to obtain a 72-bit code. If the code is clustered every three bits, a total of 24 clusters would be obtained. The excitation addresses for the 24 clusters from the least significant bit (LSB) to the most significant bit (MSB) are $n_1$ = 101b = 5, $n_2$ = 000b = 0, $n_3$ = 000b = 0, $n_4$ = 011b = 3, $n_5$ = 000b = 0, $n_6$ = 010b = 2, $n_7$ = 001b = 1, $n_8$ = 000b = 0, $n_9$ = 010b = 2, $n_{10}$ = 001b = 1, $n_{11}$ = 100b = 4, $n_{12}$ = 001b = 1, $n_{13}$ = 000b = 0, $n_{14}$ = 010b = 2, $n_{15}$ = 001b = 1, $n_{16}$ = 000b = 0, $n_{17}$ = 010b = 2, $n_{18}$ = 001b = 1, $n_{19}$ = 000b = 0, $n_{20}$ = 100b = 4, $n_{21}$ = 100b = 4, $n_{22}$ = 011b = 3, $n_{23}$ = 100b = 4, and $n_{24}$ = 110b = 6. Assuming that the initial weighting of the memory units was 0, then the sum of $w_{\mathsf{1}}^{\mathsf{5}}$, $w_{\mathsf{2}}^{\mathsf{0}}$, $w_{\mathsf{3}}^{\mathsf{0}}$, $w_{\mathsf{4}}^{\mathsf{3}}$, $w_{\mathsf{5}}^{\mathsf{0}}$, $w_{\mathsf{6}}^{\mathsf{2}}$, $w_{\mathsf{7}}^{\mathsf{1}}$, $w_{\mathsf{8}}^{\mathsf{0}}$, $w_{\mathsf{9}}^{\mathsf{2}}$, $w_{\mathsf{10}}^{\mathsf{1}}$, $w_{\mathsf{11}}^{\mathsf{4}}$, $w_{\mathsf{12}}^{\mathsf{1}}$, $w_{\mathsf{13}}^{\mathsf{0}}$, $w_{\mathsf{14}}^{\mathsf{2}}$, $w_{\mathsf{15}}^{\mathsf{1}}$, $w_{\mathsf{16}}^{\mathsf{0}}$, $w_{\mathsf{17}}^{\mathsf{2}}$, $w_{\mathsf{18}}^{\mathsf{1}}$, $w_{\mathsf{19}}^{\mathsf{0}}$, $w_{\mathsf{20}}^{\mathsf{4}}$, $w_{\mathsf{21}}^{\mathsf{4}}$, $w_{\mathsf{22}}^{\mathsf{3}}$, $w_{\mathsf{23}}^{\mathsf{4}}$, and $w_{\mathsf{24}}^{\mathsf{6}}$ would be 0. Hence, the CMAC output can be expressed as follows:

$$y={\displaystyle \sum _{i=1}^{N^{*}}{w}_i^{n_i}}$$

(2)

where $y$ is the actual output value, $N^{*}$ is the number of excitation addresses, $w_i^{n_i}$ is the weight of the excitation memory, and $n_i$ is the address of the excited memory.

3.3. Memory Weight Tuning

The output target for the CMAC was set as 1.0 in this paper. A supervised learning approach can be used for clear output targets. Subsequently, the steepest descent method was adopted to tune the various weights [27], which can be expressed as follows:

$$w_{i(new)}^{n_i}=w_{i(old)}^{n_i}+\beta \frac{y_d-y}{N^{*}} i=\mathsf{1}, \mathsf{2} ,\dots , N^{*}$$

(3)

where $w_{i(new)}^{n_i}$ is the new weight after tuning the excitation memory, $w_{i(old)}^{n_i}$ is the old weight before tuning the excitation memory, $\beta$ is the learning gain ($\mathsf{0}<\beta \le \mathsf{1}$), and $y_d$ is the target value.

3.4. Fault Tolerance

The proposed fault diagnosis method demonstrates excellent interference resistance. Using the 72-bit code characterized in Section 3.2, the original code was changed to 110100011100100000001010000001010000001100001010000001010000011001000101b. After coding the excitation addresses ($n_1$, $n_2$, $n_3$, $n_4$, $n_5$, $n_6$, $n_7$, $n_8$, $n_9$, $n_{10}$, $n_{11}$, $n_{12}$, $n_{13}$, $n_{14}$, $n_{15}$, $n_{16}$, $n_{17}$, $n_{18}$, $n_{19}$, $n_{20}$, $n_{21}$, $n_{22}$, $n_{23}$, and $n_{24}$) changed from 5, 0, 0, 3, 0, 2, 1, 0, 2, 1, 4, 1, 0, 2, 1, 0, 2, 1, 0, 4, 4, 3, 4, and 6 to 5, 0, 1, 3, 0, 2, 1, 0, 2, 1, 4, 1, 0, 2, 1, 0, 2, 1, 0, 4, 4, 3, 4, and 6. A fault occurred only $n_3$. All other excitation addresses achieved a normal output, suggesting that the method demonstrated excellent fault tolerance. By expanding the number of clusters, the address can be dispersed and stored in more locations, reducing the effects of fault detection in the neighboring bit on output and enhancing accuracy.

3.5. CMAC Training

The training process for the CMAC-based fault diagnosis system for inverters is illustrated in Figure 11. The input training samples first underwent quantization, combined coding, cluster coding, and memory address excitation. The weights of the excitation addresses were then summed to produce an output. Equation (3) was used to tune the memory weights. Once all the samples were trained, the sample weights were analyzed to determine whether the target value was achieved. The training program can be terminated once the target value is achieved. Otherwise, the training program can be terminated once the predetermined number of training sessions has been reached.

4. CMAC-Based Fault Diagnosis for Inverters

Extended overcurrent (high-temperature) operations or component aging can cause faults in inverters. The three-level T-type inverter structure illustrated in Figure 2 was used to test switch faults. The proposed CMAC-based system was then employed to detect the positions of faulty power transistors.

First, the measured waveforms of the three-phase voltage in the inverter were processed using a fast Fourier transform algorithm to obtain the voltage spectra at (m_f − 1)th and (m_f + 1)th orders and the difference between them. These values served as the input signals of the CMAC. Switches S_a1⁺, S_a2⁻, S_b1⁺, S_b2⁻, S_c1⁺, and S_c2⁻ served as the different fault types. Moreover, 648 sets of data were collected concerning the faults of the six switches in the inverter at a working frequency between 20 and 90 Hz. The datasets were divided into 432 training data sets and 216 test datasets. The training data sets were processed using the CMAC training model characterized in Section 3.5 to obtain the weights of the different faulty switches. The parameter settings for the CMAC training program are as follows: (1) quantization levels: 255 levels; (2) bits per cluster: 3 bits; (3) cluster quantity: 24 clusters; (4) learning constants ($\beta$): 1 constant; and (5) training sessions: 25 times.

Fault detection and diagnosis can commence once the CMAC has been trained. The diagnosis procedures are as follows:

• Step 1. Access the weights of the trained CMAC.
• Step 2. Access the test data samples.
• Step 3. Proceed in the quantization, combined coding, clustering, and excitation address coding of the data.
• Step 4. Sum the weights of the excitation addresses to produce an output.
• Step 5. Determine the weight of the output (weight value closer to 1 denotes an increased likeliness of fault).
• Step 6. Generate fault diagnostic results.

5. Test Results

To detect faulty power transistors, the fault categories were divided into the fault of six switches, specifically, S_a1⁺, S_a2⁻, S_b1⁺, S_b2⁻, S_c1⁺, and S_c2⁻ (

Table 1. Fault categories.

Fault Conditions	Category
Fault occurs in Sa1+	F1
Fault occurs in Sa2−	F2
Fault occurs in Sb1+	F3
Fault occurs in Sb2−	F4
Fault occurs in Sc1+	F5
Fault occurs in Sc2−	F6

).

The characteristic spectral data of the various phase voltages of the inverter operating at 52 Hz, 85 Hz, and 120 Hz with a fault in each of the switches are tabulated in

Table 2. Characteristic spectral data of the inverter at 52 Hz with different fault categories.

Fault Category	a-Phase Characteristic Spectra			b-Phase Characteristic Spectra			c-Phase Characteristic Spectra
	mf − 1	mf + 1	Difference	mf − 1	mf + 1	Difference	mf − 1	mf + 1	Difference
F1	119.613	121.643	2.030	5.313	4.388	0.925	4.758	5.824	1.066
F2	114.776	124.832	10.056	5.321	5.855	0.534	5.230	5.144	0.086
F3	5.747	5.700	0.047	120.198	120.783	0.585	5.726	6.377	0.651
F4	5.991	5.839	0.152	116.877	124.288	7.411	4.527	4.709	0.182
F5	5.067	5.678	0.611	5.630	4.802	0.828	114.667	125.159	10.492
F6	6.368	6.210	0.158	4.728	5.491	0.763	122.676	119.228	3.448

,

Table 3. Characteristic spectral data of the inverter at 85 Hz with different fault categories.

Fault Category	a-Phase Characteristic Spectra			b-Phase Characteristic Spectra			c-Phase Characteristic Spectra
	mf − 1	mf + 1	Difference	mf − 1	mf + 1	Difference	mf − 1	mf + 1	Difference
F1	103.875	104.962	1.087	3.451	2.456	0.995	3.154	3.693	0.539
F2	100.778	106.730	5.952	3.270	3.914	0.644	3.110	2.930	0.180
F3	3.270	3.141	0.129	103.991	104.641	0.650	3.971	3.995	0.024
F4	4.109	4.218	0.109	102.684	106.825	4.141	2.568	2.519	0.049
F5	2.722	3.698	0.976	3.619	2.994	0.625	100.973	107.094	6.121
F6	3.976	3.638	0.338	2.600	3.613	1.013	105.701	103.733	1.968

and

Table 4. Characteristic spectral data of the inverter at 120 Hz with different fault categories.

Fault Category	a-Phase Characteristic Spectra			b-Phase Characteristic Spectra			c-Phase Characteristic Spectra
	mf − 1	mf + 1	Difference	mf − 1	mf + 1	Difference	mf − 1	mf + 1	Difference
F1	90.164	91.107	0.944	2.995	2.132	0.863	2.738	3.206	0.468
F2	87.475	92.642	5.166	2.838	3.397	0.559	2.699	2.543	0.156
F3	2.838	2.726	0.112	90.264	90.828	0.564	3.447	3.468	0.021
F4	3.567	3.661	0.095	89.130	92.724	3.594	2.229	2.186	0.043
F5	2.363	3.210	0.847	3.141	2.599	0.542	87.645	92.958	5.313
F6	3.451	3.158	0.293	2.257	3.136	0.879	91.748	90.040	1.708

, respectively. The test data in Table 2, Table 3 and Table 4 were incorporated into the proposed fault diagnosis system.

The detection outcomes are tabulated in

Table 5. Detection outcomes of the inverter at 52 Hz with different fault categories.

Fault Category	Output Weight						Detection Outcome
	F1	F2	F3	F4	F5	F6
F1	0.7066	0.5039	0.2158	0.1147	0.5605	0.4640	F1
F2	0.5594	0.6999	0.1957	0.1363	0.4814	0.4542	F2
F3	0.2930	0.2163	0.7419	0.6132	0.5812	0.5308	F3
F4	0.2375	0.1476	0.5404	0.6918	0.4793	0.5279	F4
F5	0.5462	0.4348	0.5371	0.4375	0.8931	0.7285	F5
F6	0.4886	0.4583	0.5007	0.4262	0.7563	0.8933	F6

,

Table 6. Detection outcomes of the inverter at 85 Hz with different fault categories.

Fault Category	Output Weight						Detection Outcome
	F1	F2	F3	F4	F5	F6
F1	0.7440	0.5517	0.2297	0.2480	0.5754	0.4923	F1
F2	0.5552	0.6683	0.2333	0.1660	0.5146	0.5312	F2
F3	0.2803	0.2050	0.7136	0.4682	0.5912	0.5467	F3
F4	0.2019	0.1526	0.5619	0.5859	0.5076	0.4151	F4
F5	0.4780	0.4384	0.4806	0.4135	0.8566	0.6552	F5
F6	0.4745	0.4783	0.4386	0.3918	0.7345	0.8697	F6

and

Table 7. Detection outcomes of the inverter at 120 Hz with different fault categories.

Fault Category	Output Weight						Detection Outcome
	F1	F2	F3	F4	F5	F6
F1	0.7291	0.5406	0.2251	0.2431	0.5639	0.4825	F1
F2	0.5441	0.6549	0.2286	0.1627	0.5043	0.5206	F2
F3	0.2433	0.2009	0.6993	0.4588	0.5794	0.5358	F3
F4	0.1979	0.1495	0.5507	0.5742	0.4974	0.4068	F4
F5	0.4684	0.4296	0.4710	0.4052	0.8395	0.6421	F5
F6	0.4651	0.4687	0.4298	0.3839	0.7198	0.8523	F6

. The tables show that the system accurately detected the fault data. For example, the detection outcomes in Table 5 generated an output weight of 0.6999 for the test data of F₂ faults in Table 2, which was the highest of all the fault data points, suggesting that the fault was category F₂. To validate the interference resistance of the proposed system, the samples for three working frequencies were tested with an error margin of $\pm 5\%$. The detection outcomes are tabulated in

Table 8. Detection outcomes of the inverter at 52 Hz with a $\pm 5\%$ error margin.

Fault Category	Error Rate	Output Weight						Detection Outcome
		F1	F2	F3	F4	F5	F6
F1	+5%	0.6706	0.5592	0.2090	0.1431	0.5708	0.5251	F1
	−5%	0.6457	0.4993	0.2439	0.1454	0.5136	0.4768
F2	+5%	0.4525	0.7206	0.1111	0.1148	0.4693	0.3698	F2
	−5%	0.4726	0.6165	0.1711	0.1386	0.4906	0.4526
F3	+5%	0.2310	0.2145	0.6713	0.5192	0.5900	0.5044	F3
	−5%	0.3332	0.2504	0.6910	0.5634	0.5757	0.5640
F4	+5%	0.2518	0.0922	0.5670	0.6080	0.4840	0.4681	F4
	−5%	0.2470	0.1257	0.5595	0.7397	0.5096	0.5351
F5	+5%	0.4445	0.4228	0.5517	0.4030	0.9062	0.7037	F5
	−5%	0.5444	0.4758	0.4715	0.4586	0.8274	0.7609
F6	+5%	0.5538	0.4585	0.4769	0.4255	0.7682	0.8771	F6
	−5%	0.4258	0.4217	0.4987	0.4038	0.7699	0.8961

,

Table 9. Detection outcomes of the inverter at 85 Hz with a $\pm 5\%$ error margin.

Fault Category	Error Rate	Output Weight						Detection Outcome
		F1	F2	F3	F4	F5	F6
F1	+5%	0.7012	0.4889	0.2386	0.2282	0.5687	0.5251	F1
	−5%	0.6974	0.5512	0.2385	0.1924	0.5192	0.5309
F2	+5%	0.5301	0.6586	0.1823	0.1373	0.5600	0.4343	F2
	−5%	0.5175	0.6687	0.1922	0.1605	0.5172	0.4643
F3	+5%	0.2800	0.2232	0.6873	0.5318	0.5848	0.5731	F3
	−5%	0.2104	0.1871	0.7173	0.4320	0.6328	0.4432
F4	+5%	0.2057	0.1313	0.4782	0.5397	0.4936	0.4091	F4
	−5%	0.1315	0.1625	0.5224	0.5717	0.5107	0.3889
F5	+5%	0.4780	0.4384	0.4806	0.4135	0.8566	0.6552	F5
	−5%	0.5003	0.4220	0.4237	0.3800	0.7992	0.6669
F6	+5%	0.4479	0.4731	0.4328	0.4021	0.7341	0.8639	F6
	−5%	0.5313	0.4555	0.4687	0.4098	0.6987	0.9409

and

Table 10. Detection outcomes of the inverter at 120 Hz with a $\pm 5\%$ error margin.

Fault Category	Error Rate	Output Weight						Detection Outcome
		F1	F2	F3	F4	F5	F6
F1	+5%	0.6872	0.4791	0.2338	0.2236	0.5573	0.5146	F1
	−5%	0.6835	0.5402	0.2337	0.1886	0.5088	0.5203
F2	+5%	0.5195	0.6454	0.1787	0.1346	0.5488	0.4256	F2
	−5%	0.5072	0.6553	0.1884	0.1573	0.5069	0.4550
F3	+5%	0.2744	0.2187	0.6736	0.5212	0.5731	0.5616	F3
	−5%	0.2062	0.1834	0.7030	0.4234	0.6201	0.4343
F4	+5%	0.2016	0.1287	0.4686	0.5289	0.4837	0.4009	F4
	−5%	0.1289	0.1593	0.5120	0.5603	0.5005	0.3811
F5	+5%	0.4684	0.4296	0.4710	0.4052	0.8395	0.6421	F5
	−5%	0.4903	0.4136	0.4152	0.3724	0.7832	0.6536
F6	+5%	0.4389	0.4636	0.4241	0.3941	0.7194	0.8466	F6
	−5%	0.5207	0.4464	0.4593	0.4016	0.6847	0.9221

. The outcomes show that the proposed system can accurately detect fault categories with or without the presence of error.

In the half-bridge and full-bridge circuits, where two transistors are connected in series in one converter leg, it is important to provide a blanking time so that the turn-on control input to one transistor is delayed with respect to turn-off control input of the other transistor in the inverter leg. This blanking time should be chosen conservatively to be greater than the worst-case maximum storage time of the transistors being used to avoid cross condition. Under normal operation, such a conservatively chosen blanking time ensures that both the transistors in the inverter leg are off. This dead time introduces an unwanted nonlinearity in the converter transfer characteristic. This dead time can be minimized by the use of design enhancements to drive circuits, which minimize turn-on and turn-off delay time in power semiconductor devices being used as the power switches. There are usually only a few us for a power device IGBT. Therefore, its influence on fault diagnosis can be ignored.

6. Fault Tolerance of Three-Level T-Type Inverter

Figure 2 presents the structural diagram of the three-level T-type inverter, revealing that the occurrence of an open-circuit fault in any of the inverter switches (S_a1⁺, S_a2⁻, S_b1⁺, S_b2⁻, S_c1⁺, and S_c2⁻) would cause an abnormal output voltage in the phase and thus result in a three-phase imbalance. The imbalance would change the voltage level of the dc bus, engendering a voltage imbalance in the upper and lower capacitors. This situation would further induce repeated three-phase imbalances in the output voltage. Therefore, to maintain inverter operation in the event of switch failure, the switching state of the inverter and the phase angle of the reference voltage must be adjusted simultaneously to maintain the three-phase balance in the output voltage.

6.1. Fault-Tolerant Control Analysis

Figure 12 shows the phasor diagram of a balanced three-phase voltage of a switch without fault. When the switch S_a1⁺ or S_a2⁻ incurs an open-circuit fault, the a-phase h-bridge switches (S_a1⁺ and S_a2⁻) must be deactivated to activate the neutral-point switches (S_a1⁻ and S_a2⁺); specifically, point a is connected to the neutral point, and b and c-phases are still switched normally. The FTC for the occurrence of an open-circuit fault in S_a1⁺ is shown in Figure 13. The voltage phasor diagram corresponding to this situation is illustrated in Figure 14a. As illustrated in this figure, the phasor positions of the line voltages Vab and Vca in Figure 12 become those of Vab1 and Vca1, with the voltage magnitude decreasing by 0.577 times relative to the original line voltage. The line voltage Vbc1 remains unchanged. However, because the voltage v_ao is 0, the phase angle of the b-phase voltage should be simultaneously adjusted to be 150° behind that of the a-phase voltage, and the phase angle of the c-phase voltage should be 150° ahead of that of the a-phase voltage. After the occurrence of a fault, the three-phase voltage can still maintain the operation of the balanced three-phase system; the corresponding voltage phasor diagram of the system is shown in Figure 14b. The phasor positions of the line voltages Vab1 and Vca1 presented in Figure 14a shift to those of Vab2 and Vca2, with the magnitude of the line voltage Vbc2 decreasing by 0.577 times relative to that of the original line voltage Vbc1. If an open-circuit fault occurs in the switch S_b1⁺ or S_b2⁻, the b-phase h-bridge switches (S_b1⁺ and S_b2⁻) are deactivated, and the neutral-point switches (S_b1⁻ and S_b2⁺) are activated; specifically, point b is connected to the neutral point, and the a- and c-phase switches continue to operate normally. The FTC for the occurrence of an open-circuit fault in S_b2⁻ is shown in Figure 15. The voltage phasor diagram corresponding to this situation is shown in Figure 16a. The phasor positions of the line voltages Vab and Vbc in Figure 12 shift to those of Vab1 and Vbc1, with the voltage magnitude decreasing by 0.577 times relative to the magnitude of the original line voltage; by contrast, the magnitude of the line voltage Vca1 remains unchanged. However, because the voltage v_bo is 0, the phase angle of the a-phase voltage should be simultaneously adjusted such that it is 30° ahead of that of the a-phase voltage, and the phase angle of the c-phase voltage should be 90° ahead of that of the a-phase voltage. Figure 16b presents the voltage phasor diagram derived after these adjustments. The phasor positions of the line voltages Vab1 and Vbc1 presented in Figure 16a shift to those of Vab2 and Vbc2, with the magnitude of the line voltage Vca2 decreasing by 0.577 times relative to that of the original line voltage Vca1. Similarly, if an open-circuit fault occurs in the switch S_c1⁺ or S_c2⁻, the c-phase h-bridge switches (S_c1⁺ and S_c2⁻) are deactivated, and the neutral-point switches (S_c1⁻ and S_c2⁺) are activated. Point c is connected to the neutral point, and the a- and b-phase switches continue to operate normally. The FTC for the occurrence of an open-circuit fault in S_c1⁺ is shown in Figure 17. Figure 18a shows the voltage phasor diagram corresponding to this situation. The phasor positions of the line voltages Vbc and Vca shown in Figure 12 switch to those of Vbc1 and Vca1, with the voltage magnitude decreasing by 0.577 times relative to the magnitude of the original line voltage; by contrast, the magnitude of the line voltage Vab1 remains unchanged. However, because the voltage v_co is 0, the phase angle of the a-phase voltage should be simultaneously adjusted such that it is 30° behind the original a-phase voltage, and the phase angle of the b-phase voltage should be 90° behind the original a-phase voltage. Figure 18b illustrates the voltage phasor diagram derived after the adjustments. The phasor positions of the line voltages Vbc1 and Vca1 presented in Figure 18a switch to the positions of Vbc2 and Vca2, with the magnitude of Vab2 decreasing by 0.577 times relative to that of the original line voltage Vab1.

6.2. FTC Simulation Results

The FTC operations for the occurrence of an open-circuit fault in S_a1⁺, S_b2⁻, and S_c1⁺ were simulated. The simulation results are illustrated in Figure 19, Figure 20 and Figure 21. Distortion was exhibited in the three-phase output line voltage 0.06 s following the occurrence of an open-circuit fault, particularly in the faulty phase. The FTC was activated at 0.12 s. The figures show that once the FTC was activated, the five-level three-phase output line voltage was reduced to three levels and the output line voltage maintained three-phase balance after the occurrence of a fault.

6.3. FTC Experimental Results

To verify the simulation results, this study uses the digital signal processor TMS320F28335 as the control core and considers the occurrence of open-circuit faults in the switches S_a1⁺, S_b2⁻, and S_c1⁺ to test the fault-tolerant control strategy. Regarding the parameter setting of the motor drive, a 300-Vdc inverter with a switching frequency of 21 kHz is connected to an induction motor. The parameters of the induction motor are listed in

Table 11. Parameters of the three-phase induction motor.

Horsepower (Hp)	Rotor Resistance (Ω)	Rotor Leakage Inductance (H)	Stator Resistance (Ω)	Stator Leakage Inductance (H)	Magnetization Inductance (H)	Moment of Inertia (kg-m2)
1	10.4	0.04	11.6	0.04	0.557	0.004

.

Figure 22 shows that the occurrence of an open-circuit fault in the switch S_a1⁺ would distort the three-phase output line voltage. The fault is particularly severe in the v_ab and v_ca phases, and the fault-tolerant control strategy can be launched 0.03 s after the occurrence of the fault. In this situation, the a-phase h-bridge switches (S_a1⁺ and S_a2⁻) are deactivated, and the neutral-point switches (S_a1⁻ and S_a2⁺) are thus activated. The b and c-phase switches still operate normally; the phase angle of the b-phase voltage is simultaneously adjusted such that it is 150° behind the phase angle of the a-phase reference voltage, and the phase angle of the c-phase reference voltage is adjusted such that it is 150° ahead of that of the a-phase voltage. After the execution of the fault-tolerant control strategy, the three-phase output line voltage is reduced from five to three levels (Figure 22). However, after the occurrence of the fault, the output line voltage still maintains the operation of the balanced three-phase system. Therefore, the motor can still operate normally under reduced load.

If an open-circuit fault occurs in the switch S_b2⁻, the fault would distort the three-phase output line voltage, as illustrated in Figure 23. The fault is particularly severe in the v_ab and v_bc phases. In this situation, if the fault-tolerant control strategy is launched, the b-phase h-bridge switches (S_b1⁺ and S_b2⁻) are deactivated and the neutral-point switches (S_b1⁻ and S_b2⁺) are thus activated; the a- and c-phase switches still operate normally. However, the phase angle of the new a-phase reference voltage is adjusted such that it is 30° ahead of that of the original a-phase reference voltage, and the phase angle of the c-phase reference voltage is adjusted such that it is 90° ahead of that of the original a-phase voltage. Figure 23 indicates that after the execution of the fault-tolerant control strategy, the three-phase output line voltage is reduced from five to three levels; however, after the occurrence of the fault, the output line voltage can maintain the operation of the balanced three-phase system. Therefore, the motor can continue to operate appropriately under reduced load.

If an open-circuit fault occurs in the switch S_c1⁺, the fault would distort the three-phase output line voltage, as presented in Figure 24. The fault is particularly severe in the v_bc and v_ca phases. If the fault-tolerant control is launched 0.03 s after the occurrence of the fault, the c-phase h-bridge switches (S_c1⁺ and S_c2⁻) are deactivated and the neutral-point switches (S_c1⁻ and S_c2⁺) are activated; the a- and b-phase switches still operate normally. The phase angle of the a-phase reference voltage is adjusted such that it is 30° behind that of the original a-phase reference voltage, and the phase angle of the b-phase reference voltage is adjusted such that it is 90° behind that of the original a-phase reference voltage. Figure 24 reveals that after the execution of the fault-tolerant control strategy, the three-phase output line voltage is also reduced from five to three levels. However, after the occurrence of the fault, the output line voltage can maintain the operation of the balanced three-phase system. Therefore, the motor can continue to operate appropriately under reduced load.

If the capacitor at the DC link is not large enough, and the switching of FTC is not fast enough, the voltage of DC link will vary. In this paper, because the capacitor used in the DC link is quite large, and the switching time of FTC switch is very short, there is almost no voltage variation in the DC link before fault and after clearing the fault.

7. Conclusions

This paper proposed a CMAC-based fault diagnosis system for inverters capable of detecting the positions of faulty power transistors in three-level T-type inverters. The application of a CMAC reduces training time. It also possesses capabilities to reduce the effects of interference signals. The FTC strategy enabled the system to engage in FTC immediately following the occurrence of a fault to maintain the normal supply power of the inverter, thereby greatly enhancing the power reliability of three-level T-type inverters. Finally, the experimental results verify that the proposed system can accurately detect fault categories, even with the presence of interference. Moreover, the FTC strategy enables the system to maintain the three-phase balance of the output line voltage upon the occurrence of a switch fault, confirming the feasibility of the proposed system.