Fault Diagnosis and Tolerant Control for Three-Level T-Type Inverters

: This paper proposes a fault diagnosis system for inverters based on a cerebellar model articulation controller (CMAC). First, a three-level T-type inverter was implemented and used to create a three-level T-type inverter test environment for measuring the output voltage waveforms of faulty power transistors on the main inverter circuit under different output frequencies. The measured waveforms were processed using a fast Fourier transform (FFT) algorithm to create frequency spectrum diagrams and extract the characteristic spectra of corresponding faulty switches. Then, the associations of the spectra were determined and applied as training data for the CMAC to detect the positions of the faulty power transistors. The test results demonstrated that the proposed induction motor fault diagnosis system is capable of fast algorithm, requires less data to train, and has excellent accuracy of identiﬁcation, with an error margin of ± 5%. The detection results were then processed using a fault-tolerant controller (FTC) to enhance the reliability of the proposed system. Finally, some simulations and experimental results were conducted and analyzed to validate the feasibility of the proposed FTC system.


Introduction
Compared with two-level inverters, multi-level inverters [1][2][3][4][5] demonstrate reduced voltage stress on the switches and change in output voltage (dv/dt). They are suitable for high-power applications, and their cascaded arrangement of power transistors facilitate the formation of step-shaped wavelets in the output line-to-neutral point voltage waveform, creating trapezoidal voltage waveforms (similar to sine waveforms) that reduce harmonic content. Multi-level inverters can be categorized into diode-clamped, T-type, cascaded h-bridge (CHB), and flying capacitor inverters. Among these categories, the three-level, diode-clamped inverter is a widely applied inverter that is simple and easy to control [6]. This type of inverter is equipped with a capacitor that evenly divides the voltage from the direct current (DC) side into three voltage levels (+V dc /2, 0, and −V dc /2). Therefore, the output voltage comprises three states and requires diodes and switches to clamp the output voltage of the inverter to the neutral-point voltage of the DC side. The three-level T-type inverter proposed by Schweizer and Kolar [7], which is an inverter that does not require diode clamping, was examined in this paper. This inverter adopts common emittercascaded power transistors to achieve neutral-point voltage clamping rather than the use of additional diodes by diode-clamped inverters. The three-level T-type inverter effectively enhances the reliability and reduces the cost of the system. However, factors such as extended overcurrent (high temperature) operations, component aging, and drive circuit malfunction may damage the switches and hinder normal operations. To resolve these issues, multi-level inverter designs must take into account fault detection mechanisms and fault-tolerant control (FTC) capabilities to ensure that the inverter can maintain normal operations when a fault occurs [8][9][10]. account fault detection mechanisms and fault-tolerant control (FTC) capabilities to ensure that the inverter can maintain normal operations when a fault occurs [8−10].
Number or waveforms were directly used to represent the fault diagnosis information produced by early measuring instruments for the motor drive system. Fault points can be detected quickly and easily using these results. However, experienced personnel must be present to interpret the diagnostic information, detect the fault type, and engage in the maintenance or replacement of relevant components. This traditional fault diagnosis method has often led to detection error and waste of time and manpower for unnecessary maintenance and replacement [11−13]. Therefore, developing new techniques to diagnose system faults has been a longstanding focus of research. A number of scholars in Taiwan and other countries have centered their efforts on developing new diagnostic techniques [14−17]. Extant fault detection and diagnosis methods can be characterized into three major types, specifically, model-based techniques, expert system, and artificial intelligence (AI) algorithms. Model-based techniques are effective diagnostic methods. However, assumptions and limitations are unavoidable in model-based techniques due to the difficulty of building inverter models (including snubber capacitance and balance resistors) and the parasitic nature of inverters. Expert systems are often used in large systems. They effectively adjust systems but require experts to construct the entire system, which can be extremely costly. By comparison, AI algorithms require neither models nor expert knowledge [18−21]. Rather, they rely on the initial training data of normal and abnormal conditions, making them extremely versatile. A variety of AI algorithms is available, including the fuzzy method [22,23] and the neurofuzzy method [24]. These methods can be used to establish a fault diagnosis system solely based on the associations between input and output. However, the accuracy of algorithms increases over time. They are also limited to diagnosing single datasets at a given time and rely on expert experience. To overcome these limitations, this paper proposes a CMAC-based fault diagnosis method that adopts fast-learning and highly responsive AI algorithms.
A three-level T−type inverter was used to test the performance of the proposed system in detecting the positions of faulty power transistors. Subsequently, an FTC was used to maintain the operation reliability of the inverter. The CMAC-based fault diagnosis system for inverters architecture is illustrated in Figure 1.

Fault Characteristics of Three-Level Inverters
The three-level T-type inverter circuit illustrated in Figure 2 was used to analyze the fault diagnosis system. The time command pulse width modulation (PWM) scheme of switches is generated using the comparison between the three-phase balanced sinusoidal waves (v sin_a , v sin_b , and v sin_c ) and triangular waves (v tri_1 and v tri_2 ) as shown in Figure 3. In addition, the S X1 + and S X1 − , and S X2 + and S X2 − must be controlled into a complementary state. Take a-phase as an example: when v sin_a > v tri_1 , let the power transistors S a1 + and S a2 + be turned on and S a1 − and S a2 − be turned off. If v tri_1 > v sin_a > v tri_2 , let the power transistors S a2 + and S a1 − be turned on and S a1 + and S a2 − be turned off. However, if v sin_a < v tri_2 , then let the power transistors S a1 − and S a2 − be turned on and S a1 + and S a2 + be turned off. The power transistors of b-phase and c-phase can be controlled with the same control strategy. Generally, inverter faults can largely be categorized into three types, namely, short-circuit fault, open-circuit fault, and trigger signal mistransmission. Short-circuit faults occur when an excessive electrical voltage travels through a switch without resistance. Open-circuit faults occur when power transistors fail to transmit trigger signals to the appropriate channels. Trigger signal mistransmission occurred when switches received erroneous trigger commands.

Fault Characteristics of Three-Level Inverters
The three−level T−type inverter circuit illustrated in Figure 2 was used to analyze the fault diagnosis system. The time command pulse width modulation (PWM) scheme of switches is generated using the comparison between the three-phase balanced sinusoidal waves (vsin_a, vsin_b, and vsin_c) and triangular waves (vtri_1 and vtri_2) as shown in Figure 3 Figure 2. The three−level T−type inverter architecture. A practical three-level T-type inverter was implemented and used to create a test environment. A switch fault at a random point in time was tested. Measured outcomes indicated that the waveforms produced by the inverter achieved three-phase balance during normal operation. When the inverter operated at a working frequency of 60 Hz without faulty power transistors, the inverter produced output waveforms and frequency spectra similar to those illustrated in Figures 4 and 5. Figure 4 shows that the size and shape of the various phase voltage waveforms were similar with a mutual phase difference of 120 • . These are typical three-phase balance characteristics. When a fault occurs in any of the switches in the inverter, the characteristics in Figure 4 would change. For example, when a fault occurred in switch S a1 + , the waveform of the a-phase output voltage (v ao ) distorted ( Figure 6). Figure 7 illustrates the waveform of the b-phase voltage (v bo ) when a fault occurred in switch S b2 − . The figure clearly shows a significant difference between the waveform of the voltage (v bo ) during normal and faulty conditions. Figure 8 illustrates the waveform of the c-phase voltage (v co ) when a fault occurred in switch S c1 + . The figure clearly shows waveform distortion in the output phase voltage of the c arm (v co ). The waveform of the a-phase output voltage (v ao ) of the inverter with a fault in switch S a1 + shown in Figure 6 is same as the waveform of the c-phase output voltage (v co ) of the inverter with a fault in switch S c1 + shown in Figure 8, but the phase difference is 120 • .   A practical three−level T−type inverter was implemented and used to create a test environment. A switch fault at a random point in time was tested. Measured outcomes indicated that the waveforms produced by the inverter achieved three-phase balance during normal operation. When the inverter operated at a working frequency of 60 Hz without faulty power transistors, the inverter produced output waveforms and frequency spectra similar to those illustrated in Figures 4 and 5. Figure 4 shows that the size and shape of the various phase voltage waveforms were similar with a mutual phase difference of 120°. These are typical three-phase balance characteristics. When a fault occurs in any of the switches in the inverter, the characteristics in Figure 4 would change.
For example, when a fault occurred in switch Sa1 + , the waveform of the a-phase output voltage (vao) distorted ( Figure 6). Figure 7 illustrates the waveform of the b-phase voltage (vbo) when a fault occurred in switch Sb2 -. The figure clearly shows a significant difference between the waveform of the voltage (vbo) during normal and faulty conditions. Figure 8 illustrates the waveform of the c-phase voltage (vco) when a fault occurred in switch Sc1 + .
The figure clearly shows waveform distortion in the output phase voltage of the c arm (vco). The waveform of the a-phase output voltage (vao) of the inverter with a fault in switch Sa1 + shown in Figure 6 is same as the waveform of the c-phase output voltage (vco) of the inverter with a fault in switch Sc1 + shown in Figure 8, but the phase difference is 120°. The preceding analysis confirmed the presence of abnormalities in the voltage frequency spectra of the inverter during the occurrence of a fault. Figure 9 illustrates the frequency spectra of the various phase voltages when a fault occurs in switch S c1 + at a working frequency of 60 Hz. A comparison between the frequency spectra of Figure 9 and those of the inverter during normal operation ( Figure 5) revealed increased variance at (m f − 1)th and (m f + 1)th order of the frequency spectra for phase voltage v co . Therefore, the spectral values at a working frequency of 60 Hz were adopted as the characteristic spectra for faults. Subsequently, m f was defined as the frequency modulation index. The index can be expressed as follows: where, f tri represents the frequency of the triangular carrier wave (or the switching frequency of the inverter), and f sin represents the frequency of the sine wave (or the working frequency of the inverter). Parameter data concerning power transistor faults can be retrieved from the measured and analysis results. A CMAC was used to create a fault diagnosis system for inverters to detect faults in the main three-level T-type inverter circuit during switching.           where, ftri represents the frequency of the triangular carrier wave (or the switching frequency of the inverter), and fsin represents the frequency of the sine wave (or the working frequency of the inverter). Parameter data concerning power transistor faults can be retrieved from the measured and analysis results. A CMAC was used to create a fault diagnosis system for inverters to detect faults in the main three-level T-type inverter circuit during switching.

The Cerebellar Model Articulation Controller
The CMAC was introduced by J. S. Albus in 1970 [25]. The CMAC model mimics the cerebellar neural structure of a human to achieve rapid learning and response characteristics. The CMAC framework is illustrated in Figure 10. The input signals undergo quantization, binary coding, and excitation address coding in the CMAC. The excitation addresses are then summed to generate an output value. The size of the value

The Cerebellar Model Articulation Controller
The CMAC was introduced by J. S. Albus in 1970 [25]. The CMAC model mimics the cerebellar neural structure of a human to achieve rapid learning and response characteristics. The CMAC framework is illustrated in Figure 10. The input signals undergo quantization, binary coding, and excitation address coding in the CMAC. The excitation addresses are then summed to generate an output value. The size of the value is analyzed to determine the type of switch fault. Training samples only excite or train their corresponding memory units. For example, the ith (i = 1-6) training sample only excites, trains, or tunes the ith layer. Therefore, overall training time is drastically reduced [26]. (c) Figure 9. The frequency spectra of the various phase voltages of the inverter at a working frequency of 60 Hz with a fault in switch Sc1 + : (a) phase voltage vao; (b) phase voltage vbo; (c) phase voltage vco.

The Cerebellar Model Articulation Controller
The CMAC was introduced by J. S. Albus in 1970 [25]. The CMAC model mimics the cerebellar neural structure of a human to achieve rapid learning and response characteristics. The CMAC framework is illustrated in Figure 10. The input signals undergo quantization, binary coding, and excitation address coding in the CMAC. The excitation addresses are then summed to generate an output value. The size of the value is analyzed to determine the type of switch fault. Training samples only excite or train their corresponding memory units. For example, the ith (i = 1-6) training sample only excites, trains, or tunes the ith layer. Therefore, overall training time is drastically reduced [26].

Quantization
A number of equal quantization levels were categorized between the highest and lowest values of the input signals. Quantization levels with higher resolutions are able to produce more detailed quantization codes but demand more free memory. In this paper, the input signals were divided into 255 levels. Levels higher than the maximum value were allocated a quantization value of 255. Levels lower than the minimum value were allocated a value of 0. A corresponding quantization value was allocated to the quantization levels between the maximum and minimum values.

Memory Weight Tuning
The output target for the CMAC was set as 1.0 in this paper. A supervised learning approach can be used for clear output targets. Subsequently, the steepest descent method was adopted to tune the various weights [27], which can be expressed as follows: where w n i i(new) is the new weight after tuning the excitation memory, w n i i(old) is the old weight before tuning the excitation memory, β is the learning gain (0 < β ≤ 1), and y d is the target value.

CMAC Training
The training process for the CMAC-based fault diagnosis system for inverters is illustrated in Figure 11. The input training samples first underwent quantization, combined coding, cluster coding, and memory address excitation. The weights of the excitation addresses were then summed to produce an output. Equation (3) was used to tune the memory weights. Once all the samples were trained, the sample weights were analyzed to determine whether the target value was achieved. The training program can be terminated once the target value is achieved. Otherwise, the training program can be terminated once the predetermined number of training sessions has been reached. illustrated in Figure 11. The input training samples first underwent quantization, combined coding, cluster coding, and memory address excitation. The weights of the excitation addresses were then summed to produce an output. Equation (3) was used to tune the memory weights. Once all the samples were trained, the sample weights were analyzed to determine whether the target value was achieved. The training program can be terminated once the target value is achieved. Otherwise, the training program can be terminated once the predetermined number of training sessions has been reached.  Figure 11. Training flowchart for the CMAC−based fault diagnosis system for inverters. Figure 11. Training flowchart for the CMAC-based fault diagnosis system for inverters.

CMAC-Based Fault Diagnosis for Inverters
Extended overcurrent (high-temperature) operations or component aging can cause faults in inverters. The three-level T-type inverter structure illustrated in Figure 2 was used to test switch faults. The proposed CMAC-based system was then employed to detect the positions of faulty power transistors.
First, the measured waveforms of the three-phase voltage in the inverter were processed using a fast Fourier transform algorithm to obtain the voltage spectra at (m f − 1)th and (m f + 1)th orders and the difference between them. These values served as the input signals of the CMAC. Switches S a1 + , S a2 − , S b1 + , S b2 − , S c1 + , and S c2 − served as the different fault types. Moreover, 648 sets of data were collected concerning the faults of the six switches in the inverter at a working frequency between 20 and 90 Hz. The datasets were divided into 432 training data sets and 216 test datasets. The training data sets were processed using the CMAC training model characterized in Section 3.5 to obtain the weights of the different faulty switches. The parameter settings for the CMAC training program are as follows: (1) quantization levels: 255 levels; (2) bits per cluster: 3 bits; (3) cluster quantity: 24 clusters; (4) learning constants (β): 1 constant; and (5) training sessions: 25 times.
Fault detection and diagnosis can commence once the CMAC has been trained. The diagnosis procedures are as follows: Step 1. Access the weights of the trained CMAC.
Step 2. Access the test data samples.
Step 3. Proceed in the quantization, combined coding, clustering, and excitation address coding of the data.
Step 4. Sum the weights of the excitation addresses to produce an output.
Step 5. Determine the weight of the output (weight value closer to 1 denotes an increased likeliness of fault).
Step 6. Generate fault diagnostic results.

Test Results
To detect faulty power transistors, the fault categories were divided into the fault of six switches, specifically, S a1 + , S a2 − , S b1 + , S b2 − , S c1 + , and S c2 − (Table 1). The characteristic spectral data of the various phase voltages of the inverter operating at 52 Hz, 85 Hz, and 120 Hz with a fault in each of the switches are tabulated in Tables 2-4, respectively. The test data in Tables 2-4 were incorporated into the proposed fault diagnosis system. The detection outcomes are tabulated in Tables 5-7. The tables show that the system accurately detected the fault data. For example, the detection outcomes in Table 5 generated an output weight of 0.6999 for the test data of F 2 faults in Table 2, which was the highest of all the fault data points, suggesting that the fault was category F 2 . To validate the interference resistance of the proposed system, the samples for three working frequencies were tested with an error margin of ±5%. The detection outcomes are tabulated in Tables 8-10. The outcomes show that the proposed system can accurately detect fault categories with or without the presence of error.   In the half-bridge and full-bridge circuits, where two transistors are connected in series in one converter leg, it is important to provide a blanking time so that the turn-on control input to one transistor is delayed with respect to turn-off control input of the other transistor in the inverter leg. This blanking time should be chosen conservatively to be greater than the worst-case maximum storage time of the transistors being used to avoid cross condition. Under normal operation, such a conservatively chosen blanking time ensures that both the transistors in the inverter leg are off. This dead time introduces an unwanted nonlinearity in the converter transfer characteristic. This dead time can be minimized by the use of design enhancements to drive circuits, which minimize turn-on and turn-off delay time in power semiconductor devices being used as the power switches. There are usually only a few us for a power device IGBT. Therefore, its influence on fault diagnosis can be ignored.  Figure 2 presents the structural diagram of the three-level T-type inverter, revealing that the occurrence of an open-circuit fault in any of the inverter switches (S a1 + , S a2 − , S b1 + , S b2 − , S c1 + , and S c2 − ) would cause an abnormal output voltage in the phase and thus result in a three-phase imbalance. The imbalance would change the voltage level of the dc bus, engendering a voltage imbalance in the upper and lower capacitors. This situation would further induce repeated three-phase imbalances in the output voltage. Therefore, to maintain inverter operation in the event of switch failure, the switching state of the inverter and the phase angle of the reference voltage must be adjusted simultaneously to maintain the three-phase balance in the output voltage.  Figure 15. The voltage phasor diagram corresponding to this situation is shown in Figure 16a. The phasor positions of the line voltages Vab and Vbc in Figure 12 shift to those of Vab1 and Vbc1, with the voltage magnitude decreasing by 0.577 times relative to the magnitude of the original line voltage; by contrast, the magnitude of the line voltage Vca1 remains unchanged. However, because the voltage v bo is 0, the phase angle of the a-phase voltage should be simultaneously adjusted such that it is 30 • ahead of that of the a-phase voltage, and the phase angle of the c-phase voltage should be 90 • ahead of that of the a-phase voltage. Figure 16b Figure 17. Figure 18a shows the voltage phasor diagram corresponding to this situation. The phasor positions of the line voltages Vbc and Vca shown in Figure 12 switch to those of Vbc1 and Vca1, with the voltage magnitude decreasing by 0.577 times relative to the magnitude of the original line voltage; by contrast, the magnitude of the line voltage Vab1 remains unchanged. However, because the voltage v co is 0, the phase angle of the a-phase voltage should be simultaneously adjusted such that it is 30 • behind the original a-phase voltage, and the phase angle of the b-phase voltage should be 90 • behind the original a-phase voltage. Figure 18b illustrates the voltage phasor diagram derived after the adjustments. The phasor positions of the line voltages Vbc1 and Vca1 presented in Figure 18a switch to the positions of Vbc2 and Vca2, with the magnitude of Vab2 decreasing by 0.577 times relative to that of the original line voltage Vab1.

Fault-Tolerant Control Analysis
voltage; by contrast, the magnitude of the line voltage Vab1 remains u However, because the voltage vco is 0, the phase angle of the a-phase voltage simultaneously adjusted such that it is 30° behind the original a-phase volta phase angle of the b-phase voltage should be 90° behind the original a-pha Figure 18b illustrates the voltage phasor diagram derived after the adjust phasor positions of the line voltages Vbc1 and Vca1 presented in Figure 18a sw positions of Vbc2 and Vca2, with the magnitude of Vab2 decreasing by 0.577 tim to that of the original line voltage Vab1.   voltage magnitude decreasing by 0.577 times relative to the magnitude of the origin voltage; by contrast, the magnitude of the line voltage Vab1 remains unch However, because the voltage vco is 0, the phase angle of the a-phase voltage sho simultaneously adjusted such that it is 30° behind the original a-phase voltage, a phase angle of the b-phase voltage should be 90° behind the original a-phase v Figure 18b illustrates the voltage phasor diagram derived after the adjustment phasor positions of the line voltages Vbc1 and Vca1 presented in Figure 18a switch positions of Vbc2 and Vca2, with the magnitude of Vab2 decreasing by 0.577 times r to that of the original line voltage Vab1.

FTC Simulation Results
The

FTC Simulation Results
The

FTC Experimental Results
To verify the simulation results, this study uses the digital signal processor TMS320F28335 as the control core and considers the occurrence of open−circuit faults in the switches Sa1 + , Sb2 -, and Sc1 + to test the fault-tolerant control strategy. Regarding the parameter setting of the motor drive, a 300−Vdc inverter with a switching frequency of 21 kHz is connected to an induction motor. The parameters of the induction motor are listed in Table 11. Table 11. Parameters of the three-phase induction motor.

FTC Experimental Results
To verify the simulation results, this study uses the digital signal processor TMS320F28335 as the control core and considers the occurrence of open-circuit faults in the switches S a1 + , S b2 − , and S c1 + to test the fault-tolerant control strategy. Regarding the parameter setting of the motor drive, a 300-Vdc inverter with a switching frequency of 21 kHz is connected to an induction motor. The parameters of the induction motor are listed in Table 11.  Figure 22 shows that the occurrence of an open-circuit fault in the switch S a1 + would distort the three-phase output line voltage. The fault is particularly severe in the v ab and v ca phases, and the fault-tolerant control strategy can be launched 0.03 s after the occurrence of the fault. In this situation, the a-phase h-bridge switches (S a1 + and S a2 − ) are deactivated, and the neutra-point switches (S a1 − and S a2 + ) are thus activated. The b and c-phase switches still operate normally; the phase angle of the b-phase voltage is simultaneously adjusted such that it is 150 • behind the phase angle of the a-phase reference voltage, and the phase angle of the c-phase reference voltage is adjusted such that it is 150 • ahead of that of the a-phase voltage. After the execution of the fault-tolerant control strategy, the three-phase output line voltage is reduced from five to three levels ( Figure 22). However, after the occurrence of the fault, the output line voltage still maintains the operation of the balanced three-phase system. Therefore, the motor can still operate normally under reduced load. If an open-circuit fault occurs in the switch Sb2 -, the fault would distort the threephase output line voltage, as illustrated in Figure 23. The fault is particularly severe in the vab and vbc phases. In this situation, if the fault-tolerant control strategy is launched, the bphase h-bridge switches (Sb1 + and Sb2 -) are deactivated and the neutral-point switches (Sb1and Sb2 + ) are thus activated; the a-and c-phase switches still operate normally. However, the phase angle of the new a-phase reference voltage is adjusted such that it is 30° ahead of that of the original a-phase reference voltage, and the phase angle of the c-phase reference voltage is adjusted such that it is 90° ahead of that of the original a-phase voltage. Figure 23 indicates that after the execution of the fault-tolerant control strategy, the threephase output line voltage is reduced from five to three levels; however, after the occurrence of the fault, the output line voltage can maintain the operation of the balanced three-phase system. Therefore, the motor can continue to operate appropriately under reduced load.  If an open-circuit fault occurs in the switch S b2 − , the fault would distort the three-phase output line voltage, as illustrated in Figure 23. The fault is particularly severe in the v ab and v bc phases. In this situation, if the fault-tolerant control strategy is launched, the b-phase h-bridge switches (S b1 + and S b2 − ) are deactivated and the neutral-point switches (S b1 − and S b2 + ) are thus activated; the aand c-phase switches still operate normally. However, the phase angle of the new a-phase reference voltage is adjusted such that it is 30 • ahead of that of the original a-phase reference voltage, and the phase angle of the c-phase reference voltage is adjusted such that it is 90 • ahead of that of the original a-phase voltage. Figure 23 indicates that after the execution of the fault-tolerant control strategy, the three-phase output line voltage is reduced from five to three levels; however, after the occurrence of the fault, the output line voltage can maintain the operation of the balanced three-phase system. Therefore, the motor can continue to operate appropriately under reduced load. If an open-circuit fault occurs in the switch Sb2 -, the fault would distort the threephase output line voltage, as illustrated in Figure 23. The fault is particularly severe in the vab and vbc phases. In this situation, if the fault-tolerant control strategy is launched, the bphase h-bridge switches (Sb1 + and Sb2 -) are deactivated and the neutral-point switches (Sb1and Sb2 + ) are thus activated; the a-and c-phase switches still operate normally. However, the phase angle of the new a-phase reference voltage is adjusted such that it is 30° ahead of that of the original a-phase reference voltage, and the phase angle of the c-phase reference voltage is adjusted such that it is 90° ahead of that of the original a-phase voltage. Figure 23 indicates that after the execution of the fault-tolerant control strategy, the threephase output line voltage is reduced from five to three levels; however, after the occurrence of the fault, the output line voltage can maintain the operation of the balanced three-phase system. Therefore, the motor can continue to operate appropriately under reduced load. If an open-circuit fault occurs in the switch S c1 + , the fault would distort the three-phase output line voltage, as presented in Figure 24. The fault is particularly severe in the v bc and v ca phases. If the fault-tolerant control is launched 0.03 s after the occurrence of the fault, the c-phase h-bridge switches (S c1 + and S c2 − ) are deactivated and the neutral-point switches (S c1 − and S c2 + ) are activated; the aand b-phase switches still operate normally. The phase angle of the a-phase reference voltage is adjusted such that it is 30 • behind that of the original a-phase reference voltage, and the phase angle of the b-phase reference voltage is adjusted such that it is 90 • behind that of the original a-phase reference voltage. Figure 24 reveals that after the execution of the fault-tolerant control strategy, the three-phase output line voltage is also reduced from five to three levels. However, after the occurrence of the fault, the output line voltage can maintain the operation of the balanced three-phase system. Therefore, the motor can continue to operate appropriately under reduced load. reference voltage is adjusted such that it is 90° behind that of the original a-phase reference voltage. Figure 24 reveals that after the execution of the fault-tolerant control strategy, the three-phase output line voltage is also reduced from five to three levels. However, after the occurrence of the fault, the output line voltage can maintain the operation of the balanced three-phase system. Therefore, the motor can continue to operate appropriately under reduced load. If the capacitor at the DC link is not large enough, and the switching of FTC is not fast enough, the voltage of DC link will vary. In this paper, because the capacitor used in the DC link is quite large, and the switching time of FTC switch is very short, there is almost no voltage variation in the DC link before fault and after clearing the fault.

Conclusions
This paper proposed a CMAC-based fault diagnosis system for inverters capable of detecting the positions of faulty power transistors in three-level T-type inverters. The application of a CMAC reduces training time. It also possesses capabilities to reduce the effects of interference signals. The FTC strategy enabled the system to engage in FTC immediately following the occurrence of a fault to maintain the normal supply power of the inverter, thereby greatly enhancing the power reliability of three-level T-type inverters. Finally, the experimental results verify that the proposed system can accurately detect fault categories, even with the presence of interference. Moreover, the FTC strategy enables the system to maintain the three-phase balance of the output line voltage upon the occurrence of a switch fault, confirming the feasibility of the proposed system.  If the capacitor at the DC link is not large enough, and the switching of FTC is not fast enough, the voltage of DC link will vary. In this paper, because the capacitor used in the DC link is quite large, and the switching time of FTC switch is very short, there is almost no voltage variation in the DC link before fault and after clearing the fault.

Conclusions
This paper proposed a CMAC-based fault diagnosis system for inverters capable of detecting the positions of faulty power transistors in three-level T-type inverters. The application of a CMAC reduces training time. It also possesses capabilities to reduce the effects of interference signals. The FTC strategy enabled the system to engage in FTC immediately following the occurrence of a fault to maintain the normal supply power of the inverter, thereby greatly enhancing the power reliability of three-level T-type inverters. Finally, the experimental results verify that the proposed system can accurately detect fault categories, even with the presence of interference. Moreover, the FTC strategy enables the system to maintain the three-phase balance of the output line voltage upon the occurrence of a switch fault, confirming the feasibility of the proposed system.