A 0.0012 mm2 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS
Round 1
Reviewer 1 Report
This paper presents an calibration-free pseudo-loop-unrolled SAR ADC. It is a topic of interest to the researchers in the related areas, but the paper needs some improvement before acceptance for publication. My detailed comments are as follows:
- In equation 1 and 2, the cycle time of the LU SAR ADC and the proposed P-LU SAR ADC is compared. However, it is not clear what the advantage of the P-LU SAR ADC over LU SAR ADC. Can you describe this in more detail?
- Since only one C-DAC is used in your ADC, how do you assess the impact of the comparator’s kick back noise? Will it affect the comparator output?
- In page 8 line 233, is “tLatch’” a typo? If not, please explain the difference between tLatch’ and tLatch.
- In many designs of SAR ADC, 0.5VDD is used in the switching of C-DAC, which can decrease the size of C-DAC and the DAC settling time. Can you explain if it is possible to use in this P-LU SAR ADC?
Author Response
"Please see the attachment."
Author Response File: 
Author Response.pdf
Reviewer 2 Report
The paper presents a high-speed successive approximation register (SAR) analog-to-digital converter that takes advantage of both asynchronous SAR ADC and loop-unrolled (LU) SAR ADC. The most significant contribution of the paper is to relax the burden of calibration and reduce silicon area.
The paper is well written and the contribution is clearly explained. However, some point should be addressed :
- It will be easy for the reader if the authors indicate the reference number of the cited works in tables 1 and 2.
- The authors implemented a 6 bits ADC. Is there any reason of this choice?
- The recent similar work in table 2 ( ref [15] ) depict a better FOM, SNDR and SFDR with 8 bits ; what will be the proposed architecture with 8 bits ?
Author Response
"Please see the attachment."
Author Response File: Author Response.pdf
Reviewer 3 Report
- What is the targeted application for the proposed ADC at 6 bits?
- Table 2: what is the main reason for the drop of SNDR in comparison to JSCC21? Is it due to the absent of calibration?
Author Response
"Please see the attachment."
Author Response File: Author Response.pdf
