# POSIT vs. Floating Point in Implementing IIR Notch Filter by Enhancing Radix-4 Modified Booth Multiplier

^{1}

^{2}

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## Abstract

**:**

## 1. Introduction

- (1)
- Enhancing the POSIT multiplication operation by implementing a special type of multiplier called ERMBM, which significantly enhances the area, speed, and energy compared with the regular multiplier proposed previously in [5].
- (2)
- Implementing the POSIT cosine function along with the division arithmetic unit utilizing a shared hardware that is based on the Taylor series technique to reduce the design area.
- (3)
- (4)
- Comparing the performances of POSIT when utilizing a regular multiplier with floating point which results in better accuracy and area enhancement.

## 2. Background

#### 2.1. POSIT

#### 2.2. IIR Filter

## 3. Related Work

#### 3.1. IIR Filter

#### 3.2. POSIT Numbering System

## 4. Components Design

#### 4.1. Enhanced Radix-4 Modified Booth Multiplier

#### 4.1.1. Computing 2′s Complement

#### 4.1.2. Encoding the Multiplier

^{i}Booth reduces the number of partial products by (#of MR bits/i). To implement an n-bit multiplier when using the Radix-4 Booth encoder, a zero should be placed at position 0 and then each 3 bits are grouped together in (#of MR bits)/2 groups [31]. If the MR or the MD’s total number of bits is of an odd number, then the sign bit is extended. In this paper, a 29 × 29-bit Enhanced Radix-4 Modified Booth Multiplier is implemented. Therefore, the multiplier binary number are grouped into 15 three-bit groups, as shown in Figure 3.

#### 4.2. IIR Notch Filter

- (1)
- POSIT addition/subtraction,
- (2)
- POSIT multiplication,
- (3)
- POSIT division,
- (4)
- Cosine function for POSIT.

#### 4.2.1. POSIT Divider

#### 4.2.2. POSIT Cosine Function

## 5. Results and Discussion

- (a)
- A comparison within POSIT (regular multiplier vs. radix-4 modified booth multiplier)
- (b)
- A detailed comparison between POSIT and floating point

#### 5.1. Second-Order IIR Notch Filter

#### 5.1.1. Calculating the Filter’s Coefficients

#### 5.1.2. Generating the Output of the IIR Filter

#### 5.2. Comparison

#### 5.2.1. Radix-4 Modified Booth Multiplier vs. the Regular POSIT Multiplier

#### Accuracy

#### Area and Speed

#### Power and Energy

#### 5.2.2. A Comparison between POSIT and Floating Point

#### Accuracy

#### Area and Speed

#### Power and Energy

#### 5.3. Discussion

- (1)
- Using the Enhanced Radix-4 Modified Booth Multiplier (ERMBM) instead of a regular multiplier enhances the area, speed, power, and energy without affecting the accuracy of the output.
- (2)
- If the accuracy, area, and power are the main concern, then it is recommended to utilize the POSIT numbering system with a regular multiplier instead of floating point.
- (3)
- If the aim is to enhance all five performance metrics, then it is recommended to use POSIT units along with ERMBM instead of floating point, as POSIT optimizes area, speed, power, and energy by 35.68%, 20.66%, 31.49%, and 45.64%, respectively.

## 6. Conclusions and Future Works

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

## References

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**Figure 1.**POSIT format (2) [9].

**Figure 10.**The shared hardware of the division arithmetic unit that is used to implement $\frac{\mathbf{1}}{{f}_{s}}$.

Finite Impulse Response Filter (FIR Filter) | Infinite Impulse Response Filter (IIR Filter) |
---|---|

Depend on current input only, no feedback is required (only zeros) | Depend on previous output, feedback is required (poles and zeros) |

Uses more number of terms to achieve same result-more computations–slower | Uses less number of terms to achieve same result-less computations–faster. |

Require more memory | Require less memory space |

Can be easily designed with a linear phase | Non-linear phase |

Always stable | Has stability issues–Not always stable |

Has constant delay at all frequencies | Has unequal delays at each frequency |

No analog history | Derived from analog filters |

Used with high order tapping (20–2000) | Used with fewer order tapping type < 1/10th order of FIR filter (4–20) |

Y_{i} | Y_{i−1} | Y_{i−2} | Required Operation on the Multiplicand | Acquired Output |
---|---|---|---|---|

0 | 0 | 0 | 0 × MD | Zero |

0 | 0 | 1 | +1 × MD | Value of the multiplicand |

0 | 1 | 0 | +1 × MD | Value of the multiplicand |

0 | 1 | 1 | +2 × MD | Shifting the MD 1 bit to the left |

1 | 0 | 0 | −2 × MD | Finding 2′s complement of the MD and then shifting 1 bit to the left |

1 | 0 | 1 | −1 × MD | Finding 2′s complement of MD |

1 | 1 | 0 | −1 × MD | Finding 2′s complement of MD |

1 | 1 | 1 | 0 × MD | Zero |

Term | Multiplication | Addition | Cycle Number |
---|---|---|---|

$1/{f}_{s}$ | 10 | 6 | 12 |

$\omega $ | 2 | - | 14 |

$\mathrm{cos}\left(\omega \right)$ | 6 | 3 | 21 |

A2 | 1 | - | 21 |

B1 | 1 | - | 22 |

A1 | 1 | - | 23 |

Equation (13) Result | 3 | 4 | 27 |

**Table 4.**A total of three random cases that were tested to compare the accuracy between the arithmetic units ERMBM and the regular multiplier.

$\mathbf{Case}\mathbf{One}(34.3456\ast 434)$ | ||
---|---|---|

ERMBM | Output in POSIT = 01011011101000111001111111011000 Output in decimal = 14905.99023 | $\mathrm{ERMBM}\mathrm{error}=1.14048107\times {10}^{-6}$ |

Regular POSIT multiplier proposed by [5] | Output in POSIT = 01011011101000111001111111011000 Output in decimal = 14905.99023 | $\mathrm{Regular}\mathrm{multiplier}\mathrm{error}=1.14048107\times {10}^{-6}$ |

MATLAB | 14905.990399999998771818354725838 | |

$\mathbf{Case}\mathbf{Two}\mathbf{(}\mathbf{-}\mathbf{2.3456}\mathbf{\times}{\mathbf{10}}^{\mathbf{-}\mathbf{3}}\mathbf{\ast}\mathbf{0.564}\mathbf{)}$ | ||

ERMBM | Output in POSIT = 11010011010010100110100011100110 $\mathrm{Output}\mathrm{in}\mathrm{decimal}=-1.3229184\times {10}^{-3}$ | $\mathrm{ERMBM}\mathrm{error}=1.63910665\times {10}^{-14}$ |

Regular POSIT multiplier proposed by [5] | 11010011010010100110100011100110 $\mathrm{Output}\mathrm{in}\mathrm{decimal}=-1.3229184\times {10}^{-3}$ | $\mathrm{Regular}\mathrm{multiplier}\mathrm{error}=1.63910665\times {10}^{-14}$ |

MATLAB | −0.0013229183999999998867791450862796 | |

$\mathbf{Case}\mathbf{Three}\mathbf{(}\mathbf{-}\mathbf{585.56}\mathbf{\ast}\mathbf{-}\mathbf{5529.34}\mathbf{)}$ | ||

ERMBM | Output in POSIT = 01100101100010110011110000000010 $\mathrm{Output}\mathrm{in}\mathrm{decimal}=3237760.25$ | ERMBM error = 99.99999748 |

Regular POSIT multiplier proposed by [5] | Output in POSIT = 01100101100010110011110000000010 $\mathrm{Output}\mathrm{in}\mathrm{decimal}=3237760.25$ | Regular multiplier error = 99.99999748 |

MATLAB | 3237760.3303999998606741428375244 |

Bit Configuration | Slice LUTS | DSP48Es | Datapath Delay (ns) | Total Gate Delay (ns Logic) | Total Net Delay (ns Route) |
---|---|---|---|---|---|

Regular POSIT multiplier [5] (Exp = 7 & Regime = 2) | 2634 | 0 | 48.440 | 21.657 | 26.783 |

Enhanced Radix-4 Modified Booth Multiplier (ERMBM) (Exp = 7 & Regime = 2) | 1928 | 0 | 23.268 | 11.698 | 11.570 |

Percentage of area enhancement for ERMBM 26.80% | Percentage of speed enhancement for ERMBM 51.97% |

Bit configuration | Power (mW) | Energy (pJ) |
---|---|---|

Regular POSIT multiplier [5] (Exp = 7 & Regime = 2) | 1117 | 54,107.48 |

Enhanced Radix-4 Modified Booth Multiplier (ERMBM) (Exp = 7 & Regime = 2) | 1111 | 25,850.748 |

Percentage of power enhancement for ERMBM 0.54% | Percentage of energy enhancement for ERMBM 52.22% |

Calculation Source | Generated Output | Calculated Error |
---|---|---|

B1 (POSIT is More Accurate) | ||

B1 from MATLAB | −1.763842361931102233771193617584 | |

B1 from POSIT | 10111110011110001110100110101000 → −1.763842344 | $\mathrm{POSIT}\mathrm{error}=1.01659325\times {10}^{-6}$ |

B1 from FP proposed in [6,7] | bfe1c598 → −1.7638425827026367 | $\mathrm{FP}\mathrm{error}=12.51651160\times {10}^{-6}$ |

A1 (POSIT is more accurate) | ||

A1 from MATLAB | −1.7087222881207552889658438170345 | |

A1 from POSIT | 10111110100101010010001001011011 → −1.708722264 | $\mathrm{POSIT}\mathrm{error}=1.41162526\times {10}^{-6}$ |

A1 from FP proposed in [6,7] | bfdab76b → −1.708722472190857 | $\mathrm{FP}\mathrm{error}=10.77238260\times {10}^{-6}$ |

A2 (same precision) | ||

A2 from MATLAB | 0.9384765625 | |

A2 from POSIT | 00111111110000010000000000000000 → 0.9384765625 | POSIT error = 0 |

A2 from FP proposed in [6,7] | 3f704000 → 0.9384765625 | FP error = 0 |

Sample = 67 (same precision) | ||

Y1 from MATLAB | 67.0 | |

Y1 from POSIT | 0100110000011000000000000000000 → 67.0 | POSIT error = 0 |

Y1 from FP proposed in [6,7] | 42860000 → 67.0 | FP error = 0 |

Sample = −456 (POSIT is more accurate) | ||

Y2 from MATLAB | −459.69304494529324530195843663682 | |

Y2 from POSIT | 10101110011010001001110100101000 → −459.6930466 | $\mathrm{POSIT}\mathrm{error}=0.35995906\times {10}^{-6}$ |

Y2 from FP proposed in [6,7] | c3e5d8b6 → −459.69305419921875 | $\mathrm{FP}\mathrm{error}=2.01306624\times {10}^{-6}$ |

Sample = 19 (POSIT is more accurate) | ||

Y3 from MATLAB | 41.946435760963943178399103612273 | |

Y3 from POSIT | 01001010100111110010010010000000 → 41.9464111328125 | $\mathrm{POSIT}\mathrm{error}=58.71333520\times {10}^{-6}$ |

Y3 from FP proposed in [6,7] | 4227c930 → 41.94647216796875 | $\mathrm{FP}\mathrm{error}=86.79403660\times {10}^{-6}$ |

Sample = 28 (POSIT is More Accurate) | ||

Y4 from MATLAB | 41.572953440710447008497063642695 | |

Y4 from POSIT | 01001010100110010010101010101000 → 41.57291412 | $\mathrm{POSIT}\mathrm{error}=94.58243210\times {10}^{-6}$. |

Y4 from FP proposed in [6,7] | 42264ac0 → 41.572998046875 | $\mathrm{FP}\mathrm{Error}=107.29611600\times {10}^{-6}$ |

Sample = 160 (POSIT is more accurate) | ||

Y5 from MATLAB | 161.28329915100100573765568271504 | |

Y5 from POSIT | 01001110100001010010001000001101 → 161.2832546 | $\mathrm{POSIT}\mathrm{Error}=27.62282350\times {10}^{-6}$ |

Y5 from FP proposed in [6,7] | 4321488a → 161.28335571289062 | $\mathrm{FP}\mathrm{Error}=35.06989870\times {10}^{-6}$ |

Sample = 39 (POSIT is more accurate) | ||

Y6 from MATLAB | 21.358347613975862138928193744926 | |

Y6 from POSIT | 01001000101010110111011100110000 → 21.35829926 | $\mathrm{POSIT}\mathrm{Error}=226.3938050\times {10}^{-6}$ |

Y6 from FP proposed in [6,7] | 41aade00 → 21.3583984375 | $\mathrm{FP}\mathrm{Error}=237.9562550\times {10}^{-6}$ |

Sample = 142 (POSIT is more accurate) | ||

Y7 from MATLAB | 118.34503631422772995296612011743 | |

Y7 from POSIT | 01001101101100101100001010001101 → 118.3449955 | $\mathrm{POSIT}\mathrm{Error}=34.48748590\times {10}^{-6}$ |

Y7 from FP Proposed in [6,7] | 42ecb0ae → 118.34507751464844 | $\mathrm{FP}\mathrm{Error}=34.81381390\times {10}^{-6}$ |

Sample = 151 (POSIT is more accurate) | ||

Y8 from MATLAB | 121.70887719492042148245152838541 | |

Y8 from POSIT | 01001101110011011010101110111000 → 121.70887402 | $\mathrm{POSIT}\mathrm{Error}=2.60861861\times {10}^{-6}$ |

Y8 from FP proposed in [6,7] | 42f36af6 → 121.70890808105469 | $\mathrm{FP}\mathrm{Error}=25.37705960\times {10}^{-6}$ |

Sample = 117 (FP is more accurate) | ||

Y9 from MATLAB | 89.562431604401888060911774239986 | |

Y9 from POSIT | 01001100110011000111111111010100 → 86.56241608 | $\mathrm{POSIT}\mathrm{Error}=3349636.081\times {10}^{-6}$ |

Y9 from FP proposed in [6,7] | 42b31ff8 → 89.56243896484375 | $\mathrm{FP}\mathrm{Error}=8.21822468\times {10}^{-6}$ |

Sample = 294 (POSIT is more accurate) | ||

Y10 from MATLAB | 277.44683801916972138270230542038 | |

Y10 from POSIT | 01010000001010101110010011001000 → 277.4468384 | $\mathrm{POSIT}\mathrm{Error}=0.13726243\times {10}^{-6}$ |

Y10 from FP proposed in [6,7] | 43687263 → 277.4468231201172 | $\mathrm{FP}\mathrm{Error}=5.37005671\times {10}^{-6}$ |

**Table 8.**Comparison of the area and speed between 32-bit POSIT IIR notch filter utilizing a regular multiplier and a 32-bit floating point second-order IIR notch filter.

Bit Configuration | Slice LUTS | DSP48Es | Datapath Delay (ns) | Total Gate Delay (ns Logic) | Total Net Delay (ns Route) |
---|---|---|---|---|---|

32-bit POSIT utilizing regular multiplier in implementing IIR notch filter (Exp = 7 & Regime = 2) | 5729 | 8 | 58.070 | 28.799 | 29.271 |

32-bit FP IIR notch filter using the proposed FP adder/subtractor & the proposed multiplier | 7323 | 8 | 41.918 | 14.744 | 27.174 |

Percentage of area enhancement for POSIT 21.77% | Percentage of speed enhancement for FP 27.81% |

**Table 9.**Comparison of the area and speed between a 32-bit POSIT IIR notch filter utilizing an ERMBM and a 32-bit floating point second-order IIR notch filter.

Bit Configuration | Slice LUTS | DSP48Es | Datapath Delay (ns) | Total Gate Delay (ns Logic) | Total Net Delay (ns Route) |
---|---|---|---|---|---|

32-bit POSIT utilizing ERMBM in implementing IIR notch filter (Exp = 7 & Regime = 2) | 12,270 | 0 | 58.014 | 28.844 | 29.17 |

32-bit FP IIR notch filter using the proposed FP adder/subtractor & the proposed multiplier | 19,077 | 0 | 73.125 | 32.918 | 40.207 |

Percentage of area enhancement for POSIT 35.68% | Percentage of speed enhancement for POSIT 20.66% |

**Table 10.**Comparison of the power and energy between a 32-bit POSIT IIR notch filter utilizing a regular multiplier and a 32-bit floating point second-order IIR notch filter.

Bit Configuration | Power (mW) | Energy (pJ) |
---|---|---|

32-bit POSIT utilizing regular multiplier in implementing IIR notch filter (Exp = 7 & Regime = 2) | 1630 | 94,654.1 |

32-bit FP IIR notch filter using the proposed FP adder/subtractor & the proposed multiplier | 2671 | 111,962.98 |

Percentage of power enhancement for POSIT 38.98% | Percentage of energy enhancement for POSIT 15.46% |

**Table 11.**Comparison of the power and energy between a 32-bit POSIT IIR notch filter utilizing an ERMBM and a 32-bit floating point second-order IIR notch filter.

Bit Configuration | Power (mW) | Energy (pJ) |
---|---|---|

32-bit POSIT utilizing ERMBM in implementing IIR notch filter (Exp = 7 & Regime = 2) | 1619 | 93,924.67 |

32-bit FP IIR notch filter using the proposed FP adder/subtractor & the proposed multiplier | 2363 | 172,794.38 |

Percentage of power enhancement of POSIT 31.49% | Percentage of energy enhancement of POSIT 45.64% |

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**MDPI and ACS Style**

Esmaeel, A.A.; Abed, S.; Mohd, B.J.; Fairouz, A.A.
POSIT vs. Floating Point in Implementing IIR Notch Filter by Enhancing Radix-4 Modified Booth Multiplier. *Electronics* **2022**, *11*, 163.
https://doi.org/10.3390/electronics11010163

**AMA Style**

Esmaeel AA, Abed S, Mohd BJ, Fairouz AA.
POSIT vs. Floating Point in Implementing IIR Notch Filter by Enhancing Radix-4 Modified Booth Multiplier. *Electronics*. 2022; 11(1):163.
https://doi.org/10.3390/electronics11010163

**Chicago/Turabian Style**

Esmaeel, Anwar A., Sa’ed Abed, Bassam J. Mohd, and Abbas A. Fairouz.
2022. "POSIT vs. Floating Point in Implementing IIR Notch Filter by Enhancing Radix-4 Modified Booth Multiplier" *Electronics* 11, no. 1: 163.
https://doi.org/10.3390/electronics11010163