# Robust Circuit and System Design for General-Purpose Computational Resistive Memories

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Memory Array Topology and In-Memory Logic Schemes

#### 2.1. Definitions and Assumptions for Memristors

_{OFF}or HRS) and logic “1” with a low resistive state (R

_{ON}or LRS) [20], as shown in Figure 1a. According to Figure 1b,c, a SET process (HRS → LRS) occurs when the device is forward biased with a voltage of amplitude higher than a V

_{SET}threshold, whereas a RESET process (LRS → HRS) occurs when it is reverse-biased with a voltage amplitude higher than a |V

_{RESET}| threshold. Applied voltages of amplitude lower than such thresholds do not affect the device state and are thus used for memory read operations. Device polarity is defined by the thick black line in bottom electrode (BE) of the memristor symbol in the circuit schematics. All simulation results were based on the model of Yakopcic et al. [21]. It is a threshold-type model of a voltage-controlled memristor belonging to the hyperbolic sine models and can capture rich switching dynamics, while it also supports nonlinear HRS and LRS states. The model was tuned with parameter values selected so as to demonstrate switching time in the ns-regime and memristance ratio HRS/LRS = 10

^{6}, being in accordance with experimental results in Reference [22] for amorphous silicon (a-Si)-type memristors.

#### 2.2. One Transistor One Memristor (1T1R) Crossbar Array

_{i}connects to the gate terminal of all the select transistors in the same crossbar row, so as to simultaneously select/enable all the n memristive cross-points in a memory word. Each bitline BL

_{j}drives all the m cross-points found in the same column of the array, whose memristors have their bottom electrode (BE) commonly connected to a crossbar output line (OL). Through the sensing circuitry, every OL is selectively connected either to logic components or to ground. Depending on whether a memory (read/write) or a logic operation is performed, the wordline decoder will activate simultaneously between one and three wordlines, while the target bitlines are driven accordingly with the corresponding read/write voltage pulses (or otherwise are left floating).

#### 2.3. Sensing Circuit Implementations That Enable Memristor-Based Logic Operations

_{i}) and a network of pull-down resistors in the sense amplifier (SA

_{i}). This scheme requires that the SA

_{i}, which is connected to the crossbar OL

_{i}, supports reconfigurable reference voltages. In this direction, Figure 3 shows a voltage-based SA circuit that complies with this requirement. It was originally proposed in Reference [17] to enable memory read operations, as well as 2-input AND/OR/XOR logic operations. In fact, a read voltage pulse (of amplitude lower than the SET threshold of the memristors) is applied to the target bitlines while activating two wordlines for two-input logic gates. Note that there is no output memristor in this scheme: the logic output is not directly stored in a memristor during the logic operations. Instead, the logic output is the voltage at the output node OL of the aforementioned voltage divider. This constitutes a major departure from stateful logic styles, such as IMPLY or MAGIC, which indeed subject a properly initialized output memristor to a “conditional write” operation [8,13,14]. Moreover, since memory/logic output data are represented in voltage, if required, the output can be stored back to any memory element(s) right afterwards via a reliable memory write operation. Thus, conducting chained operations assumes an intermediate write step to store the output of one stage to a memory location, so that is can later be used as input to subsequent stages. At first glance, such a read + write operation sequence impacts negatively logic latency. Nevertheless, as shown in the following sections, a properly designed memory module can allow for the simultaneous writing of the memory/logic readout result to the crossbar array (i.e., “a write while reading concept”).

_{r1}is conducting, pulling V

_{IN2}to ground, whereas V

_{IN1}results from the voltage divider between the two input memristors and resistor R

_{1}. The value of R

_{1}was selected such that, when at least one of the memristors is in LRS, V

_{IN1}will be high enough to be interpreted as logic “1” by the CMOS XOR gate and thus produce a logic “1” output. Note that, for a memory read operation, the SA function is practically equivalent to a logic OR gate but with only one input. Similarly, for an AND gate, there are two pull-down resistors connected in parallel, so that only when both input memristors are in LRS will the V

_{IN1}voltage be high enough to cause a logic “1” output. An XOR logic operation is realized by the SA if only the transistor S

_{r3}is conductive. In such a case, the series combination of resistors R

_{1}and R

_{3}is activated, with V

_{IN2}being now equal to the voltage on resistor R

_{3}. When both memristors are in HRS (LRS), both V

_{IN1}and V

_{IN2}are low (high) and equivalent to logic “0” (logic “1”). Thus, only when one of the memristors is in LRS does the CMOS XOR gate give a logic “1” output. For AND, OR, and XOR logic operations with more than 2 inputs, the required values for the pull-down resistors might have to be re-calculated. However, by using the exact same SA configuration as for the AND gate while activating a third input memristor (thus a third WL in the crossbar), we figured out that the same circuit can implement a three-input majority (MAJ) logic operation. Certainly, MAJ can be implemented in different ways, e.g., by comparing the current through the crossbar OL with a current threshold, as in Reference [18]. MAJ is worth being considered in such computational memory as it can accelerate certain tasks in arithmetic operations. Therefore, it is important that the considered SA circuit is able to implement MAJ computation as well. For readability reasons, Table A1 in Appendix A presents all possible SA configurations with their equivalent circuits, along with the mathematical expression describing the resulting voltage inputs applied to the CMOS XOR gate.

_{OLk}(see Table A1), only leads to slightly modified voltage at the input nodes of the CMOS XOR gate. So, if the inherent variability of HRS and LRS of memristors affects the resulting V

_{IN1,2}input voltages to a similar degree, this could potentially lead to erroneous logic computations at the CMOS XOR gate.

_{read}, which is commonly applied to all memristors connected to the same crossbar OL. Depending on the SA configuration, different comparisons are enabled based on different threshold voltages, owing to the configurable resistive network (R

_{1–4}). For example, in case of MAJ, the combination “HRS, HRS” = “00” will produce a very small voltage sum, whereas “HRS, LRS” = “01” (or “10”) will give a higher voltage sum, and “LRS, LRS” = “11” will result in the highest voltage sum, which we compare with a voltage threshold in the final stage. For higher reliability, in this case, the resulting voltage threshold should be ideally located in the middle point between the value corresponding to having two memristors in LRS versus having only one memristor in LRS. For both SA circuits, the resistor values were selected based on simulation results to maximize the reliability of the supported logic operations.

_{IN1,2}input voltages of the CMOS XOR gate of the circuit shown in Figure 3, calculated by using the equations presented in Table A1 for all possible combinations of the input data, expressed in HRS and LRS values. Likewise, Table 1 also presents the resulting input voltage applied to the comparator(s) stage (V

_{comp}) and the configurable thresholds (V

_{th,1,2}) for the circuit shown in Figure 4, calculated by using the equations presented in Table A2. By observing the data, it can be figured out that, indeed, in the alternative SA implementation, a change in the logic state of any input memristor has a much higher impact on the voltage representing the weighted sum in the alternative SA (V

_{comp}), compared to the change induced to the output of the voltage divider (V

_{IN1}) which is applied to the input nodes of the CMOS XOR gate in the original SA implementation.

#### 2.4. Performance Comparison in Presence of HRS and LRS Variability

_{read}= 0.85 V and V

_{dd}= 2 V, and assuming 0.4 V as threshold voltage for the CMOS XOR gate [17], we calculated the resulting voltages at the nodes of interest of both SA modules. Figure 5 shows the evaluation results, wherein an error corresponds to an erroneous logic output at the SA circuits for a given input combination. We repeated the tests for an increasing SD of HRS and LRS distributions. The results in Figure 5a,b concern 10% and 20%, respectively.

- Both circuits are robust for memory read and OR logic operations.
- The original scouting SA presents an increasing error percentage up to 20% in MAJ operations when we apply input combinations with only one logic “1” (i.e., “001”, “010”, and “100”). This is attributed to the fact that the V
_{IN1}value for nominal HRS and LRS values (0.36 V in Table 1) is very close to the threshold of the CMOS XOR gate. On the contrary, observed errors in the proposed circuit reach up to 3% for the same input combination when 20% SD is considered. - The original scouting SA presents an increasing error percentage for the AND operation up to 21% when we apply input combinations with only one logic “1” (i.e., “01” and “10”), whereas the observed error in the proposed alternative circuit generally does not exceed 3% when 20% SD is considered.
- The most error-prone logic operation is XOR, for which the original scouting SA presents errors up to 33% when we apply input combinations with only one logic “1” (i.e., “01” and “10”). On the contrary, the observed errors in the proposed alternative SA topology generally do not exceed 2% when 20% SD is considered.

_{IN1}voltage at the CMOS XOR gate terminal for nominal HRS and LRS is very close to the switching threshold of the CMOS XOR gate, then the slightest perturbance of the input memristance can result in mostly erroneous behavior. Therefore, in the rest of this work, we exploit the proposed alternative SA circuit within a novel computational ReRAM architecture.

## 3. The “Twin” Computational ReRAM Architecture

#### 3.1. Overall Design Description

#### 3.2. Hardware Modules for Bit/Word-Wise Memory and Logic Operations

_{k}). Its functionality is configured via four control bits. Two of them are used as configuration bits of the SA circuit, as shown in Figure 4, for memory (Read) or logic operations. Another bit (Output Op Sel) is used in the top DEMUX to define whether the crossbar OL

_{k}will connect to the SA circuit, or to ground, which is necessary for memory write (SET/RESET) operations. One last bit is used as selection line in the output MUX shown at the bottom, to make readily available the inversion of the memory/logic result. The basic logic functions supported by the system (AND, OR, NOT, XOR, and MAJ) and their complements form a basis for more complex arithmetic operations.

_{N}, In

_{N-1}, … In

_{2}, In

_{1}” are reorganized as “In

_{N-2}, In

_{N-3}, … 0, 0”. When the number of displacements to apply is 0, the output is equivalent to the input. These logic values are used at the write driver MUXes as selection signals to allow the corresponding SET/RESET write voltages to be applied to the memristors that will store the memory/logic results.

#### 3.3. Supported Set of Instructions/Operations

_{3}bit is the selection line of SA DEMUX; b

_{2}b

_{1}are the configuration bits for the internal SA module, whereas b

_{0}defines the inversion of the memory/logic output in the output MUX. Memory read/write operations require the mode selection bit to be “0” to take place in a target sub-array independently. On the contrary, the copy operation requires the mode selection bit to be “1” since the target sub-array is different from the source sub-array. However, in all logic operations the mode selection bit can take any value, since the results can be either driven directly to the external output or written to the adjacent sub-array. Finally, the bit-shift/selection operations do not take place in the SA but instead in their respective modules, thus there is no SA configuration code shown in their case. According to the list of operations in Table 2, we defined a generic form for the corresponding ReRAM instructions, shown in Figure 9. More specifically, Figure 9a shows the code describing the address of a target word in the two sub-arrays; the most significant 1+logm bits define the target sub-array and the selected wordline in the Wordline Decoder, whereas the last 1+logn bits are the control bits of the Bitline Selector, allowing to activate the entire word or only a specific bitline. The address code field is present in all forms of the instructions, as shown in Figure 9b–d. They consist of an opcode represented by the four SA control bits shown in Table 2, followed by the mode selection bit (Mode Code), the output/input address fields and the inputs of the Shift Controller.

## 4. Examples of Memory and Logic Operations

#### 4.1. System-Level Configuration Example

_{dd}= 2 V. For all memristors, we used the hyperbolic sine-type model of a bipolar threshold-based switching memristor proposed by Yakopcic et al. [21]. Such a model has been correlated against several published device characterization data with very good precision, closely approximating performance of physics-based models [29]. Parameters were set in accordance with experimental data for amorphous silicon (a-Si)-type memristors [22] that are suitable for digital applications, as follows: a1 = 1.6 × 10

^{−4}, a2 = 1.6 × 10

^{−4}, b = 0.05, Vp = 1.088, Vn = 1.088, Ap = 81,600,000, An = 81,600,000, xp = 0.985, xn = 0.985, alphap = 0.1, alphan = 0.1, and xo = 0.01. The read/write pulses applied to the bitlines were 150 ns wide, and the amplitude was 1.7 V for SET, −1.5 V for RESET, and 0.9 V for READ operations. The corresponding memristance boundary values (for a given V

_{read}voltage) were R

_{ON}= 125 KΩ and R

_{OFF}= 125 GΩ, whereas the SET/RESET switching time was 10 ns.

#### 4.2. Simulation Results for Individual Memory and Logic Operations

_{1}. The latter will either reflect the result of a memory read/logic operation or will be 0 V when a write operation takes place and the OL is connected to ground. Note also that, during every cycle, the MUX/DEMUXes of the crossbar sub-array are enabled 30 ns after the read/write voltages have been correctly set up in the bitline drivers, to make sure the SA output is correctly updated and all MUX/DEMUXes have valid selection signals.

#### 4.3. Simulation Results for n-Bit Binary Addition

_{i}and B

_{i}bits (along with carry-in C

_{i}bit) takes place according to equation S

_{i}= A

_{i}⊕ B

_{i}⊕ C

_{i}for Sum and C

_{i}= A

_{i−1}B

_{i−1}+ B

_{i−1}C

_{i−1}+ A

_{i−1}C

_{i−1}for Carry, respectively. This way, through such a case study of arithmetic computing, we highlight all the major benefits offered by the proposed “twin” computational ReRAM.

_{OFF}(HRS) value. The simulation starts with an initialization phase which lasts three cycles, in which we update the memory content to be used as input to the logic operation, and we also RESET the devices in two auxiliary words which will hold intermediate data during computations. During the next four cycles, the logic operations in both sub-arrays are carried out. The result of the binary addition is stored in a memory word in the last cycle (cycle N° 8). Figure 12 shows the simulation results where every different 150 ns cycle is designated by vertical dashed lines. More specifically, Figure 12a shows the voltages applied to the bitlines of each sub-array, whereas Figure 12b shows the evolution of the logic state of the memristors in the words involved in the computation. Finally, Figure 12c shows the output voltage of the SA Array of the two crossbars. For readability reasons, in Table 3, we describe graphically all the simulated computational steps required to perform the binary addition of numbers “011” and “010”. In Table 3, we use the notation “word[N° crossbar][N° row]” to refer to a complete word, whereas for operations on a single bit of a specific word, we use “bit[N° crossbar][N° row][N° column]”. Left/right sub-array is mentioned as crossbar N° 1/N° 2. We included a series of schematics as a guide to the eye for all the operations, highlighting the active word-/bit-lines in red color, while showing the logic inputs applied to the bitlines during the write operations, and the SA Array configuration at the bottom of every sub-array.

_{i}and B

_{i}) for the binary addition. Next, in cycle N° 3, we write simultaneously “000” both to word 3 of crossbar 1 and to word 2 of crossbar 2, which will hold intermediate results of Carry bits. The first logic operation takes place in the fourth cycle, being a logic XOR(A, B) with the contents of words 1 and 2 of crossbar 1. The result is written to word 1 of crossbar 2 in the same cycle. This can be verified by observing Figure 12c; the final output of the SA modules of crossbar 1 shows “100”, which is the same with the final state of the memristors observed in word 1 of crossbar 2 in Figure 12b. At the same time, we observe that the SA array of crossbar 2 connects all bitlines to ground for the write operation to take place correctly. Next, we sequentially compute the resulting Carry bit from each bitline using the majority operation according to equation C

_{out}= MAJ(A, B, C

_{in}) = AB + BC

_{in}+ AC

_{in}. During Carry bit computations, given that the produced C

_{i}in every stage i acts as input for stage i+1, we exploit the Shift Controller to apply a left shift to the SA output of crossbar 1, and the Bitline Selector of crossbar 2 to activate only one target bitline, where the computed C

_{i}should be stored.

_{in}is zero for the LSB stage, crossbar 2 has already a logic “0” in bitline 1, owing to the RESET write operation performed in cycle N° 3. Next, the recently produced C

_{i}is copied to the memristor in word 3 and bitline 2 of crossbar 1, so that, in cycle N° 7, we can compute again the MAJ operation. However, this time, MAJ is performed at bitline 2 of crossbar 1 to produce the last Carry bit, which we simultaneously store in the memristor in word 2 and bitline 3 of crossbar 2. In Figure 12b, we can confirm that a logic “1” is stored in crossbar 2 as a final Carry bit to the memristor in word 2 and bitline 3, as expected. Finally, in the eighth cycle, we compute the result of Sum with another XOR operation performed in crossbar 2 with the contents of word 1, which holds the result of the previous XOR operation, and word 2, which holds the computed Carry bits. The result is stored simultaneously to word 3 of crossbar 1, which eventually holds “101” (equal to “011” + “010”), as we can confirm by checking Figure 12b.

#### 4.4. Performance Comparison Results

## 5. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## Appendix A

SA Operation | Equivalent Circuit |
---|---|

Read | |

OR | |

XOR | |

AND | |

MAJ |

_{OLk}in equations stands for the equivalent resistance of the parallel input memristors.

SA Operation | Equivalent Circuit |
---|---|

Read | |

OR | |

XOR | |

AND | |

MAJ |

_{1–3}stands for the memristance of any input memristor.

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**Figure 1.**(

**a**) Memristance range and HRS/LRS correspondence with logic “0”/“1”. Intermediate forbidden state is defined by the highest LRS and the lowest HRS, respectively. (

**b**) Memristor switching behavior when forward or reverse-biased. TE/BE stand for Top/Bottom Electrode. (

**c**) Cartoon plot showing the required voltage pulses, which are higher than the switching thresholds, to be applied for SET/RESET memory write operations (light gray shade), and pulses of lower amplitude used for memory read operations (light green shade). Dashed horizontal lines denote the SET/RESET thresholds.

**Figure 2.**Circuit schematic of a 1T1R crossbar array. WL

_{i}denotes wordlines, whereas BL

_{i}denotes bitlines. The bottom electrodes (BE) of memristors (denoted by the black thick line) in every column output line (OL) connect to a sense amplifier, SA

_{i}, or to ground. (Different color is used for crossing WL and OL lines that are not connected.)

**Figure 3.**Circuit schematic of voltage-based sense amplifier for scouting logic (adapted from Reference [17]). Inset shows the different possible configurations to activate different voltage reference values at IN

_{1,2}terminals. Resistor values were selected based on simulation results, assuming 2-input AND/OR/XOR logic operations, and memristors with HRS/LRS = 125 GΩ/125 KΩ.

**Figure 4.**Circuit schematic of an alternative voltage-based sense amplifier for scouting logic. It consists of a summing amplifier, an inverting amplifier, and a configurable comparator stage (far right side of the schematic). Resistor values were selected based on simulation results, assuming 2-input AND/OR/XOR logic operations and memristors with HRS/LRS = 125 GΩ/125 KΩ.

**Figure 5.**Performance evaluation results for the original “Scouting” SA and the “Proposed” SA circuit, showing the error percentage observed in 100.000 samples for each input combination, for memory and logic operations. Results concern (

**a**) 10% and (

**b**) 20% SD for the HRS and LRS distributions with mean values HRS/LRS = 125 GΩ/125 KΩ.

**Figure 6.**Block level description of the proposed computational memory, consisting of a symmetric segmented structure with two “twin” 1T1R crossbar sub-arrays with dedicated peripheral circuitry and control signals. Adapted from Reference [19].

**Figure 7.**Compact block-level description of the configurable voltage-based sensing module, which connects to a crossbar output line OL

_{k}(BE of memristors), enabling either memory or logic operations. The block entitled “AND/MAJ/OR/XOR” corresponds to the SA circuit in Figure 4.

**Figure 8.**Compact block-level description of the Shift Controller module, which applies a number of logical left/right displacements to the N input lines In

_{1}…In

_{N}equal to the number given by the Shift Ctrl bits. The yellow blocks hide routing of interconnection lines between the modules (not shown for clarity).

**Figure 9.**Description of the fields composing the system instructions. (

**a**) The form of the address code present in all instruction types. The full instruction form for memory read/logic operations towards the external interface is shown in (

**b**), and for memory write operations of externally applied input, it is shown in (

**c**). The full instruction form for memory read/logic operations when the output is written to the adjacent sub-array is shown in (

**d**). Unused fields are shown in a light gray color.

**Figure 10.**Configuration of the system’s modules to perform word-wise XOR operation with simultaneous storage of results to the adjacent sub-array. Text in blocks reveals the actual action performed in all modules. Inactive modules are shown in a light gray shade. The active wordlines in the two sub-arrays and the valid SA configuration (shown in the inset) are highlighted in red color.

**Figure 11.**Circuit simulation results for operations performed in a single bitline of the computational ReRAM. From top to bottom, we observe the voltage applied to bitline BL

_{1}, the evolution of the logic state (expressing conductivity in the model) of the memristors in words 1–3 connected to BL

_{1}(notation “memristor XY” in the legend means wordline X and bitline Y), and the output voltage of the SA connected to OL

_{1}. Logic “1” corresponds to 2 V in the SA output voltage. Vertical dashed lines designate different 150 ns–wide cycles of operation.

**Figure 12.**Circuit simulation results for a binary addition performed inside the computational ReRAM. (

**a**) Shows the voltages applied to three bitlines of interest in both sub-arrays. (

**b**) Shows the evolution of the logic state of the memristors in all the words involved in the computation. Notation “memristor XY” in the legend means the device in wordline X and bitline Y. (

**c**) Shows the output voltage of the SA Array modules of the two sub-arrays. Logic “1” corresponds to 2 V in the SA output voltage. Vertical dashed lines designate different 150 ns–wide cycles of operation.

**Table 1.**Calculated voltages at nodes of interest of the SA modules for all possible configurations.

Operation | Input Resistance | Original SA | Alternative SA | Logic Output | |||||
---|---|---|---|---|---|---|---|---|---|

R_{1}(KΩ) | R_{2}(KΩ) | R_{3}(KΩ) | V_{IN1}(V) | V_{IN2}(V) | V_{comp}(V) | V_{th1}(V) | V_{th2}(V) | ||

Read | 125 | X | X | 0.6 | 0 | 0.9 | 0.571 | X | 1 |

Read | 125 × 10^{6} | X | X | 1.8 × 10^{−6} | 0 | 9 × 10^{−7} | 0.571 | X | 0 |

OR | 125 | 125 | X | 0.72 | 0 | 1.8 | 0.571 | X | 1 |

OR | 125 | 125 × 10^{6} | X | 0.6 | 0 | 0.9 | 0.571 | X | 1 |

OR | 125 × 10^{6} | 125 × 10^{6} | X | 3.6 × 10^{−6} | 0 | 1.8 × 10^{−6} | 0.571 | X | 0 |

AND | 125 | 125 | X | 0.514 | 0 | 1.8 | 1.333 | X | 1 |

AND | 125 | 125 × 10^{6} | X | 0.36 | 0 | 0.9 | 1.333 | X | 0 |

AND | 125 × 10^{6} | 125 × 10^{6} | X | 1.2 × 10^{−6} | 0 | 1.8 × 10^{−6} | 1.333 | X | 0 |

XOR | 125 | 125 | X | 0.8 | 0.433 | 1.8 | 0.571 | 1.429 | 0 |

XOR | 125 | 125 × 10^{6} | X | 0.73 | 0.37 | 0.9 | 0.571 | 1.429 | 1 |

XOR | 125 × 10^{6} | 125 × 10^{6} | X | 7.8 × 10^{−6} | 4.17 × 10^{−6} | 1.8 × 10^{−6} | 0.571 | 1.429 | 0 |

MAJ | 125 | 125 | 125 | 0.6 | 0 | 2.7 | 1.333 | X | 1 |

MAJ | 125 | 125 | 125 × 10^{6} | 0.514 | 0 | 1.8 | 1.333 | X | 1 |

MAJ | 125 | 125 × 10^{6} | 125 × 10^{6} | 0.36 | 0 | 0.9 | 1.333 | X | 0 |

MAJ | 125 × 10^{6} | 125 × 10^{6} | 125 × 10^{6} | 1.8 × 10^{−6} | 0 | 2.7 × 10^{−6} | 1.333 | X | 0 |

_{th1}is equivalent to V

_{th}in Table A2 when there is one threshold.

**Table 2.**Summary of operations supported by the proposed computational memory system. X means a don’t care value.

Operation | Description | SA Ctrl Bits b _{3}b_{2}b_{1}b_{0} | Mode Sel Bit |
---|---|---|---|

Copy | Copy data to adjacent crossbar | 0000 | 1 |

Inv | Inversion of the value in the SA output | XXX1 | X |

OR | 2-input logic OR for two words in the same sub-array | 0000 | X |

AND | 2-input logic AND for two words in the same sub-array | 0010 | X |

XOR | 2-input logic XOR for two words in the same sub-array | 0100 | X |

MAJ | 3-input MAJORITY for three words in the same sub-array | 0010 | X |

Write | Write external input data to a memory word | 1XXX | 0 |

Read | Read data stored in a memory word, to the external output | 0000 | 0 |

Bit shift | Apply left/right logical shift to the SA output through the Shift Controller | N/A | X |

Bit selection | Activate one target bitline through the Bitline Selector | N/A | X |

Cycle | Operation | Output/Destination | Input | Schematic Guide |
---|---|---|---|---|

1 | Write | word 11 | 011 | |

2 | Write | word 12 | 010 | |

3 | Write | word 22 | 000 | |

Write | word 13 | 000 | ||

4 | XOR | word 21 | word 11 word 12 | |

5 | MAJ | bit 222 | bit 111 bit 121 bit 131 | |

6 | Copy | bit 132 | bit 222 | |

7 | MAJ | bit 223 | bit 112 bit 122 bit 132 | |

8 | XOR | word 13 | word 21 word 22 |

**Table 4.**Form of instructions executed to perform the binary addition. Colors in the values given for input/output addresses designate the different fields of the address code in Figure 9a. X means a don’t care value.

Cycle | Opcode | Mode | Output | Input(s) | Shift |
---|---|---|---|---|---|

1 | 1XXX | 0 | 001000 | 011 | XXX |

2 | 1XXX | 0 | 010000 | 010 | XXX |

3 | 1XXX | 0 | 011000 | 000 | XXX |

1XXX | 0 | 110000 | 000 | XXX | |

4 | 0100 | 1 | 101000 | 001000 010000 | 000 |

5 | 0010 | 1 | 110101 | 001011 010011 011011 | 001 |

6 | 0000 | 1 | 011101 | 110101 | 000 |

7 | 0010 | 1 | 110111 | 001101 010101 011101 | 001 |

8 | 0100 | 1 | 011000 | 101000 110000 | 000 |

IMPLY [30,31] | MAGIC [32] | NAND [33] | MAJ+NOT [18] | Proposed | ||||||
---|---|---|---|---|---|---|---|---|---|---|

Steps | Area | Steps | Area | Steps | Area | Steps | Area | Steps | Area | |

OR | 2 | 3 | 2 | 4 | 2 | 6 | 3 | 3 | 1 | 2 |

AND | 3 | 3 | 2 | 5 | 1 | 3 | 1 | 3 | 1 | 2 |

NOR | 3 | 3 | 1 | 3 | 3 | 6 | 3 | 3 | 1 | 2 |

NAND | 2 | 3 | 3 | 5 | 1 | 3 | 1 | 3 | 1 | 2 |

XOR | 4 | 5 | 3 | 6 | 3 | 6 | 5 | 6 | 1 | 2 |

MAJ | 26 | 5 | 6 | 6 | 7 | 7 | 1 | 3 | 1 | 3 |

Description | Latency (Steps) | Circuit Area (N° of Memristors) | Reference |
---|---|---|---|

MAGIC (NOR, area optimized) | 15n | 5 | Talati et al. [32] |

MAGIC (lNOR, latency optimized) | 12n + 1 | 11n − 1 | Talati et al. [32] |

IMPLY (parallel) | 5n + 18 | 6n − 1 | Kvatinsky et al. [31] |

IMPLY (serial) | 22n | 2 | Rohani et al. [34] |

IMPLY (semi-serial) | 17n | 2 | Rohani et al. [12] |

NAND | 10n | 9 | Huang et al. [33] |

ORNOR | 2n + 15 | 6n + 6 | Siemon et al. [35] |

MAJ + NOT | 4log_{2}n + 6 | 6(6n + 16) | Reuben et al. [36] |

Enhanced Scouting(XOR and MAJ) | 2n + 2 | 3n | This work |

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**MDPI and ACS Style**

Pinto, F.; Vourkas, I.
Robust Circuit and System Design for General-Purpose Computational Resistive Memories. *Electronics* **2021**, *10*, 1074.
https://doi.org/10.3390/electronics10091074

**AMA Style**

Pinto F, Vourkas I.
Robust Circuit and System Design for General-Purpose Computational Resistive Memories. *Electronics*. 2021; 10(9):1074.
https://doi.org/10.3390/electronics10091074

**Chicago/Turabian Style**

Pinto, Felipe, and Ioannis Vourkas.
2021. "Robust Circuit and System Design for General-Purpose Computational Resistive Memories" *Electronics* 10, no. 9: 1074.
https://doi.org/10.3390/electronics10091074