A Hardware-in-the-Loop-on-Chip Development System for Teaching and Development of Dynamic Systems

Abstract

This paper proposes a low-cost on-chip Hardware-in-the-Loop (HIL) platform for teaching and fast prototyping of dynamic systems. A dual-core digital signal controller (DSC)-based solution is proposed for the HIL system. CPU core A, as the simulation engine, is dedicated to circuit and system simulation. The actuation and control logic are implemented in CPU core B, which is working as the control engine. Inter-processor communication is used to interchange variables between the CPUs. The digital-to-analog converter and digital outputs are used to send the duty cycle and system state variables to the oscilloscope for users’ visual feedback. Two typical systems with fast and slow dynamics are modeled and implemented in the simulation engine. Under the excitation generated by the control engine, system dynamics can be observed for studying purposes. Close-loop control for a buck converter is also demonstrated on the developed prototype, where both input voltage and load variations performance are tested. The test results indicate that the digital simulator can well emulate the average small signal model of a power converter in open-loop and close-loop scenario. Meanwhile, the control parameters can be modified for system performance evaluation and education purposes. The proposed low-cost HIL system can be easily applied to the engineering teaching as well as fast prototype development phase of product design.

1. Introduction

The product design phases require thorough and reliable tests to verify and validate step by step. However, as modern systems grow in size and complexity, both in control software and in the physical plant, verification based on a new hardware plant is extremely time consuming such that the first few milestones in design are very difficult to achieve. Hardware-in-the-Loop technology (HIL) is a testing technique in which physical signals from a controller are connected to a test system that simulates the physical plant, tricking the controller into thinking it is in the assembled product. Test and design iteration take place as though the real-world system is being used. The researcher and engineers can easily run through thousands of possible scenarios to properly exercise the controller without the cost and time associated with actual physical tests. For the educational institutes, HIL based simulation will help visualize the plant characteristics, especially the dynamic systems, and provide safe experimental environment. Rapid Control Prototyping (RCP) systems, in a sense the opposite of HIL, utilize target hardware for control computation. The target hardware can be a dedicated computer or a microcontroller. Code generation tools generate target-specific C codes from block diagrams of the control algorithms. Executable programs made from generated C codes run on the target hardware in a real time. RCP is a major player in the embedded product development cycle nowadays, which helps validate the algorithm under test in a close-loop and real time manner. Before the host embedded hardware is ready, RCP provides the engineers with more time and options to fix the predictable and unpredictable issues, rending more mature and proven control solutions. For complex system development, the design phase including both RCP and HIL is common.

Researchers have been aware of the advantages of HIL simulation for more than three decades. However, due to limited calculation power, simulation of fast dynamic systems like switching converters has been challenging for long. Recent development in the processors and field-programmable devices make real time simulation possible for complex systems even for switching systems. References [1,2,3,4,5,6,7] investigated the HIL application with power converter in the loop, dealing with resolution and modeling issues. Reference [1] investigates the stability issue of the power HIL (PHIL) simulation, and presented the appropriate interface algorithm for power HIL system. Reference [2] developed a multi-physical model of the PV plant where electric-thermal model was validated using experimental data in realistic scenarios. References [4,5,8] investigates the stability issues that rise with power amplifier in the loop where software and topology based approach to stabilization were investigated respectively. References [6,7] presented FPGA based power converter emulator framework in which the performance of the system is evaluated.

Identification of switching or multi-physical system requires the single or broad frequency band signal injection and heavy computation, [9] proposed a power HIL system in which profiling of battery multi-states is performed by interacting with an electronic load for online system identification. References [8,10,11,12] applied HIL supported system identification to the distributed power systems. Reference [10] applied pseudo-random binary sequence (PRBS) as an external injection to the more electric aircraft (MEA) on-board power system, the discrete model of the primary converter is obtained for system impedance modification purposes. Reference [12] investigated the power quality issues, especially the immunity of electric components and equipment and the consequent impact on ac distribution systems.

References [13,14,15] focused on power interface modeling and trans-platform modeling method for wind energy conversion system. Reference [16] proposed a linear motor digital model with state space description while [17] implemented the induction machine HIL model with the equivalent circuit model, fast iteration speed is achieved in both research by implementing the plant model inside the FPGA. References [18,19] both investigated the fault diagnosis method in motor drive system while [19] adopted the numerical model obtained from finite element analysis for fast look-up.

With growing interests in large scale distributed power systems, hybrid simulation and verification were studied as in [20,21], where issues in real time coupling of geographically distributed power infrastructures are investigated. Reference [20], especially, presented the recent IEEE PES Task Force on Interfacing Techniques for Simulation Tools towards standardization of GDS as a concept. And [22,23] address the stability and communication delay issues in the control framework. Reference [24] proposed a HIL platform for simulating electric vehicle power train where PSIM simulation and c-block is applied as the intermediate verification process before implementation in Typhoon HIL simulator.

On education aspect, dynamic systems related courses interconnect the fundamental courses and senior design courses, in which modeling and basic control methods are introduced for different plants such as power converters, motors, and industrial processes. The hardware setup usually requires high voltage, high current, fluid, or even rotating mechanical bodies. The experimental preparation is time consuming even for observation purposes. The feedback control phase is also panic for the students; the system variables might be “out of control” if improper control schemes or parameters are used. An effective HIL system can tolerate try-and-error based study and help the students with a jump start in the verification phase [12].

In this paper, a low-cost Hardware-in-the-Loop-on-Chip (HILoC) platform for teaching and development dynamic systems, especially for digital control study and development, is developed. The on-chip solution is based on the state-of-the-art dual-core DSP technology in which the simulation engine calculates the sets of differential equations for the dynamic plant while the control engine performs the digital control task. The digital-to-analog converter and digital outputs are used to send the duty cycle and other system state variables to the oscilloscope for end-users’ visual feedback. Selected DC-DC converters are modeled and implemented in the simulation engine. Under the excitation generated by the control engine, different system dynamics are verified. Close-loop control is also demonstrated on the developed prototype, where both input voltage and load variations performance are tested. The rendered system is of low cost, which can shed light on the teaching of dynamic systems and fast prototype development phase of the product design.

2. Hardware-in-the-Loop System Analysis

A physical close-loop controlled system is presented in Figure 1a, where $G\left(s\right)$ is the physical plant, $H\left(s\right)$ is the sensors and conditioning circuit model, and $C\left(s\right)$ is the controller which can be implemented in either analog or digital form. A typical HIL based close-loop system is shown in Figure 1b. The plant is simulated by dedicated computation hardware, while the sensor and conditioning can be implemented in the digital simulator or digital controller. In a switching system such as the power electronic converter, to interpret the control input, the digital simulator should precisely detect the rising and falling edge of the PWM signals from the digital controller in order to calculate the control duty cycle or the frequency. Therefore, high performance interfacing peripherals and high frequency clock are required for the digital simulator.

Comparing to commercial HIL simulators with dedicated graphical compiler and real-time monitoring interface, the proposed digital simulator establishes the plant model with c-coded difference equation sets. In the case of a switching system, the power converter circuit for example, the average model is used. In authors’ early research, as in Figure 1b, the control output from the digital controller d was the averaged PWM signal, generated from the on-chip DAC. The output signal y from the simulated plant is also from the on-chip DAC in the digital simulator. An early version of the hardware prototype is shown in Figure 2, where three dsPIC controllers are used with the third one managing the human machine interface.

3. HIL-Based Teaching and Learning Model

For the HIL based teaching and learning, the students are required to work through seven steps, as listed below, which are graphically shown in Figure 3. Comparing to the conventional control oriented design and teaching without Steps 4 and 5, students or engineers with trouble in hardware debugging and testing could spend a lot of time to find the loop-holes in the design by starting from Step 2 again. With Steps 4 and 5, the errors in modeling and control can be fixed before going to the hardware debugging phase, which is sometimes time consuming and irreversible.

• System design, including the circuit analysis and parameter calculation
• Modeling
• Continuous control system design
• Discretization
• HIL simulation and verification
• Hardware design
• Hardware debugging and testing

In the commercial HIL system, Step 4 is done automatically by the compiler for graphical interface, while, in the proposed low-cost HILoC system, this step is conducted by the instructor and the student respectively.

The detailed model for the HIL based learning model is shown in Figure 4. The proposed HIL system featured with a dual-core DSC with support from auxiliary micro-controller for man-machine interface. The DSC CPU A, as the simulation engine, dedicates to circuit simulation with small simulation steps. The system excitation input or digital control routine is implemented in DSC CPU B, which is used as the control engine. Inter-processor communication is used to interchange variables between two CPUs. The system variables and control variables is isolated and conditioned through the signal conditioning circuit and sent to the oscilloscope for observation and debugging purpose.

Considering the capability of the students, when the proposed HILoC is used for teaching, the sets of plant models are developed by the course instructor, which is preloaded into the simulation engine (CPU A). After finishing Step 3, the students discretize the controller, which is obtained previous step, and load the code into the control engine (CPU B). With no need to understand how the data exchange and plant modeling is done, the students only need to code the discretized controller into the designated sub-function and include it as the input file in the project.

Desired state variable and control variable can be captured in realtime on the oscilloscope screen for students’ visual feedback. The system performance indices such as the output overshot, setting times, and steady state error can be observed for control design iteration.

4. Dynamic System Modeling and Iteration

4.1. HIL Model of the Switching Systems

In this section, the plant modeling and iteration methods are presented. As stated in Section 3, due to limited hardware resource, switching state detection is not used in the proposed system. The average model is used instead. A buck converter, as shown in Figure 5, is chosen as the example to demonstrate the modeling and iteration process.

$[i_{\mathrm{L}},v_{\mathrm{C}}]$ are chosen as the state variables. When the switch T is turned on, the differential equation can be found using Equations (1) and (2)

$$\begin{array}{ccc}\hfill V_{in}& =& i_L(r_{\mathrm{dson}}+r_L)+L\frac{\mathrm{d}{i}_L}{\mathrm{d}t}+v_C\hfill \end{array}$$

(1)

$$\begin{array}{ccc}\hfill i_L& =& C\frac{\mathrm{d}{v}_C}{\mathrm{d}t}+\frac{v_C}{R}\hfill \end{array}$$

(2)

while, for the switch off state, the system equation can be obtained by Equations (3) and (4)

$$\begin{array}{ccc}\hfill 0& =& i_L{r}_L+L\frac{\mathrm{d}{i}_L}{\mathrm{d}t}+v_C\hfill \end{array}$$

(3)

$$\begin{array}{ccc}\hfill i_L& =& C\frac{\mathrm{d}{v}_C}{\mathrm{d}t}+\frac{v_C}{R}\hfill \end{array}$$

(4)

To show the steady state load effect, the MOSFET switch on-state resistor $r_{\mathrm{dson}}$ and the inductor parasitic resistance $r_L$ are included in the equation. Applying the state-space averaging, the state equation including the switching function $d\left(t\right)$ can be obtained as in Equations (5) and (6).

$$\begin{array}{ccc}\hfill L\frac{\mathrm{d}{i}_L}{\mathrm{d}t}& =& d{V}_{in}-v_C-i_L(r_L+d{r}_{\mathrm{dson}})\hfill \end{array}$$

(5)

$$\begin{array}{ccc}\hfill C\frac{\mathrm{d}{v}_C}{\mathrm{d}t}& =& i_L-\frac{v_C}{R}\hfill \end{array}$$

(6)

Discretization is applied to the plant equation, which runs in the simulation engine at high update rate $T_s$. The accelerated iteration method is proposed in this HILoC system. As indicated in iteration equation, in the kth iteration, Equation (7) is calculated first, using the inductor current and capacitor voltage in the previous sampling period. Once the updated inductor current $i_L\left[k\right]$ is obtained, it is substituted into the second half of the iteration, which is shown in Equation (8). The cross-update in one iteration results in faster variable convergence and improves the efficiency of the simulation.

$$\begin{array}{ccc}\hfill i_L\left[k\right]& =& i_L[k-1]+\frac{T_s}{L}\left[d\left[k\right]V_{in}-v_C[k-1]-i_L[k-1](r_L+d\left[k\right]r_{\mathrm{dson}})\right]\hfill \end{array}$$

(7)

$$\begin{array}{ccc}\hfill v_C\left[k\right]& =& v_C[k-1]+\frac{T_s}{C}\left[i_L\left[k\right]-\frac{v_C[k-1]}{R}\right]\hfill \end{array}$$

(8)

Similarly, the boost converter’s continuous and discrete model can be obtained as in Equations (9) to (12)

$$\begin{array}{ccc}\hfill L\frac{\mathrm{d}{i}_L}{\mathrm{d}t}& =& V_{in}-(1-d)v_C-i_L(r_L+d{r}_{\mathrm{dson}})\hfill \end{array}$$

(9)

$$\begin{array}{ccc}\hfill C\frac{\mathrm{d}{v}_C}{\mathrm{d}t}& =& (1-d)i_L-\frac{v_C}{R}\hfill \end{array}$$

(10)

$$\begin{array}{ccc}\hfill i_L\left[k\right]& =& i_L[k-1]+\frac{T_s}{L}\left[V_{in}-(1-d)v_C[k-1]-i_L[k-1](r_L+d{r}_{\mathrm{dson}})\right]\hfill \end{array}$$

(11)

$$\begin{array}{ccc}\hfill v_C\left[k\right]& =& v_C[k-1]+\frac{T_s}{C}\left[(1-d)i_L\left[k\right]-\frac{v_C[k-1]}{R})\right]\hfill \end{array}$$

(12)

4.2. HIL Model of Typical Process Systems

Basic process control systems are designed to meet a wide range of industrial challenges related to system operation and monitoring. A number of process control system can be modeled with continuous states and event-based inputs. A simple example of a process system is shown in Figure 6. In this classical two-container system, $Q_i$ is the pipeline flow rate, $S_i$ is the value, $R_i$ is the liquid resistance of the value, $A_i$ is the cross-section area of the container, and $h_i$ is the liquid level, where $i=1,2,3$.

Without considering the time delay of the pipeline in and out of the two tanks, Equations (13) and (14) can be obtained by applying Bernoulli’s principle.

$$\begin{array}{ccc}\hfill Q_1-Q_2& =& A_1\frac{d{h}_1}{dt}\hfill \end{array}$$

(13)

$$\begin{array}{ccc}\hfill Q_2-Q_3& =& A_2\frac{d{h}_2}{dt}\hfill \\ \hfill \mathrm{where}& & \\ \hfill Q_2& =& \frac{s_1}{R_1}\sqrt[]{2g{h}_1}\hfill \\ \hfill Q_3& =& \frac{s_2}{R_2}\sqrt[]{2g{h}_2}\hfill \\ \hfill R_1,R_2& \in & [1,+\propto )\hfill \end{array}$$

(14)

By further applying discretization with the accelerated iteration method, the iteration difference equation can be implemented in the processor, as shown in Equations (15) and (16)

$$\begin{array}{ccc}\hfill h_1\left[k\right]& =& h_1[k-1]+\frac{T}{A_1}(Q_1-\frac{s_1}{R_1}\sqrt[]{2g{h}_1[k-1]})\hfill \end{array}$$

(15)

$$\begin{array}{ccc}\hfill h_2\left[k\right]& =& h_2[k-1]+\frac{T}{A_2}(\frac{s_1}{R_1}\sqrt[]{2g{h}_1\left[k\right]}-\frac{s_2}{R_2}\sqrt[]{2g{h}_2[k-1]})\hfill \end{array}$$

(16)

4.3. Discrete Model of the Digital Controller

In the control engine, the control routine is executed at a slower rate than that of the simulation engine, which is $T_c$. In most design cases, single feedback loop is implemented. In this paper, a type-2 PI controller is used to demonstrate the feasibility of the HILoC design. By applying the bilinear transformation to Equation (17), the discretized controller iteration expression (Equation (18)) can be obtained.

$$\begin{array}{ccc}\hfill C\left(s\right)& =& \frac{k(1+\frac{s}{{\omega }_z})}{s(1+\frac{s}{{\omega }_p})}\hfill \end{array}$$

(17)

$$\begin{array}{ccc}\hfill u\left[k\right]& =& Au[k-1]+Bu[k-2]+Ce\left[k\right]\hfill \\ \hfill & & +De[k-1]+Ee[k-2]\hfill \\ \hfill A& =& \frac{4}{{\omega }_p{T}_c+2}\hfill \\ \hfill B& =& \frac{{\omega }_p{T}_c-2}{{\omega }_p{T}_c+2}\hfill \\ \hfill C& =& \frac{{\omega }_{p}k{T}_c({\omega }_z{T}_c+2)}{2{\omega }_z({\omega }_p{T}_c+2)}\hfill \\ \hfill D& =& \frac{{\omega }_{p}k{T}_c^2}{{\omega }_p{T}_c+2}\hfill \\ \hfill E& =& \frac{{\omega }_{p}k{T}_c(w_z{T}_c-2)}{2{\omega }_z({\omega }_p{T}_c+2)}\hfill \end{array}$$

(18)

5. Computation Routine and Data Exchange

The iteration process introduces sampling delay. Therefore, to emulate the plant effectively, the simulation steps is chosen to be much smaller than the equivalent system time constant. In the proposed system, the update rate of the simulated plant is chosen as $T_s$. For the digital power electronic systems with limited switching frequency, the control routine serves at or below the switching frequency, the updating period of which is defined as $T_c$.

As the simulation and control engine are both inside one DSC, the state and control variable exchange between two engines does not require interfacing circuitry or analog-to-digital peripherals. Inter-processor communication (IPC) protocol is used to send and fetch the variables between two CPUs. The proposed timing sequence of the data exchange is indicated in Figure 7. High resolution timers are used as the time-base to generate interrupt service routines (ISR) for both simulation and control engine. The plant model is iterated inside the simulation engine’s ISR running at a high refreshing rate of 5 $\mathsf{\mu }$s. Therefore, the state variable is considered realtime for both observation and the control purposes. The simulation and data exchange take place as per described in the chart. The digital control service is scheduled for every 50 $\mathsf{\mu }$s, which is divided into four phases:

• Request state variables
• Calculate control routine
• Send control variables
• Idle time

At the beginning of the digital control service, the control engine initiates the state variable request through IPC. After the variables are obtained from the IPC buffer, digital control routine computation is performed to generate the control variable, the duty cycle, which is immediately sent to IPC buffer. The simulation engine picks up the control variable from IPC buffer at the beginning of the 5 $\mathsf{\mu }$s interrupt routine. Therefore, the control action is equivalent to the instantaneous duty cycle update mode in most of the commercial DSCs. Due to the digital nature of the simulated plant, the HILoC introduce an average delay time of 2.5 $\mathsf{\mu }$s to the system.

6. Experimental Verification

The proposed HIL system was implemented with Texas Instrument dual-core DSC TMS320F28379D (Texas Instruments, Dallas, TX, USA) as the computation hardware and Atmega328p (Microchip Technology, Chandler, AZ, USA) for system house-keeping. The prototype is shown in Figure 8, in which two analog and two PWM outputs are allocated for oscilloscope based observation. The specifications are listed in

Table 1. HILoC system specifications.

Specification	Description
Processor	TMS320F28379D, ATMEGA328
Capacity	200 MHz, 800 MIPS (dual C28xCPU, dual CLA)
Digital Output	2 isolated channels, $V_{\mathrm{HL}}=5$ V, $I_{\mathrm{o},\mathrm{MAX}}=50$ mA
Analog Output	2 isolated channels, 0–5 V, $\Delta V_{\mathrm{out}}=1.2$ mV/bit
Simulation Step	$T_s=5\mathsf{\mu }$s
Control period	$T_c=50\mathsf{\mu }$s

.

To demonstrate the HILoC capability of simulation fast dynamic systems, two basic dc-dc topologies, the buck and boost converters, were modeled for system verification. Eight test session were proposed for both learning and design purposes, including the open-loop experiment for system dynamic behavior observation and close-loop design experiment.

Load disturbances, input disturbances and duty cycle perturbation are the input for three important transfer functions in modern switching power converter design, which are the output impedance, audio susceptibility, and the control to output transfer function. The step changes are implemented in the control engine while the circuit model is implemented in the simulation engine.

Figure 9 shows the simulation results for the open loop characteristics of a buck converter. As listed in

Table 2. Test condition.

Topology	$\mathit{Vin}$	L	C	R	d
Buck	20 V	1 mH	220 $\mathsf{\mu }$F	1/2	0.5
Buck	16/24 V	1 mH	220 $\mathsf{\mu }$F	2	0.5
Buck	30 V	1 mH	220 $\mathsf{\mu }$F	4	0.3/0.5
Boost	10 V	1 mH	220 $\mathsf{\mu }$F	10/20	0.5
Boost	8/12 V	1 mH	220 $\mathsf{\mu }$F	10	0.5
Boost	5 V	1 mH	220 $\mathsf{\mu }$F	10	0.4/0.6
Buck close-loop	24/16	1 mH	220 $\mathsf{\mu }$F	1	-
Buck close-loop	20	1 mH	220 $\mathsf{\mu }$F	1/2	-

, the load step disturbance, input voltage disturbance, and the duty cycle disturbance are verified with the HILoC hardware. Hardware simulation of the open loop characteristics of a boost converter is shown in Figure 10.

Figure 11 shows the close-loop interaction between the simulation engine and the control engine in the proposed HILoC system. The proposed HILoC system simulates the close-loop control under the load disturbance and the input voltage disturbance injection. As can be observed, the control engine can receive the voltage feedback from the simulation engine and perform PI control to the simulated plant. The analog and digital outputs of the HILoC will enable real-time close-loop performance evaluation and debugging. As mentioned above, the power converter under hardware simulation is implemented with the average model. The proposed HILoC still generates equivalent PWM signals to illustrate the duty cycle variation under the regulation period. Taking Figure 11b as an example, when the system is undergoing a step load increase, the system output drops due to the step discharge of the capacitor and the voltage drop along the feedforward path. One can easily observe from the test waveform that the control duty cycle increases slightly under close-loop control to compensate the voltage drop.

With the proposed HILoC, the students or the engineers can easily modify the control parameter to observe the system performance. Figure 12 shows the hardware simulation results of voltage controlled buck converter with different $k_p$ and $k_i$ parameters in a traditional PI controller. The regulation performance is clearly demonstrated using the proposed HILoC system.

A comparison was conducted with the commercial HIL system, the Typhoon. The system was tested under the load step dynamic situation. As can be observed in Figure 13, the two system showed very close dynamic performance, which indicates the effectiveness of the proposed HILoC system.

A dual-tank process system with all continuous states is also verified with the proposed HILoC. The system parameter is scaled such that the simulation can be accomplished with in 100 s. From the beginning, all the valves are closed; the liquid is pumped into tank 1 continuously. The liquid fills tank 1 by 10 s and keeps running over. The operator opens $S_1$ at 15 s to release the liquid into tank 2. Since $S_2$ remains closed, tank 2 is filled and the liquid keeps running over tank 2. The operator opens $S_2$ at 30 s to release the liquid from tank 2. As expected, the liquid level of tank 2 drops, and the system eventually goes to the steady state. At 80 s, the system input $Q_1$ is cut-off, all the tanks are drained. The simulation engine of the proposed HILoC simulates the dual tank plant, and the control engine launches different events, including $Q_1$, $S_1$, and $S_2$. The hardware simulation results is indicated in Figure 14a, which matches the computer simulation results in Figure 14b.

7. Conclusions

This paper proposes a low-cost Hardware-in-the-Loop on Chip (HILoC) platform for dynamic systems, especially for teaching and designing of digital power converters. The dual-core DSC solution is proposed. Critical issues of modeling implementation, inter-processor information exchange, and fast iteration are presented in detail in this paper. A full demonstration using the HILoC prototype is carried out for the buck and boost topology as well as a dual-tank process control system. The proposed low-cost HILoC system can be easily applied to the engineering teaching as well as fast prototype development phase of product design.