Runtime Analysis of Area-Efficient Uniform RO-PUF for Uniqueness and Reliability Balancing
Abstract
:1. Introduction
2. The Proposed RO-PUF
2.1. RO-PUF Circuit
- High RO utilization: a higher response bit can be achieved, as CRP generation is independent.
- Routing equality: the distance between each RO and the respective counter is equal. Hence, there will be no locking phenomena or jitter noise.
2.2. Ring Oscillator Realization
2.3. RO-PUF Placement
2.4. RO Patterns
2.5. Routing Density
2.6. RO Runtimes
3. Experimental Setup
3.1. Uniformizing Routing Hotspots
- Rearrange the logic fan-out of input pins. Logic gates corresponding to the Clock and Enable inside the controller are rearranged.
- Rearrange the logic fan-in of output pins. Logic gates corresponding to display responses inside CRP Generation are rearranged.
- Distribute logic fan-in of ROs uniformly. All logic gates inside the Controller connected directly to ROs are distributed uniformly in the entire region.
- Distribute logic fan-out of counters uniformly. All logic gates in the CRP Generation region connected directly to counters are rearranged to be uniformly distributed in the entire region.
- Rearrange other logics in the CRP Generation region. Several logics inside this region do not have to be uniformly distributed. However, they are relocated based on the routing hotspots in the respective ROs.
3.2. LUT Configuration
3.3. Data Acquisition
4. Performance Metrics
4.1. Estimating the Pulse Count
4.2. Uniqueness and Reliability
4.3. Uniformity and Bit Aliasing
5. Performance Analysis
5.1. Statistical Properties
5.2. Runtimes Analysis
5.3. CRP and Metric Comparisons
6. Conclusions
Author Contributions
Funding
Conflicts of Interest
References
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FPGA Technology | Intel Cyclone V (28 nm) |
---|---|
Board Chip no. | Four DE1-SoC (5CSEMA5F31C6), six DE0-Nano (5CSEMA4U23C6) |
RO stage | 5, 11, 20 (e.g., RO11-6 denote RO no. 6 of an 11-stage RO) |
RO runtimes | 1–8 ms (RO5), 2–16 ms (RO11), 4–32 ms (RO20) |
RO5 | RO11 | RO20 | ||||||
---|---|---|---|---|---|---|---|---|
Pattern-1 | Pattern-2 | Pattern-3 | Pattern-1 | Pattern-2 | Pattern-3 | Pattern-1 | Pattern-2 | |
DE1-SoC | ||||||||
Routing hotspots (%) | 21–42 | 35–57 | 28–50 | 35–50 | 42–64 | 35–57 | 42–64 | 35–57 |
Average (%) | 30.6 | 45.4 | 36.5 | 46.2 | 51 | 43.7 | 52.6 | 44.6 |
DE0-Nano | ||||||||
Routing hotspots (%) | 7–22 | 8–28 | 11–21 | 21–35 | 21–35 | 25–37 | 19–42 | 19–42 |
Average (%) | 16.4 | 18.7 | 15.1 | 27.3 | 25.1 | 29.3 | 26.6 | 28.7 |
Pattern/Stage | Inputs Configuration | ||
---|---|---|---|
DE1-SoC | DE0-Nano | ||
Pattern-1 | RO5 | DF-DDFF | FB-DCFF |
RO11 | DF-DDFFFFFFFF | FB-DCFFFFFFFE | |
RO20 | FD-DDFFFFFFFFFFDFFDFFD | FD-DCFFFFFFFFFFDFFDFFD | |
Pattern-2 | RO5 | FE-FFFD | FE-FFFC |
RO11 | FE-FFFFFFFFFD | FE-EFFFFFFFFC | |
RO20 | FD-FDFFDFFDFFFFFFFFFFD | FD-FDFFDFFDFFFFFFFFFFC | |
Pattern-3 | RO5 | FC-FFFF | FC-FFFF |
RO11 | DF-FFFFFFFFDF | FB-FFFFFFFFDF |
Uniqueness (%) | Reliability (%) | Uniformity (%) | Bit aliasing (%) | |||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|
RO5 | RO11 | RO20 | RO5 | RO11 | RO20 | RO5 | RO11 | RO20 | RO5 | RO11 | RO20 | |
Pattern-1 | 40.52 | 46.51 | 47.31 | 99.20 | 97.96 | 98.80 | 60.04 | 63.78 | 61.24 | 59.78 | 63.69 | 61.16 |
Pattern-2 | 44.46 | 47.33 | 47.48 | 97.96 | 98.09 | 99.16 | 59.69 | 60.62 | 62.89 | 59.65 | 60.71 | 62.98 |
Pattern-3 | 50.98 | 47.69 | - | 98.18 | 98.27 | - | 56.49 | 58.40 | - | 59.44 | 58.80 | - |
Author | No. of CRPs | CRP Enhance/Location |
---|---|---|
Suh et al. [3] | n/8 | no/inside chip |
Maiti et.al. [31] | n − 1 | no/inside chip |
Merli et.al. [38] | n/2 | no/inside chip |
Yin et.al. [39] | log2 n! | no/inside chip |
Our set-up | n! /2(n − 2)! | yes/inside or outside |
Maiti et.al. [22] | 2n − n − 1 | yes/outside chip |
Delavar et.al. [23] | 2n − 1 | yes/outside chip |
Uniqueness (%) | Reliability (%) | Uniformity (%) | Bit-Aliasing (%) | Platform | |
---|---|---|---|---|---|
Suh et al. [3], 2007 | 46.15 | 99.52 | - | - | Xilinx (90 nm) |
Maiti et al. [31], 2009 | 35.91–45.90 | - | - | - | Xilinx (90 nm) |
Merli et al. [5], 2010 | 43.40–48.51 | 99.20, 98.28 | - | - | Xilinx (90 nm) |
Xin et al. [46], 2011 | 32, 41 | 99.29 | - | - | Xilinx (90 nm) |
Maiti et al. [22], 2012 | 49.99–50.07 | ±92 *, ±70 * (45 °C) | 50.02, 49.4 | 50.02, 49.4 | Xilinx (90 nm) |
Feiten et al. [14], 2013 | 6.68 *–37.03 * | 99.41 *–82.5 * | 50.00 *, 62.07 * | - | Altera (65 nm) |
Sahoo et al. [45], 2013 | 47.57 | 90.70 *** | 47 | 14.95 | Altera (65 nm) |
Kodytek et al. [7], 2016 | 48.42–48.74 | 98.22, 97.55 | - | - | Xilinx (90 nm) |
Delavar et al. [23], 2016 | 49.81 | 96.07 | - | - | Xilinx (90 nm) |
Chauhan et al. [40], 2019 | 49.9 | 97.85–99.80 | - | - | Xilinx (28 nm) |
Deng et al. [41], 2020 | 49.95 | 91.4–99.13 * | 49.61 | - | Xilinx (28 nm) |
This work ** | 47.48 | 99.16 | 62.89 | 62.98 | Altera (28 nm) |
Ideal value | 50% | 100% | 50% | 50% |
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Zulfikar, Z.; Soin, N.; Wan Muhamad Hatta, S.F.; Abu Talip, M.S. Runtime Analysis of Area-Efficient Uniform RO-PUF for Uniqueness and Reliability Balancing. Electronics 2021, 10, 2504. https://doi.org/10.3390/electronics10202504
Zulfikar Z, Soin N, Wan Muhamad Hatta SF, Abu Talip MS. Runtime Analysis of Area-Efficient Uniform RO-PUF for Uniqueness and Reliability Balancing. Electronics. 2021; 10(20):2504. https://doi.org/10.3390/electronics10202504
Chicago/Turabian StyleZulfikar, Zulfikar, Norhayati Soin, Sharifah Fatmadiana Wan Muhamad Hatta, and Mohamad Sofian Abu Talip. 2021. "Runtime Analysis of Area-Efficient Uniform RO-PUF for Uniqueness and Reliability Balancing" Electronics 10, no. 20: 2504. https://doi.org/10.3390/electronics10202504
APA StyleZulfikar, Z., Soin, N., Wan Muhamad Hatta, S. F., & Abu Talip, M. S. (2021). Runtime Analysis of Area-Efficient Uniform RO-PUF for Uniqueness and Reliability Balancing. Electronics, 10(20), 2504. https://doi.org/10.3390/electronics10202504