The uniqueness, reliability, uniformity, and bit aliasing of ROs, to compare the performances, were presented in
Section 4. The variations of performance among patterns were analyzed by assessing some statistical parameters of the pulses. The range of runtimes was calculated using Equations (1)–(6). The comparison of CRP models and our set-up is presented at the end of this section.
5.1. Statistical Properties
The chips of the DE1-SoC boards were numbered 1 to 4, and the chips of the DE0-Nano boards were numbered 5 to 10.
Figure 10 shows the average frequencies of RO5, RO11, and RO20 in all chips for all patterns. As shown in the figures, chip-7 was the slowest, and chip-5 was the fastest. The differences in frequencies among patterns were due to various input configurations, as listed in
Table 3.
In the RO5 realization, as shown in
Figure 10a, the average frequency varied from around 345 MHz to 478 MHz. The realization of RO5 using Pattern-3 produced more pulses than others, especially in DE0-Nano boards, which is reflected by the input configuration of FC-FFFF, as listed in
Table 3.
Figure 10b shows the average frequency of RO11. In DE1-SoC, based on the configuration of LUTs, as listed in
Table 3, the average frequency of ROs using Pattern-2 should have been higher than that of those using Pattern-3. However, Pattern-3 produced a higher average frequency because routing hotspots of ROs using this pattern (43.7%) were lower than those of Pattern-2 (51%), as listed in
Table 2.
Figure 10c shows the average frequencies of Pattern-1 and Pattern-2 in the RO20 realizations. The average frequency of RO20 varied from 100 to 120 MHz, about half of RO11’s range. Thus, there were slight frequency differences between the two patterns for all chips.
Figure 11 shows the frequency ranges and standard deviations of all chips. For RO5, there existed significant differences in frequency ranges among patterns on DE0-Nano. The differences in frequency were due to average routing hotspots and input LUTs, as listed in
Table 2 and
Table 3. The plots explained why Pattern-1 resulted in the least uniqueness, as listed in
Table 4: high standard deviation and the high frequency ranges of some chips, as shown in
Figure 11a. For RO11, there were minor differences in routing hotspots among patterns, as listed in
Table 2. Therefore, the frequency ranges and standard deviations among patterns were similar, as shown in
Figure 11b, which explains the slight uniqueness difference, as listed in
Table 4. In RO20, the slight differences in frequency range and standard deviation between patterns, as shown in
Figure 11c, explains the minor performance differences, as listed in
Table 4.
5.2. Runtimes Analysis
Merli et al. stated that the uniqueness was becoming stagnant after 204.8 µs [
5]. This study found a similar behavior, where there were no significant changes in uniqueness and other metrics upon increasing the runtime. We analyzed the runtimes of RO11 and RO20 implemented using Pattern-3 and Pattern-2, respectively. The selection was made due to closer uniqueness to the ideal than other patterns, as shown in
Table 4.
Whenever two or more ROs generate equal pulses, bit flipping happens when the ROs are run in different environmental conditions. For use as a PUF, all ROs should produce different pulses that are scattered from each other. In previous work [
36,
37], any RO pairs with a frequency difference less than the set threshold have been ignored, reducing the number of response bits. Instead of ignoring pairs, in this study we increased the runtime until RO produced a minimum pulse difference
s. The runtime estimates were based on the minimum frequency differences among ROs. The minimum frequency differences of RO11 and RO20 in this work were 62.55 and 36.81 kHz, respectively. Hence, for s pulses, the shortest runtimes of RO11 and RO20 were (
s/62.55) ms and (
s/36.81) ms. Upon that realization,
s was chosen to be significantly higher. For instance, with
s = 100, the shortest runtimes of RO11 and RO20 were 1.598 and 2.717 ms, respectively.
Figure 12 shows the runtime predictions of RO11 (Pattern-3) and RO20 (Pattern-2) calculated using Equations (1)–(6). For RO11, as shown in
Figure 12a, we suggest running ROs for
t_H1 = 1.598 to 4.30 ms (Δ
P_H1 = 2.77%);
t_L2 = 6.12 ms (Δ
P_L2 = 3.53%) to
t_H2 = 8.61 ms (Δ
P_H2 = 5.54%);
t_L3 = 12.24 ms (Δ
P_L3 = 7.06%) to
t_H3 = 12.91 ms (Δ
P_H3 = 8.31%). Meanwhile, for RO20, as shown in
Figure 12b, this work suggests running ROs for about
t_H1 = 2.717 to 8.37 ms (Δ
P_H1 = 3.09%);
t_L2 = 10.97 ms (Δ
P_L2 = 3.81%) to
t_H2 = 16.74 ms (Δ
P_H2 = 6.19%);
t_L3 = 21.93 ms (Δ
P_L3 = 7.62%) to
t_H3 = 25.10 ms (Δ
P_H3 = 9.28%). Whenever ROs are activated at extreme temperatures (0 °C or 85 °C), the maximum pulses change with respect to counter capacity at a specific runtime is Δ
P.
5.3. CRP and Metric Comparisons
Table 5 shows the comparisons of the number of CRPs to the number of ROs. Our set-up can generate more responses due to more CRPs compared to other works, without a CRP enhancement technique (CRP inside an FPGA chip). In comparison, for
n = 16 ROs, the CRPs of this work numbered 120, which is by far the highest compared to other models. Hence, our set-up requires a lesser area for realizing Ros, which allows more space for primary circuits. The CRPs of our set-up may also be realized outside the FPGA chip.
Furthermore, we compared the performances of the proposed uniform RO-PUF with other works in terms of uniqueness, reliability, uniformity, and bit aliasing. Most of the proposed RO-PUF that can be found in the literature utilize Xilinx FPGA, but some work is realized on Altera FPGA.
Table 6 lists the metrics of the published works compared to those from this work. The authors improved RO quality in several previously published works using different techniques [
5,
7,
14,
22]. Most of the previously proposed works are inapplicable due to massive area usage for creating ROs, CRP generation, or the controlling circuit. We found that the ideas proposed by Maiti et al. [
22] and Delavar et al. [
23] are applicable due to CRP enhancing techniques. Both designs are better than this work in terms of uniqueness, but have lesser reliability scores, as listed in
Table 6. Moreover, upon realization, Delavar et al. [
23] compared the design quality using five chips only, implying that the ideal uniqueness is higher than 50% [
13].
Chauhan et al. [
40] proposed a different frequency characterization to improve reliability based on Delavar et al.’s idea [
23]. However, since no expanded CRP techniques were used during response generation, it required a considerable area. Recently, Deng et al. proposed modifying the available configurable ring oscillator (C-RO) using hybrid logic gates [
41]. The idea was realized on a 28 nm Xilinx chip with the help of 90 nm Spartan 3 for extracting reliability upon voltage variation. Upon comparing RO-PUFs, this study did not classify or identify the aging impact that may shift the frequency [
42,
43,
44]. For instance, high temperatures set up and its duration for extracting data from chips may degrade the frequency.
On a similar FPGA platform (Altera, San Jose, United States), in 2012, Bernard et al. implemented the ROs using Cyclone II and Cyclone III [
20], making them the first in the literature to realize ROs as PUF on Altera. However, there were no metrics mentioned in the paper. Later then, Sahoo et al. [
45] also realized the RO-PUF on Cyclone III. However, the reliability was measured at room temperature, and the design resulted in the worst bit aliasing. Finally, Feiten et al. [
14] realized the RO-PUF using Cyclone IV. They described in detail the realization of Altera FPGA, but they were unable to improve the uniqueness. Meanwhile, this study was the first to realize RO using Cyclone V (28 nm). We found that our method is the best among those who realized their designs on Altera devices.
For implementation in Cyclone V, we required 354 of the total available 15,880 ALMs (2% using DE0-Nano) or 30,070 ALMs (1% using DE1-SoC). The design also utilized 270 registers. However, most of the resources were used by control circuits. Upon realization of a fixed runtime, resource usage may be reduced. This work requires 10 × 20 ALMs to create RO20 or 10 × 11 ALMs to create RO11 and a number of (200 ALMs + 200 registers) to realize counters. The design would approximately draw 315 mW (DE0-Nano) or 411 mW (DE1-SoC) of static power, estimated using the Power Analyzer Tool (available in Quartus).