Load-Independent Voltage Balancing of Multi-Level Flying Capacitor Converters in Quasi-2-Level Operation

Abstract

Quasi-2-level (Q2L) operation of multi-level bridge-legs, especially of flying-capacitor converters (FCC), is an interesting option for realizing single-cell power conversion in applications whose system voltages exceed the ratings of available power semiconductors. To ensure equal voltage sharing among a Q2L-FCC’s switches, the voltages of a Q2L-FCC’s minimized flying capacitors (FCs) must always be balanced. Thus, we propose a concept for load-independent FC voltage balancing: For non-zero load current, we use a model predictive control (MPC) approach to identify the commutation sequence of the individual switches within a Q2L transition that minimizes the FC or cell voltage errors. In case of zero load current, we employ a novel MPC-based approach using cell multiple switching (CMS), i.e., the insertion of additional zero-current commutations within a Q2L transition, to exchange charge between the FCs via the charging currents of the switches’ parasitic capacitances. Experiments with a 5-level FCC half-bridge demonstrator confirm the validity of the derived models and verify the performance of the proposed load-independent balancing concept.

1. Introduction

Stringent efficiency requirements for the supply of high-power DC applications such as hyperscale data centers [1,2,3,4] and high-power electric vehicle (EV) charging stations [5,6,7,8] drive the interest in direct power electronic interfaces between a medium-voltage (MV) AC grid and a low-voltage (LV) DC bus. Such flexible isolation and voltage-scaling MVAC-LVDC interfaces are commonly referred to as solid-state transformers (SSTs) [2,3,9,10]. Given the typical MV grid voltage levels of 6.6 kV rms line-to-line (3.8 kV line-to-neutral) in Europe [2] and 4.16 kV rms line-to-line (2.4 kV line-to-neutral) in the USA [3,9], clearly either latest technology wide-bandgap (WBG) power semiconductors with extreme blocking voltage ratings of up to 15 kV [11,12,13,14] or, alternatively, multi-cell topologies employing production-grade LV power semiconductors (e.g., 1.2 kV–3.3 kV SiC MOSFETs or SI IGBTs) are necessary.

Even though multi-cell SSTs can achieve a high conversion performance by configuring the cells in an input-series/output-parallel (ISOP) fashion, they are highly complex due to the typically high number of sub-units, the required communication system, and ultimately, the high component count. Therefore, recently the research focus has shifted to single-cell SST realizations, i.e., 2- or 3-level topologies enabled by new 6.5 kV–15 kV SiC MOSFETs or IGBTs [2,15]. However, the availability of these HV transistors is limited (mainly engineering samples), and prices remain high despite strong activity towards commercialization and manufacturing [16].

Alternatively, bridge-legs for single-cell SSTs can be realized with a series connection of semiconductors [17,18], super-cascode configurations [19,20], or multi-level converter structures, i.e., modular multi-level converter (MMC) [21,22,23,24,25] and flying capacitor converter (FCC) structures [18,26,27,28]. However, due to unavoidable differences (manufacturing tolerances etc.) of the semiconductor and gate driver properties, direct series connections of semiconductors require additional circuitry, i.e., (lossy) snubbers, to ensure equal transient and stationary blocking voltage sharing. The super-cascode approach [19,20] employs a series connection of several HV SiC (normally-on) JFETs and a LV Si (normally-off) MOSFET for initiating turn-on and turn-off. Similarly, it requires a passive network that is adapted to the parasitic capacitances of the SiC JFETs to ensure proper operation with balanced blocking voltages. Furthermore, only a few suppliers of MV SiC JFETs exist. The main drawbacks of an MMC topology are the high total chip area usage, the high number of gate drivers, and the presence of branch inductors. Finally, an FCC half-bridge (HB) features several advantages such as reduced switching losses (snubberless, on the contrary to direct series connection) and robust voltage balancing without additional chip area and gate drivers (compared to an MMC HB). However, conventional multi-level operation of MMC and FCC bridge-legs, while resulting in low harmonic content of the generated output voltage, requires a relatively large total volume of the flying capacitors (FCs).

The large capacitor volumes required for the MMC and FCC can be reduced by employing a quasi-2-level modulation scheme (Q2L-MMC, Q2L-FCC). With Q2L modulation, the intermediate voltage levels are only used during the switching transitions. The bridge-leg’s output voltage thus transitions between the two DC voltage levels (positive and negative) in a staggered fashion [22,23,24,28,29,30,31,32,33,34]. Note that these staggered transitions of the the Q2L-MMC and Q2L-FCC topologies feature lower average $\mathrm{d}v/\mathrm{d}t$ compared to the (MV) 2-level converters, which is beneficial for the design of EMI filters and magnetics such as medium-frequency transformers, and lowers the stress of the electric insulation [29,35,36,37,38].

However, whereas in conventional multi-level operation of a FCC bridge-leg, balancing of the FC voltages occurs naturally [39], balancing is not automatically ensured in Q2L operation. Recently, the evaluation of Q2L modulation, including the selection of number of levels, dimensioning of FCs, switching frequency and modulation index have been considered in [33]. In [31], methods of FC voltage balancing through adaptation of delay times without using redundant switching sequences are presented for a Q2L-operated 5-level FCC (Q2L-5L-FCC). In this context, switching sequence refers to the order in which the individual FC cells are commutated during a single Q2L transition. The authors of [32] present a balancing algorithm incorporating all switching sequences based on FC voltage errors by prioritizing the FC with the largest voltage error. As shown in [32] due to the opposite voltage ripple on FCs, the switch voltages can by unbalanced by a maximum peak-to-peak voltage ripple of the FCs, which leads to a strong asymmetry of the switches’ blocking voltages. To mitigate this asymmetry, further investigations of active balancing methods are required, and experimental verification of such methods, which, to the knowledge of the authors, is so far missing in literature, is needed. In addition, so far no method to ensure voltage balancing in no-load operation, i.e., with zero output current, has been presented.

In this context, in [29] we have proposed a Q2L-5L-FCC half-bridge and provided the fundamental description of Q2L operation as well as the passive and active balancing of the FC voltages for a Q2L-3L-FCC. Addressing the need discussed above, this paper generalizes these analyses and proposes a new, comprehensive concept for load-independent FC voltage balancing of Q2L-FCC bridge-legs, which so far is lacking in the literature. Similarly, so far literature does not report experimentally validated Q2L operation of FCC bridge-legs with non-sinusoidal (i.e., DC) or even zero output currents. This paper addresses this need by providing a comprehensive experimental validation of the proposed concept for load-independent FC voltage balancing. This concept comprises an original method of active cell voltage balancing using all switching sequences and it includes a novel method to balance the FC voltages even without a load current flowing (e.g., during start-up). Figure 1a presents the considered 5L-FCC. Aiming for generic results, we consider two exemplary DC-link/load configurations resulting in symmetric (typical, e.g., for an isolated DC-DC converter) or asymmetric (typical, e.g., for a PFC rectifier or a motor inverter) output currents. Figure 1b,c show corresponding exemplary waveforms and the characteristic staggered Q2L transitions of the bridge-leg’s output voltage in case of zero-voltage switching (ZVS) and hard-switching (HS).

This paper is organized as follows: Section 2 describes the Q2L operating principle of the 5L-FCC half-bridge for ZVS and HS transitions with non-zero output current. In addition, Q2L transitions with zero output current are analyzed, too, and a generic description of resulting charge and voltage increments is derived. Section 3 briefly recapitulates open-loop (passive) balancing of FCs, before then Section 4 presents the proposed concept of load-independent closed-loop FC voltage balancing using a model predictive controller (MPC) with FC voltage or cell voltage reference tracking. Furthermore, we introduce the cell multiple switching (CMS) concept to facilitate FC voltage balancing with zero output current. Section 5 covers the hardware demonstrator used to experimentally validate the proposed concepts. The experimental results are presented and discussed in Section 6, before Section 7 provides a concluding discussion. Finally, Appendix A investigates the behavior of CMS for semiconductors of different voltage classes. Appendix B complements the analysis of load-independent FC voltage balancing in Q2L-FCCs by discussing the behavior under overload and short-circuit conditions.

2. Q2L Operation of the 5L-FCC

This section recapitulates the processes in the Q2L-operated 5L-FCC for ZVS and HS transitions employing consecutive switching sequences described in [29]. Next, the analysis is extended by first considering also non-consecutive switching sequences and second including operation of the Q2L-FCC with zero output current. The in-depth analysis of the switching transitions given here is required to determine the total net charge exchange of the flying capacitors during Q2L transitions and ultimately to enable the development of a robust FC voltage balancing concept for Q2L-FCCs. Note that the obtained results are generic and apply to N-level Q2L-FCCs. However, we exemplify the considerations using a 5L-FCC (see Figure 1) for clarity. The corresponding circuit simulations employ an exemplary MOSFET equivalent circuit that consist of a voltage-controlled current source, the non-linear parasitic MOSFET capacitances, the antiparallel body diode, the diode reverse recovery, and the package inductances.

2.1. Operating Principle with Non-Zero Output Current

As it can be seen in Figure 1, a 5L-FCC consists of 4 cells (in general, an N-level FCC consists of $n=N-1$ cells), each comprising two complementary switches ($S_{x\mathrm{p}}$ and $S_{x\mathrm{n}}$) and a flying capacitor ($C_{\mathrm{FCx}}$), whereas the cell which is the closest to the DC-link includes the DC-link capacitance. A Q2L (switching) transition is a commutation of the load current from all upper switches ($S_{1\mathrm{p}}$-$S_{4\mathrm{p}}$) in state on to all bottom switches ($S_{1\mathrm{n}}$-$S_{4\mathrm{n}}$) in state on, cf. Figure 1a, or vice versa. The bride-leg output voltage $v_{\mathrm{o}}$ thus attains two distinct voltage levels ($V_{\mathrm{dc}}/2$ and $-V_{\mathrm{dc}}/2$) for most of the time and the several intermediate voltage levels appear only shortly during the Q2L transitions. A Q2L transition is characterized by a switching sequence ($SEQ$) that defines the order in which the individual cells are commutated. For example, in a 5L-FCC $SE{Q}_{1234}$ means that the cells are commutated consecutively starting from cell 1 and ending with cell 4, see Figure 2a.

Figure 2a illustrates such a Q2L transition and defines selected time intervals for the example of a falling slope of $v_{\mathrm{o}}$, positive output current $i_{\mathrm{o}}$ and $SE{Q}_{1234}$ which results in ZVS transitions for all switches. Figure 2b shows the simulated key waveforms of this transition. Similarly, Figure 2c shows key waveforms for a HS transition, i.e., constant positive output current ($I_{\mathrm{o},\max }$) during the switching transition with positive slope of $v_{\mathrm{o}}$ and $SE{Q}_{4321}$. For a more in-depth description of processes in the sub-intervals of ZVS and HS commutations we refer to [29].

Note that consecutive sequences, i.e., $SE{Q}_{1234}$ or $SE{Q}_{4321},$ lead to FC charge increments given by

$$\begin{array}{cc}\hfill |\Delta Q_{\mathrm{FC}\left\{j\right\}}|& \approx T_{\mathrm{delay}\left\{j\right\}}\left|I_{\mathrm{o},\max }\right|,\hfill \end{array}$$

(1)

where j is the number of the FC and $T_{\mathrm{delay}}$ is the time allocated for the transition of an individual cell. Note that the selection of $T_{\mathrm{delay}}$ is discussed in detail in Section 2.3. To facilitate the modeling and balancing of FC voltages, we assume equal delay times $T_{\mathrm{delay}}$ for all cells and thus identical base charge increments result:

$$\begin{array}{cc}\hfill \Delta Q_{\mathrm{FC}0}=\Delta Q_{\mathrm{FC}1}=\Delta Q_{\mathrm{FC}2}=\Delta Q_{\mathrm{FC}3}& \approx T_{\mathrm{delay}}{I}_{\mathrm{o},\max }.\hfill \end{array}$$

(2)

It is worth noting that the transferred charges are independent of the switching frequency and the number of levels. However, the sign of the net charge exchange of an FC during a Q2L transition for a given sequence depends on the sign of the load current and the direction of the voltage slope.

For FCC realizations with more than two cells, i.e., $n>2$ ($N>3$), the cells can also be switched in a non-consecutive manner and thus a total of $(n!)$ different consecutive and non-consecutive sequences exists. The subset of non-consecutive sequences contains $(n!-2)$ sequences. Figure 3 presents an example of a Q2L transition with the non-consecutive sequence $SE{Q}_{1324}$: FC₁ and FC₃ are charged with $2\Delta Q_{\mathrm{FC}0}$, whereas the FC₂ is discharged with $\Delta Q_{\mathrm{FC}0}$. Therefore, in contrast to consecutive sequences, non-consecutive sequences lead to non-equal charge exchanges of the individual FCs (for the same $T_{\mathrm{delay}}$ and $I_{\mathrm{o},\max }$). Therefore, even charging of some FCs and discharging of others during the same Q2L transition can be achieved. Note, however, that all FCs experience a charge exchange, and hence are coupled through a sequence in the sense that it is not possible to influence only a selected subset of the FCs.

Considering the exemplary 5L-FCC,

Table 1. Effect of all sequences available (${\mathcal{S}}_{\mathrm{CL}}$) for Q2L-5L-FCC on FC charge increments in the function of delay times for Q2L ZVS transition (for HS transition, the same value but opposite signs apply): (+1) charge, (−1) discharge, (0) no effect. Scaling the values with the respective $T_{\mathrm{delay}\left\{n\right\}}$ and $I_{\mathrm{o},\max }$ gives the charge increment values. Note that the table is simplified and values for $SE{Q}_{3\mathrm{xxx}}$ and $SE{Q}_{4\mathrm{xxx}}$ are obtained by using symmetry and multiplying the respective values by (−1).

	FC1				FC2				FC3
Sequence	${\mathit{T}}_{\mathbf{delay}\mathbf{1}}$	${\mathit{T}}_{\mathbf{delay}\mathbf{2}}$	${\mathit{T}}_{\mathbf{delay}\mathbf{3}}$	${\mathit{T}}_{\mathbf{delay}\mathbf{4}}$	${\mathit{T}}_{\mathbf{delay}\mathbf{1}}$	${\mathit{T}}_{\mathbf{delay}\mathbf{2}}$	${\mathit{T}}_{\mathbf{delay}\mathbf{3}}$	${\mathit{T}}_{\mathbf{delay}\mathbf{4}}$	${\mathit{T}}_{\mathbf{delay}\mathbf{1}}$	${\mathit{T}}_{\mathbf{delay}\mathbf{2}}$	${\mathit{T}}_{\mathbf{delay}\mathbf{3}}$	${\mathit{T}}_{\mathbf{delay}\mathbf{4}}$
$SE{Q}_{1234}$	+1	0	0	0	0	+1	0	0	0	0	+1	0	$-SE{Q}_{4321}$
$SE{Q}_{1243}$	+1	0	0	0	0	+1	0	+1	0	0	0	−1	$-SE{Q}_{4312}$
$SE{Q}_{1324}$	+1	0	+1	0	0	0	−1	0	0	+1	+1	0	$-SE{Q}_{4231}$
$SE{Q}_{1342}$	+1	0	+1	+1	0	0	−1	−1	0	0	+1	0	$-SE{Q}_{4213}$
$SE{Q}_{1423}$	+1	0	0	+1	0	+1	0	0	0	−1	0	−1	$-SE{Q}_{4132}$
$SE{Q}_{1432}$	+1	0	+1	+1	0	0	−1	0	0	0	0	−1	$-SE{Q}_{4123}$
$SE{Q}_{2134}$	0	−1	0	0	+1	+1	0	0	0	0	+1	0	$-SE{Q}_{3421}$
$SE{Q}_{2143}$	0	−1	0	0	+1	+1	0	+1	0	0	0	−1	$-SE{Q}_{3412}$
$SE{Q}_{2314}$	0	−1	−1	0	0	+1	0	0	+1	0	+1	0	$-SE{Q}_{3241}$
$SE{Q}_{2341}$	0	−1	−1	−1	0	+1	0	0	0	0	+1	0	$-SE{Q}_{3214}$
$SE{Q}_{2413}$	0	−1	0	−1	+1	+1	0	+1	−1	0	0	−1	$-SE{Q}_{3142}$
$SE{Q}_{2431}$	0	−1	−1	−1	0	+1	0	+1	0	0	0	−1	$-SE{Q}_{3124}$
	$T_{\mathrm{delay}4}$	$T_{\mathrm{delay}3}$	$T_{\mathrm{delay}2}$	$T_{\mathrm{delay}1}$	$T_{\mathrm{delay}4}$	$T_{\mathrm{delay}3}$	$T_{\mathrm{delay}2}$	$T_{\mathrm{delay}1}$	$T_{\mathrm{delay}4}$	$T_{\mathrm{delay}3}$	$T_{\mathrm{delay}2}$	$T_{\mathrm{delay}1}$	Sequence
	FC3				FC2				FC1

summarizes all sequences, denoted henceforth as set ${\mathcal{S}}_{\mathrm{CL}}$, and their effects on the FCs’ charge for the case of ZVS transitions. It is found that for the HS transition, the sequences have opposite effect. Therefore, the values from Table 1 need to be multiplied by (−1) to obtain the charge increments for HS transitions. Furthermore, Table 1 is simplified by utilizing symmetry, i.e., the fact that sequences $SE{Q}_{3\mathrm{xxx}}$ and $SE{Q}_{4\mathrm{xxx}}$ result in the same absolute values of total charge exchanges as $SE{Q}_{2\mathrm{xxx}}$ and $SE{Q}_{1\mathrm{xxx}}$, respectively. However the order of FCs and delay times is reversed, and the values from the table must be multiplied with $(-1)$ to obtain the actual FC charge exchanges, which is denoted by the − sign preceding the sequence’s name (see right & bottom labels in Table 1).

Based on this analysis, we formulate the total change of charge provided to the FCs as

$$\begin{array}{c}\hfill \mathbf{\Delta }{\mathit{Q}}_{\mathrm{FC}}=\left[\begin{array}{c}\Delta Q_{\mathrm{FC}1}\\ \cdots \\ \Delta Q_{\mathrm{FC}\left\{j\right\}}\end{array}\right]=I_{\mathrm{o},\max }(\mathit{S}\times {\mathit{T}}_{\mathrm{delay}}),\end{array}$$

(3)

where

$$\begin{array}{c}\hfill {\mathit{T}}_{\mathrm{delay}}={\left[\begin{array}{ccc}{T}_{\mathrm{delay}1}& \cdots & T_{\mathrm{delay}\left\{n\right\}}\end{array}\right]}^T\end{array}$$

(4)

is a delay time vector and $\mathit{S}$ is a matrix which specifies how the particular delay times influence the charge change of the FCs and is equivalent to the rows in Table 1. The matrix $\mathit{S}$ is constructed by stacking the effects that the sequence has on each FC, hence it has dimensions of $j\times n$. From Table 1 it is apparent that the charge increments can be equal to values from the following set: $\pm \Delta Q_{\mathrm{FC}0}·\{1,2,\dots ,j\}$. In order to ensure well defined voltage levels across the switches and ease of balancing, equal values $C_{\mathrm{FC}}$ of all FCs are selected, which consequently leads to the voltage increments

$$\begin{array}{c}\hfill \mathbf{\Delta }{\mathit{V}}_{\mathrm{FC}}=\left[\begin{array}{c}\Delta V_{\mathrm{FC}1}\\ \cdots \\ \Delta V_{\mathrm{FC}\left\{j\right\}}\end{array}\right]=\frac{\mathbf{\Delta }{\mathit{Q}}_{\mathrm{FC}}}{C_{\mathrm{FC}}}.\end{array}$$

(5)

Henceforth, for the sake of simplicity, we will consider equal delay times $T_{\mathrm{delay}}$ for all cells, and the implications of that assumption are discussed further in Section 4. Taking as an example the sequence $SE{Q}_{1324}$ (cf. Figure 3) and equal delay times $T_{\mathrm{delay}}$ we obtain:

$$\mathbf{\Delta }{\mathit{V}}_{1324}=\frac{I_{\mathrm{o},\max }}{C_{\mathrm{FC}}}\left[\begin{array}{cccc}1& 0& 1& 0\\ 0& 0& -1& 0\\ 0& 1& 1& 0\end{array}\right]\times \left[\begin{array}{c}{T}_{\mathrm{delay}}\\ T_{\mathrm{delay}}\\ T_{\mathrm{delay}}\\ T_{\mathrm{delay}}\end{array}\right],$$

(6)

$$\begin{array}{cc}\hfill \mathbf{\Delta }{\mathit{V}}_{1324}& =\frac{\Delta Q_{\mathrm{FC}0}}{C_{\mathrm{FC}}}\left[\begin{array}{c}2\\ -1\\ 2\end{array}\right].\hfill \end{array}$$

(7)

which corresponds to the FC voltage waveforms in Figure 3.

2.2. Operating Principle with Zero Output Current: Cell Multiple Switching

From (3) it is obvious that in case of zero output current, the charge increments of the FCs are expected to be zero. Figure 4 presents the simulation results for Q2L operation with $i_{\mathrm{o}}=0$ during the switching transition with negative slope of $v_{\mathrm{o}}$. It can be seen that during each commutation, due to the hard-switching and charging of the switches’ output capacitances, the commutation loop current leads to an exchange of charges, i.e., subtraction of charge from a cell’s input-side capacitor and addition of charge to the output-side capacitor of the respective converter cell. This can be seen, e.g., in Figure 4 between $t_2<t<t_3$ where the exchange of charges between FC₁ and FC₂ occurs. Note that in case of zero-current switching of cell 1, the charge is delivered to the load, whereas in case of cell 3, the charge delivered to FC₃ is subtracted from the DC-link. For an in-depth analysis we refer to [40]. However, the net charge exchange of each FC over the entire transition is approximately zero. Nevertheless, the exchange of charge between the FCs during no-current Q2L transitions can be utilized in a novel method for balancing the FC voltages in case of zero output current.

To do so, we insert additional commutations in one or more cells during a Q2L transition. This leads to additional hard-switching events of one or several of the MOSFETs. This concept that we refer to as cell multiple switching (CMS) thus allows to obtain non-zero net charge exchange of certain FCs over a Q2L transition, therefore offering a means of balancing the FC voltages even in case of zero output current.

Figure 5 shows the exemplary simulation results for a 5L-FCC in split DC-link configuration with zero output current during the Q2L transition with negative slope of $v_{\mathrm{o}}$ and a CMS event inserted in cell 3. It can be noticed that until $t<t_3$ the processes in the transition occur as for a sequence $SE{Q}_{1234}$ (see Figure 4). However, at $t=t_4$, $S_{3\mathrm{n}}$ turns off and the circuit remains in steady-state during $[t_4,t_5]$ and $v_{\mathrm{o}}=-V_{\mathrm{dc}}/4$ applies. The time interval between $t_3$ and $t_4$, in which $S_{3\mathrm{n}}$ is on, has a duration of one pulse time $T_{\mathrm{p}}$. Two additional switching operations are inserted between $t_5<t<t_8$: First, $v_{\mathrm{o}}$ is switched back to 0 during $t_5<t<t_7$, and, subsequently, $v_{\mathrm{o}}$ is switched to $-V_{\mathrm{dc}}/4$ during $t_7<t<t_8$. During $t_3<t<t_4$, the charge of FC₂ is increased by $\Delta Q_{\mathrm{S}3\mathrm{p}}$ and FC₃ is discharged by the same value, where

$$\begin{array}{c}\hfill \Delta Q_{\mathrm{S}3\mathrm{p}}=Q_{\mathrm{oss},3\mathrm{p}}+Q_{\mathrm{rr},3\mathrm{p}},\end{array}$$

(8)

with $Q_{\mathrm{oss},3\mathrm{p}}$ and $Q_{\mathrm{rr},3\mathrm{p}}$ being the charges stored in the output capacitance $C_{\mathrm{oss}}$ of the MOSFET and the reverse-recovery charge of the anti-parallel diode, respectively. During $t_5<t<t_6$, FC₂ is again charged, whereas FC₃ is discharged by $\Delta Q_{\mathrm{S}3\mathrm{n}}$. Finally, at $t=t_8$, $S_{4\mathrm{n}}$ turns on and the last commutation is completed. It can be seen that the presented sequence introduces two additional switching pulses in cell 3, therefore it is denoted as $SE{Q}_{123\left(33\right)4}$, where subscript (33) denotes the CMS event in cell 3.

Assuming that the charge increment from each switch is approximately the same and equal to $\Delta Q_{\mathrm{S}}$, a CMS event results in total net charge increment of the affected FCs equal to:

$$\Delta Q_{\mathrm{FC}}\approx 2\Delta Q_{\mathrm{S}}.$$

(9)

The corresponding voltage increment per CMS event is thus:

$$\begin{array}{cc}\hfill \Delta V_{\mathrm{CMS}}& \approx \frac{\Delta Q_{\mathrm{FC}}}{C_{\mathrm{FC}}}\approx \frac{2\Delta Q_{\mathrm{S}}}{C_{\mathrm{FC}}}.\hfill \end{array}$$

(10)

Using the linear charge-equivalent output capacitance $C_{\mathrm{Q},\mathrm{eq}}$ and assuming that $Q_{\mathrm{rr}}\approx 0$, (10) can be further simplified to:

$$\begin{array}{c}\hfill \Delta Q_{\mathrm{S}}={\int }_0^{V_{\mathrm{ds}}}{C}_{\mathrm{oss}}\left(v\right)·\mathrm{d}v=C_{\mathrm{Q},\mathrm{eq}}·V_{\mathrm{ds}},\end{array}$$

(11)

$$\Delta V_{\mathrm{CMS}}\approx \frac{2C_{\mathrm{Q},\mathrm{eq}}·V_{\mathrm{ds}}}{C_{\mathrm{FC}}}.$$

(12)

Therefore, the CMS balancing controllability depends on the capacitance ratio $k_{\mathrm{c}}=2C_{\mathrm{Q},\mathrm{eq}}/C_{\mathrm{FC}}$ and is discussed in detail for semiconductors of different voltage classes in Appendix A.

2.3. Duty Cycle Limitation/Selection of $T_{\mathit{delay}}$

For a certain output current $I_{\mathrm{o},\max }$ the charge increments of the FCs during a Q2L transition are proportional to the delay times, see (3). Hence this parameter is a degree of freedom in the design of Q2L-FCCs and its constraints are discussed in the following. The duration $T_{\mathrm{t}}$ of a complete Q2L transition, cf. Figure 2b,c, in the NL-FCC is given by

$$T_{\mathrm{t}}\approx (N-1)T_{\mathrm{delay}},$$

(13)

$$\begin{array}{cc}\hfill & \approx 4T_{\mathrm{delay}},\mathrm{for}N=5.\hfill \end{array}$$

(14)

Thus, the Q2L transitions limit the maximum duty cycle to

$$\begin{array}{cc}\hfill d_{\max }& =1-\frac{2T_{\mathrm{t}}}{T_{\mathrm{s}}},\hfill \end{array}$$

(15)

$$\begin{array}{cc}\hfill & =1-\frac{8T_{\mathrm{delay}}}{T_{\mathrm{s}}},\mathrm{for}N=5.\hfill \end{array}$$

(16)

Therefore, the delay time can be selected only within certain boundaries

$$T_{\mathrm{delay}}\in [T_{\min },T_{\max }].$$

(17)

The maximum boundary $T_{\max }$ follows from the allowable duration of the switching transition, i.e., from the application-specific $d_{\max }$, given that increased commutation times decrease the available output voltage-time product. The minimum boundary $T_{\min }$ follows from the system’s physical limitations, i.e., the required interlock delay time to prevent shoot-through events. In practical applications additional constraints can be considered, e.g., in soft-switching Q2L-FCCs the time required to achieve ZVS in partial-load operation increases $T_{\min }$ above the minimum required to prevent shoot-through.

Note that if CMS is activated in the Q2L-FCC, the duration of the transition increases due to the inserted additional pulses. In case of inserting $n_{\mathrm{CMS}}$ events of duration $T_{\mathrm{CMS}}$ (cf. Figure 5), the transition time is:

$$T_{\mathrm{CMS}}\approx 2n_{\mathrm{CMS}}(T_{\mathrm{p}}+T_{\mathrm{delay}}),$$

(18)

$$T_{\mathrm{t}}\approx (N-1)T_{\mathrm{delay}}+T_{\mathrm{CMS}},$$

(19)

$$\begin{array}{cc}\hfill & \approx 6T_{\mathrm{delay}}+2T_{\mathrm{p}},\mathrm{for}N=5,n_{\mathrm{CMS}}=1.\hfill \end{array}$$

(20)

Therefore, based on the application specific $d_{\max }$, the allowable number of CMS events, the number of involved cells, and $T_{\mathrm{p}}$ must be defined together with $T_{\mathrm{delay}}$.

3. Open-Loop FC Balancing

As described earlier in [29], the balancing of the FC voltages can be achieved with a passive modulation that employs consecutive sequences, hence either by charging or discharging all FCs with the same charge increment during a Q2L transition, see Table 1. For a versatile HB realization, i.e., designed for operation with asymmetrical or symmetrical output currents, the following modulation scheme has been proposed:

$${\mathcal{S}}_{\mathrm{OL}}=\{SE{Q}_{1234},SE{Q}_{1234},SE{Q}_{4321},SE{Q}_{4321},\dots \}.$$

(21)

The scheme results in open-loop balancing over two switching periods (4 Q2L transitions). However, the maximum peak-to-peak voltage ripple is

$$\Delta V_{\mathrm{pp}}\approx 2\frac{T_{\mathrm{delay}}·I_{\mathrm{o},\max }}{C_{\mathrm{FC}}},$$

(22)

due to the charging characteristic with asymmetric currents. Please refer to [29] for an in-depth discussion.

While in principle this modulation scheme is sufficient to achieve balanced FC voltages, the controllability is limited and results in a non-optimal FC voltage ripple. Advantageously, this approach does not require FC voltage measurements. On the other hand, balancing resistors connected in parallel to the switches are necessary to ensure balanced FC voltages in case of zero output current. We refer to this approach as open-loop (OL) balancing and provide experimental evaluation in Section 6.2.

4. Load-Independent Closed-Loop Balancing

In this section we propose a concept for load-independent closed-loop (CL) balancing. The most straightforward approach is to implement a controller which uses measurements of the FC voltages and of the output current to achieve close tracking of the FC voltage references. However, as indicated in [32] due to the opposite voltage ripple on FCs, the switches can be operated with a strong asymmetry of the blocking voltages. To address this issue, alternatively the controller can be built to equalize the cell voltages, derived as differences between the voltages of capacitors adjacent to the switches, and hence ensuring equal voltage sharing among the series-connected switches. We present the two aforementioned approaches in detail in Section 4.1. Furthermore, the proposed balancing concept is eventually implemented and tested (see Section 6) up to the nominal output current of the FCC; for the discussion of extreme load cases, i.e., an overload and short-circuit currents we refer to Appendix B.

Figure 6a shows the block diagram of an FCC HB with Q2L voltage balancing controller. The measured HB output current $i_{\mathrm{o}}$ is fed to the output quantity controller which specifies the reference output voltage $V_{\mathrm{o}}^{\ast }$ for the modulator and the Q2L voltage balancing controller. The design and realization of the output quantity controller is decoupled from Q2L operation and not within the scope of this paper. For that reason, the considered Q2L-FCC is operated with a fixed duty cycle of $d=50\%$ in the following.

As mentioned before, a given switching sequence affects several FC voltages, i.e., they are coupled through the selection of the sequences. Therefore, controlling all FC voltages is a multiple-input multiple-output (MIMO) control problem. MIMO systems can be easily addressed by model predictive control (MPC) which is formulated in the time domain [41,42]. Therefore, we use MPC with reference tracking to realize a Q2L voltage balancing controller.

Essentially, based on the slope of the reference output voltage $V_{\mathrm{o}}^{\ast }$, the measured FC voltages $v_{\mathrm{FC}1}$, …, $v_{\mathrm{FC}j}$, the measured output current $i_{\mathrm{o}}$, and the DC-link voltage $v_{\mathrm{dc}}$, the Q2L voltage balancing controller selects a switching sequence $SEQ$ and respective times $T_{\mathrm{delay}}$, $T_{\mathrm{p}}$, which are the input to the actual Q2L modulator. Figure 6b presents the detailed block diagram of the controller which contains two distinct parallel paths (sub-controllers), i.e., one for control without load current using CMS ($i_{\mathrm{o}}=0$, based on FC voltage tracking, see Section 4.1.1) and one for operation with non-zero load current ($|i_{\mathrm{o}}|>0$, based on cell voltage tracking, see Section 4.1.2). The implementation of these sub-controllers is explained in the following subsections. In the last part of the Q2L controller, based on the value of $i_{\mathrm{o}}$, the multiplexer decides which of the two sub-controllers is activated.

Ultimately, both controllers define a certain commutation sequence ($SEQ$) for a given Q2L transition (e.g., $SEQ=123\left(33\right)4$ for the example shown in Figure 4) and also the values for $T_{\mathrm{delay}}$ and $T_{\mathrm{p}}$ to be used. During the Q2L transition, the modulator translates this information into gate signals for the individual switches according to the state machine shown in Figure 7.

4.1. Closed-Loop Control with Non-Zero Output Current

In [29] we have proposed an active method for FC voltage balancing in a Q2L-3L-FCC. This method relies on the determination of an optimal ripple of $v_{\mathrm{FC}}$ and then the computation of individual delay times that eliminate any voltage ripple error in the next transition, similarly to a deadbeat controller. This method is however complex and computationally expensive for FCC realizations with $N>3$: For each of the $(N-1)!$ available sequences, $(N-1)$ different delay times for ($N-2$) FCs need to be considered. For that reason, in this work we propose a different approach that still utilizes all available sequences. However, to limit the degrees of freedom, we make the following simplifications:

• All delay times in a given switching transition are equal, i.e., $T_{\mathrm{delay}1}=T_{\mathrm{delay}2}=T_{\mathrm{delay}3}=T_{\mathrm{delay}4}=T_{\mathrm{delay}}$.
• Two discrete delay time values are used: $T_{\mathrm{delay}}\in \{T_{\min },T_{\max }\}$, where $T_{\min }$ is intended to be selected by the controller in the steady-state in order to keep the voltage ripple small. On the other hand, $T_{\max }$ is selected in cases of significant unbalance to reduce the error more aggressively.

For the exemplary 5L-FCC, there are thus only 48 different possible actions that the controller needs to consider (24 unique sequences × 2 unique delay times). Note that with a higher number of levels, the number of possible actions increases substantially, as does the computation effort. However, to reduce the computation effort, the solution to the optimization problem can be solved offline and stored in a look-up table (LUT), see more details of implementation presented in Section 4.2.

As presented in Section 2.1 the charge increments in the FCs occur during the switching transition only, whose duration is relatively short compared to the switching period. Therefore, a discrete time domain with constant sampling interval $k\left(0.5T_{\mathrm{s}}\right)$ is defined, where $k\in \mathbb{N}$ denotes the time steps, cf. Figure 8a. Note that this simplified expression is valid for a fixed duty cycle of 50% only. For realizations with variable duty cycle, the sampling intervals would need to be changed such that the sampling instants coincide with the Q2L transitions. Figure 8b shows the timing of the measurement data acquisition and the control routine execution in the FPGA within the highlighted Q2L transition. It can be noticed that the measured value of the output current is delayed by a measurement delay $T_{\mathrm{ADC}}$ due to analog-to-digital conversion (ADC). Furthermore, $T_{\mathrm{comp}}$ denotes the delay resulting from performing the required computations in the FPGA. For the experimental system considered in this paper (cf. Section 5 for details) the total delay amounts to approx. 600 ns and the deviation between the measured current used for the controller execution and the current value present during the actual switching transition is found to be less than 2.6%; therefore we do not employ delay compensation.

4.1.1. FC Voltage Tracking

In this approach the proposed MPC relies on the model of the voltage increment (cf. (5)) to predict the future FC voltages,

$$\begin{array}{cc}\hfill {\mathit{V}}_{\mathrm{FC}}(k+1)& ={\mathit{V}}_{\mathrm{FC}}\left(k\right)+\mathbf{\Delta }{\mathit{V}}_{\mathrm{FC}}\left(k\right),\hfill \end{array}$$

(23)

where

$$\begin{array}{c}\hfill {\mathit{V}}_{\mathrm{FC}}={\left[\begin{array}{ccc}{v}_{\mathrm{FC}1}& \cdots & v_{\mathrm{FC}\left\{j\right\}}\end{array}\right]}^T\end{array}$$

(24)

and it depends on the available control actions and input variables:

$$\begin{array}{cc}\hfill \mathbf{\Delta }{\mathit{V}}_{\mathrm{FC}}\left(k\right)& =f_1(V_{\mathrm{o}}^{\ast },{\mathcal{S}}_{\mathrm{CL}},{\mathit{T}}_{\mathrm{delay}},i_{\mathrm{o}})\left(k\right).\hfill \end{array}$$

(25)

In order to keep the computation effort low and eliminate the need to predict the future output current, a one-step prediction horizon is used, i.e., $N_{\mathrm{p}}=1$, which is found to provide sufficient performance. The control problem at time step k of tracking the FC voltage reference can be mapped into the cost function:

$$\begin{array}{cc}\hfill J_1& =\sum [{({\mathit{V}}_{\mathrm{FC}}^{\ast }-{\mathit{V}}_{\mathrm{FC}}(k+1))}^2],\hfill \end{array}$$

(26)

using the squared 2-norm, where

$$\begin{array}{cc}\hfill {\mathit{V}}_{\mathrm{FC}}^{\ast }& =\frac{V_{\mathrm{dc}}}{N-1}{\left[\begin{array}{cccc}1& 2& \cdots & j\end{array}\right]}^T\hfill \end{array}$$

(27)

$$\begin{array}{cc}\hfill & =V_{\mathrm{dc}}{\left[\begin{array}{ccc}1/4& 1/2& 3/4\end{array}\right]}^T,\mathrm{for}N=5.\hfill \end{array}$$

(28)

Using the squared 2-norm, possible control actions that would lead to large voltage deviations and hence poor reference tracking are heavily penalized, which ultimately ensures good tracking performance. The optimization problem can be stated as

$$\begin{array}{cc}\hfill & [SE{Q}_{\mathrm{opt}}\left(k\right),{\mathit{T}}_{\mathrm{opt}}\left(k\right)]=\arg \mathrm{minimize}{J}_1\hfill \end{array}$$

(29a)

$$\begin{array}{cc}\hfill & \mathrm{subject}\mathrm{to}{\mathit{T}}_{\mathrm{delay}}\in {\mathbf{1}}_{1,\mathrm{n}}\times \{T_{\min },T_{\max }\}\hfill \end{array}$$

(29b)

$$\begin{array}{cc}\hfill & SEQ\left(k\right)\in {\mathcal{S}}_{\mathrm{CL}}\hfill \end{array}$$

(29c)

4.1.2. Cell Voltage Tracking

In the second approach, to ensure well defined voltage levels across the switches, the controller is built to equalize the cell voltages,

$$\begin{array}{c}\hfill {\mathit{V}}_{\mathrm{cell}}=\left[\begin{array}{c}{v}_{\mathrm{FC}1}\\ v_{\mathrm{FC}2}-v_{\mathrm{FC}1}\\ \cdots \\ v_{\mathrm{dc}}-v_{\mathrm{FC}\left\{j\right\}}\end{array}\right],\end{array}$$

(30)

instead of the FC voltages. Note that unlike the FC voltages, all cell voltages are ideally equal. Using the cell voltage increments defined as

$$\mathbf{\Delta }{\mathit{V}}_{\mathrm{cell}}=\left[\begin{array}{c}\Delta V_{\mathrm{cell}1}\\ \Delta V_{\mathrm{cell}2}\\ \cdots \\ \Delta V_{\mathrm{cell}\left\{n\right\}}\end{array}\right]=\left[\begin{array}{c}\Delta V_{\mathrm{FC}1}\\ \Delta V_{\mathrm{FC}2}-\Delta V_{\mathrm{FC}1}\\ \cdots \\ -\Delta V_{\mathrm{FC}\left\{j\right\}}\end{array}\right],$$

(31)

the MPC can predict the cell voltages at the next time step as

$$\begin{array}{cc}\hfill {\mathit{V}}_{\mathrm{cell}}(k+1)& ={\mathit{V}}_{\mathrm{cell}}\left(k\right)+\mathbf{\Delta }{\mathit{V}}_{\mathrm{cell}}\left(k\right),\hfill \end{array}$$

(32)

which, similar to (25), depends on the available control actions and input variables

$$\begin{array}{cc}\hfill \mathbf{\Delta }{\mathit{V}}_{\mathrm{cell}}\left(k\right)& =f_2(V_{\mathrm{o}}^{\ast },{\mathcal{S}}_{\mathrm{CL}},{\mathit{T}}_{\mathrm{delay}},i_{\mathrm{o}})\left(k\right).\hfill \end{array}$$

(33)

The function $f_2$ maps the sequences to effects on the cell voltage increments in dependence of the delay times based on Table 1. Consequently, the following cost function describes the control problem of tracking the cell voltage references at time step k:

$$\begin{array}{cc}\hfill J_2& =\sum [{({\mathit{V}}_{\mathrm{cell}}^{\ast }-{\mathit{V}}_{\mathrm{cell}}(k+1))}^2],\hfill \end{array}$$

(34)

where

$$\begin{array}{cc}\hfill {\mathit{V}}_{\mathrm{cell}}^{\ast }& =\frac{V_{\mathrm{dc}}}{n}\times {\mathbf{1}}_{1,\mathrm{n}}.\hfill \end{array}$$

(35)

Finally, the optimization problem is stated as (29), however in this case minimizes the cost function $J_2$. Both proposed control targets, i.e., tracking of FC voltages or cell voltages, result in good FC voltage balancing performance. However, the cell voltages controller ensures more balanced and symmetrized switch voltages and is used in experiments presented in Section 6.

Regarding implementation (cf. Figure 6b), first a pre-processor computes (32)–(33), i.e., based on the required $V_{\mathrm{o}}^{\ast }$ slope, the sign of $i_{\mathrm{o}}$, the expected cell voltage increments $\Delta {\mathit{V}}_{\mathrm{cell}}$ for all combinations of sequences (cf. Table 1) and $\{T_{\min },T_{\max }$} are computed and the cell voltages at time step $k+1$ are predicted. Next, the cost function (34) is evaluated and the optimization problem (29) for $J_2$ solved, resulting in the selection of the control action (i.e., one sequence and either $T_{\min }$ or $T_{\max }$) with the minimum cost, i.e., leading to cell voltages at time step $k+1$ that are as close as possible to the reference values. Note that Table 1 shows the effect on charge increments for the ZVS-type of transitions, therefore, in the last step, the post-processor by using the symmetry, adapts the signs if the next transition is of HS-type instead (note that the transition type follows from the desired output voltage change and the output current direction). In the prototype system described below in Section 5, this control algorithm has been implemented in a high-performance Xilinx Zynq Z-7020 SoC.

4.2. Closed-Loop Control with Zero Output Current

As discussed above in Section 2.2, CMS can be utilized to charge/discharge FCs even in case of zero output current. The following assumptions are considered for the realization of the corresponding CMS-based controller, i.e., the second path shown in Figure 6b:

• The delay times $T_{\mathrm{delay}}$ are set to the minimum value $T_{\min }$ as their duration does not impact the balancing when $i_{\mathrm{o}}=0$.
• Similarly, the sequence of the switching actions within a Q2L transition does not influence the total voltage increments when $i_{\mathrm{o}}=0$. Therefore only the sequence $SE{Q}_{1234}$ is used for simplicity when CMS is active.
• The pulse time $T_{\mathrm{p}}$ of a CMS event must be sufficiently long for a zero-current HS transition to complete. Therefore, we set $T_{\mathrm{p}}=T_{\min }$.

Note that using short delay and pulse times is preferable to minimize the overall transition times $T_{\mathrm{t}}$.

The analysis presented above in Section 2.2 indicates that theoretically there is an infinite number of ways to insert CMS events if the number of events inserted per Q2L transition is not limited. However, practically, it is desirable to keep the number of CMS events per transition low (duty cycle limitation) and it is found that for the considered exemplary 5L-FCC a selection of only 6 CMS sequences (given in

Table 2. Effect on charge increments of the FCs in dependence of different CMS events/sequences: (+1) charge, (−1) discharge, (0) no effect. Scaling the values by $2\Delta Q_{\mathrm{S}}$ gives the charge increment values.

CMS Events	CMS seq.	$\mathbf{\Delta }{\mathit{Q}}_{\mathbf{FC}1}$	$\mathbf{\Delta }{\mathit{Q}}_{\mathbf{FC}2}$	$\mathbf{\Delta }{\mathit{Q}}_{\mathbf{FC}3}$
0001	$SE{Q}_{1234\left(44\right)}$	0	0	+1
0010	$SE{Q}_{123\left(33\right)4}$	0	+1	−1
0100	$SE{Q}_{12\left(22\right)34}$	+1	−1	0
1000	$SE{Q}_{1\left(11\right)234}$	−1	0	0
0011	$SE{Q}_{123\left(33\right)4\left(44\right)}$	0	+1	0
1100	$SE{Q}_{1\left(11\right)2\left(22\right)34}$	0	−1	0

) is sufficient to achieve robust controllability. The reasoning behind the selection of these CMS sequences is explained in the following.

Interestingly, it can be seen from Table 2 that inserting a CMS event in the $m\mathrm{th}$ cell leads to a discharge of FC_m (in case of $m=n$, the energy is exchanged with the DC-link capacitor), and charges FC_m−1 (for $m=1$ there is no FC to charge). Furthermore, the CMS events can be superimposed to achieve desired charge increments, e.g., events ‘0001’ and ‘0010’ inserted over two subsequent Q2L switching transitions yield the same effect as the same two events ‘0011’ within one Q2L transition. However, the latter results in a longer Q2L transition time and hence a reduction of the available duty cycle. This characteristic can be used to obtain individual balancing of FCs (charge/discharge) over two Q2L transitions. Note that in the following design of the controller, for flexibility reasons, we use all CMS events shown in Table 2.

Similar to the approach used in case of non-zero output current, again we employ an MPC with reference tracking over a finite prediction horizon, but in this case of length $N_{\mathrm{p}}=6$, to accommodate the aforementioned superposition of CMS events in the controller. Moreover, we use FC voltage tracking (not cell votlage tracking), because for zero output current operation, no large voltage ripples occur. Based on Table 2 the set of available CMS sequences is defined as

$$\begin{array}{cc}\hfill \mathcal{U}& =\{0001,0010,0100,1000,0011,1100\}.\hfill \end{array}$$

(36)

We introduce a vector of CMS sequences for the considered prediction horizon:

$$\mathit{U}\left(k\right)\hspace{0.17em}=\hspace{0.17em}\left[\begin{array}{cccc}u\left(k\right)& u(k+1)& \dots & u(k+N_{\mathrm{p}}-1)\end{array}\right].$$

(37)

The prediction model of FC voltages is

$${\mathit{V}}_{\mathrm{FC},\mathrm{CMS}}(k+1)={\mathit{V}}_{\mathrm{FC}}\left(k\right)+\mathbf{\Delta }{\mathit{V}}_{\mathrm{CMS}}\left(k\right),$$

(38)

$$\mathbf{\Delta }{\mathit{V}}_{\mathrm{CMS}}\left(k\right)=f_3\left(\mathcal{U}\right)\left(k\right).$$

(39)

The control problem can be described by the cost function

$$\begin{array}{cc}\hfill J_3& =\sum _{l=k}^{k+N_{\mathrm{p}}-1}[\sum [{({\mathit{V}}_{\mathrm{FC}}^{\ast }-{\mathit{V}}_{\mathrm{FC},\mathrm{CMS}}(l+1))}^2]],\hfill \end{array}$$

(40)

and the solution to the optimization problem is the choice of $\mathit{U}\left(k\right)$ that minimizes this cost function $J_3$:

$${\mathit{U}}_{\mathrm{opt}}\left(k\right)=\arg \mathrm{minimize}{J}_3$$

(41a)

$$\begin{array}{cc}& \mathrm{subject}\mathrm{to}\forall l=k,\dots ,k+N_{\mathrm{p}}-1\hfill \end{array}$$

(41b)

$$\mathit{U}\left(k\right)\in \mathbb{U}$$

(41c)

where $\mathbb{U}$ is the $N_{\mathrm{p}}-\mathrm{times}$ Cartesian product of the set of CMS sequences $\mathcal{U}$, cf. (36). Following the principle of receding horizon policy, only the first element of the optimal CMS sequence ${\mathit{U}}_{\mathrm{opt}}\left(k\right)$ is applied at time step k, and another optimization is performed at the next time step.

The CMS controller (cf. Figure 6b) relies on the solution to the optimization problem (41) which is solved offline: The FC voltage errors (${\mathit{V}}_{\mathrm{FC}}^{\ast }-{\mathit{V}}_{\mathrm{FC}}$) as well as the expected voltage increments $\mathbf{\Delta }{\mathit{V}}_{\mathrm{CMS}}$ are normalized by the capacitance ratio $k_{\mathrm{c}}$ (cf. Section 2.2) and then stored in a look-up table (LUT) for the considered voltage error range. In the online implementation, the CMS pre-processor computes the voltage errors $({\mathit{V}}_{\mathrm{FC}}^{\ast }-{\mathit{V}}_{\mathrm{FC}}\left(k\right))$ and normalizes them. This information is fed to the MPC block which retrieves the optimum solution from the precomputed LUT in the FPGA’s memory. To avoid unnecessary CMS activation, especially when the FC voltages are close to the references (small errors), a voltage hysteresis is considered. Again, the online part of the algorithm has been implemented in a high-performance Xilinx Zynq Z-7020 SoC.

5. Hardware Implementation

In order to validate the proposed concepts, a LV proof-of-concept hardware demonstrator of a 5L-FCC HB has been designed according to the schematic presented in Figure 9. Depending on the connection of the load, two types of operation can be achieved (see also Figure 1): ➀ Symmetrical output current with ZVS transitions, and ➁ asymmetrical output current ZVS and HS transitions. In order to test OL balancing, resistors $R_{\mathrm{b}}$ can be placed in parallel to the switches.

Figure 10 shows the photos of the realized 5L-FCC bridge-leg demonstrator and

Table 3. Specifications and control parameters of the Q2L-5L-FCC proof-of-concept demonstrator.

$V_{\mathrm{dc}}$	100 V	DC-link voltage
$I_{\mathrm{o},\max }$	6.6 A	output current maximum
$f_{\mathrm{s}}$	50 kHz	switching frequency
d	50%	duty cycle
Flying capacitors
$C_{\mathrm{FC}}$	66 nF	CAA572C0G3A663J640LH
$\Delta V_{\mathrm{pp},\max }$	20 V	max. peak-to-peak volt. ripple
Semiconductors
S	150 V/7 m	GaN eFET EPC2033
$C_{\mathrm{oss},\mathrm{eq}}$	760 pF	charge eq. capacitance
Control parameters
$T_{\mathrm{t},\max }$	400 ns	max. transition time
$T_{\min }$	50 ns	min. delay time
$T_{\max }$	100 ns	max. delay time
$T_{\mathrm{p}}$	50 ns	pulse time

summarizes the main specifications and the selected control parameters. Even though 150 V GaN e-FETs are used (EPC2033) and hence a DC link voltage of up to 400 V would be possible, all experiments have been carried out with a reduced DC-link voltage of 100 V for safety reasons. Note that the DC voltage level does not impact the validity of the experimental verification (see also Appendix A). The converter is operated with 50 kHz switching frequency and a fixed 50% duty cycle. For demonstration purposes, a relatively large maximum peak-to-peak FC voltage ripple of 20 V is selected. With a maximum output current of 6.6 A and a maximum delay time of 100 ns, the required capacitance value of the FCs is 66 nF, see (22). The FCs are realized with C0G ceramic capacitors due to their linearity (1 kV CAA572C0G3A663J640LH).

The FC voltage measurement circuitry is placed on a separate PCB that is mounted on top of the main power board (cf. Figure 10a) and it can be disconnected for the tests with OL balancing. The power board, cf. Figure 10b contains the switching-cell daughter boards (carrying the GaN eFETs) on top and the FCs on the bottom. Furthermore, it contains the DC-link voltage and output current measurements circuitry. The Q2L controller and modulator are implemented in a high-performance Xilinx Zynq Z-7020 SoC.

6. Measurement Results

This section presents experimental results obtained with the 5L-FCC hardware demonstrator introduced in Section 5. In order to demonstrate the Q2L operation and the proposed concepts for FC voltage balancing, two synchronized LeCroy HDO4054A 12-bit oscilloscopes are used to measure waveforms of the DC-link voltage ($v_{\mathrm{dc}}$), all FC voltages ($v_{\mathrm{FC}\{1,2,3\}}$), and the half-bridge output voltage ($v_{\mathrm{o}}$) as well as the output current ($i_{\mathrm{o}}$), see Figure 9. Consequently, for each experiment two (temporally aligned) oscillograms are presented. Unless stated otherwise, resistive balancers $R_{\mathrm{b}}=30\mathrm{k}\Omega$ are connected in parallel to the switches.

6.1. Q2L Transitions

First, Q2L output voltage transitions are analyzed to confirm the Q2L operation and the description of charge and voltage increments presented in Section 2. Figure 11 shows measured waveforms during the switching transition with a positive slope of $v_{\mathrm{o}}$ and negative output current ($i_{\mathrm{o}}\approx I_{\mathrm{o}}=-5.9\mathrm{A}$), which results in a ZVS transition. Figure 12 shows waveforms of the switching transition with a positive slope of $v_{\mathrm{o}}$ and positive output current ($i_{\mathrm{o}}\approx I_{\mathrm{o}}=2.9\mathrm{A}$), which results in a HS transition. Based on the employed delay times and FC capacitance values, the voltage increments are calculated according to (5) and compared with the measured voltage changes (see oscillograms). The average absolute relative deviation of the estimated from the measured voltage changes is 3.7% for ZVS (cf. Figure 11) and 13.3% for HS (cf. Figure 12), thus confirming good accuracy of the estimation.

Figure 13 shows an exemplary CMS sequence $SE{Q}_{1\left(11\right)234}$ (events in cells ‘1000’) during a switching transition with negative slope of $v_{\mathrm{o}}$ and zero output current. It can be seen that the voltage change of FC₁ is about −0.7 V, whereas the expected voltage change calculated with (12) is −0.8 V, again showing good agreement with a deviation of 13% between calculation and measurement. Moreover, it can be noticed that also the voltages of FC₂ and FC₃ change slightly, i.e., by −0.11 V and −0.19 V, respectively, which is due to the non-idealities of the circuit.

6.2. Open-Loop Balancing

Next, we present measurement results confirming the OL balancing concept proposed in [29] and briefly described in Section 3. The modulation scheme from (21) is implemented with $T_{\mathrm{delay}}=100\mathrm{ns}$ for all cells. Consequently, all of the capacitors are charged/discharged with the same charge value in each transition, and open-loop balancing over two fundamental switching periods is achieved.

Figure 14 shows measured waveforms for split DC-link configuration with OL balancing and triangular current ($I_{\mathrm{o},\max }=7.0\mathrm{A}$, $I_{\mathrm{o},\min }=-5.8\mathrm{A}$). The average absolute relative deviation of the estimated peak-to-peak voltage ripple (19.4 V, cf. (22)) from the measured value is 3%, which corroborates the proposed model. However, note that in steady-state the mean values of the FC voltages deviate from the reference values (cf. (27)), on average by 4.9 V (15%). This is a consequence of the circuit’s equivalent impedances formed by the switches and the resistive balancers.

Figure 15 presents measured waveforms for full DC-link configuration with OL balancing during a negative load step from 100% to 67% of the nominal load ($I_{\mathrm{o}}=4.6\mathrm{A}\to 3.0\mathrm{A}$, $\Delta I_{\mathrm{pp}}=4\mathrm{A}$). Note that balancing is maintained despite the transient at the FCC bridge-leg’s output. It can be concluded that even without closed-loop voltage balancing, load steps within the nominal load range are not critical regarding FC voltage balancing thanks to correctly dimensioned FCs.

6.3. Closed-Loop Balancing

This section presents experimental verification of the CL balancing concept proposed in Section 4. First, operation with non-zero load currents is demonstrated, cf. Section 4.1, where the cell voltage tracking MPC with horizon one, see (31)–(35), is employed and $T_{\mathrm{delay}}=\{50,100\}\mathrm{ns}$ for all cells is used. Next, for the operation with zero load current, the FC voltage tracking MPC with a horizon of six steps ($N_{\mathrm{p}}=6$) is employed, see (36)–(41), and $T_{\mathrm{delay}}=T_{\mathrm{p}}=50\mathrm{ns}$ are used, cf. Section 4.2.

6.3.1. Balancing with Non-Zero Output Current

Figure 16 shows measured waveforms for split DC-link configuration with CL balancing and triangular current ($I_{\mathrm{o},\max }=5.9\mathrm{A}$, $I_{\mathrm{o},\min }=-5.8\mathrm{A}$). The average absolute relative deviation of the estimated peak-to-peak voltage ripple (4.5 V) from the measured value is 11%, which again corroborates the proposed model. Note that compared to OL balancing, an approx. $4\times$ smaller peak-to-peak voltage ripple is achieved for the following two reasons. First, with CL balancing in steady-state a minimum delay time ($T_{\mathrm{delay}}=50\mathrm{ns}$) is selected by the optimization, whereas with OL balancing the FCs operate with voltage ripples that are characteristic for the maximum delay time ($T_{\mathrm{delay}}=100\mathrm{ns}$), which is a consequence of the need to account for the the worst-case output current type (cf. Section 3). Second, in OL operation balancing occurs over 4 output voltage transitions, cf. (21), whereas in CL balancing, the optimization is carried out in every transition, ensuring minimum FC voltage ripple. Furthermore, under CL voltage balancing, the mean values of the FC voltages deviate in steady-state from the ideal reference values (cf. (27)) on average only by 1.9 V (3%), which results in more symmetric voltage sharing among the switches compared to OL balancing (cf. Figure 14).

Figure 17 presents measured waveforms for the full DC-link configuration with CL balancing during a negative load step from 100% to 67% of the nominal load (similar to Figure 15, $I_{\mathrm{o}}=4.6\mathrm{A}\to 3.0\mathrm{A}$, $\Delta I_{\mathrm{pp}}=4\mathrm{A}$). It can be seen that CL with MPC does not feature a symmetric balancing cycle of fixed length like OL, which explains why the voltage ripple shows a stochastic pattern. At a first glance, it seems as if the FC voltages in case of CL are not as well balanced as in the OL case, i.e., during nominal load operation, the maximum voltage ripples in CL are {11.4 V, 15.0 V, 8.5 V} compared to {13.9 V, 13.9 V, 13.9 V} in OL. This is, however, an intended result of the employed MPC that regulates the cell voltages (and not directly the FC voltages) and is addressed in more detail in the following.

Subsequently, Figure 18 demonstrates measured waveforms during the switch-over from OL balancing ($T_{\mathrm{delay}}=100\mathrm{ns}$) to the CL balancing ($T_{\mathrm{delay}}=\{50,100\}\mathrm{ns}$) in a full DC-link configuration with nominal output current $I_{\mathrm{o}}=4.6\mathrm{A}$. It is clear that the CL balancing enables better FC voltage reference tracking. Furthermore, based on the stored waveforms, we compute the corresponding cell voltages ${\mathit{V}}_{\mathrm{cell}}$ and Figure 19 presents the results. It can be observed for the OL balancing that even though the FC voltages are nicely balanced, the outermost cells, i.e., cell 1 and 4, operate with the maximum voltage ripple across their switches, whereas the middle cells (2 and 3) see an almost constant voltage. As can be seen from the example of voltage sharing on the lower arm of the HB (➀, cf. Figure 19) this leads to a large asymmetry of blocking voltages (e.g., $V_{\mathrm{S}1\mathrm{n}}$ = 36.6 V and $V_{\mathrm{S}4\mathrm{n}}$ = 15.0 V).

On the other hand, with CL balancing (worst-case example, cf. ➁ in Figure 19) the voltage sharing among the cells is symmetrical, which ensures well-defined voltage levels across the switches. To quantify those differences, we analyze the cell voltage error $({\mathit{V}}_{\mathrm{FC}}^{\ast }-{\mathit{V}}_{\mathrm{cell}})$ for OL and CL intervals, and average it for each cell over the number of considered half-periods. Considering all cells, the mean voltage deviation with CL balancing is approximately half that observed with OL balancing, i.e., 10.8% instead of 21.8%, respectively.

The proposed CL balancing concept compared to methods proposed in the literature, e.g., [31,32], avoids the operation with opposite voltage ripple on FCs, therefore, the switch voltages are not unbalanced by a maximum peak-to-peak voltage ripple of the FCs, which significantly improves the symmetry of the switches’ blocking voltages as shown above. This highlights the superiority of the proposed CL balancing concept.

6.3.2. Balancing with Zero Output Current

Figure 20 compares no-load FC voltage balancing for OL and CL balancing during full load shedding ($I_{\mathrm{o}}=5\mathrm{A}\to 0\mathrm{A}$) in a full DC-link configuration. Figure 20a shows the operation with resistive balancers and OL balancing, whereas Figure 20b illustrates the proposed CL controller concept employing CMS, cf. Section 4.2. Note the delay before CMS activation which is a consequence of the implemented hysteresis. Nevertheless, the CL controller achieves better dynamics as the steady-state is achieved after approx. 130 μs compared to appox. 540 μs settling time in case of resistive/OL balancing. It is noteworthy that the resistive balancers need to be selected considering the leakage currents of the switches and capacitors, therefore the time constant of the resistive balancing is determined by the circuitry and there are only limited tuning possibilities, especially if the losses in the balancing resistors must be limited. Furthermore, the resistive balancers are generating continuous losses, whereas in case of balancing with CMS, the zero-current hard-switching losses occur only during activation of CMS, i.e., several events at most over tens of switching transitions which leads to negligible average losses.

6.4. Start-Up and Shut-Down

In the last part of experimental validation we demonstrate voltage balancing during start-up and shut-down of the Q2L-5L-FCC. Note that in both experiments CL balancing is used.

Figure 21a presents measured waveforms in a full DC-link configuration with resistive balancers. The operation profile consists of the following intervals: A DC-link precharge via a resistor (disconnected load) → idle operation of Q2L-FCC after bridging the precharging resistor → connection of the load (nominal FC voltage ripple) → disconnection of the input supply and dissipation of the DC-link energy in the load. It can be noticed that the FC voltages are brought smoothly to and remain close to the their reference average values in the steady-state. Note that the jump in the capacitor’s voltage at the transition from precharge to idle interval is caused by the bridging of the precharging resistor. Furthermore, from the start of the idle interval the CL controller is active.

Figure 21b shows measured waveforms of a similar operation profile but in a split DC-link configuration without resistive balancers, however, in this case, the load is connected at all times. Again, it can be stated that the proposed CL balancing concept ensures balanced FC voltages and thus defined voltage levels on the switches in all operating modes of the Q2L-FCC.

7. Conclusions

This paper presents a new, comprehensive control concept for load-independent voltage balancing of flying capacitor converters (FCCs) operated in quasi-2-level mode (Q2L-FCC). This new and fully experimentally-verified concept ensures well-defined FC voltages and equal blocking voltages across the series-connected switches with and without load current flowing in the bridge-leg’s output terminal.

The proposed closed-loop voltage balancing control concept comprises two methods which are activated depending on the output current of the bridge-leg. In case of a non-zero output current, a first method of active cell voltage balancing involves a model predictive controller (MPC) that selects the most suitable sequence of FC cell commutations within one Q2L transition (1-step horizon) from all possible permutations by minimizing the predicted deviation from the reference values. On the other hand, when the output current is zero, a novel method to balance the FC voltages by means of cell multiple switching (CMS) is used. CMS utilizes the fact that during zero-current hard-switching of a switch, the commutation loop current leads to an exchange of charge (subtraction of charge in a cell’s input-side capacitor and addition of that charge to the output-side capacitor) which is equal to the charge stored in the switch’s parasitic capacitance. By adding additional switching actions during a Q2L transition, the FC voltages can be adjusted. Again, an MPC approach is utilized to select the optimum CMS sequence, however, using FC voltage reference tracking over a 6-step horizon.

The proposed voltage balancing control concept is thoroughly validated with a 5-level FCC half-bridge demonstrator for hard-switching and soft-switching output voltage transitions, during load transients, as well as for start-up and shut-down operation modes. The hardware experiments demonstrate an excellent average FC voltage tracking as well as symmetric cell voltages. More importantly, the results prove the validity of the proposed description of charge and voltage increments in FCs. The presented closed-loop cell voltage control concept, compared to open-loop (passive) balancing or active balancing directly controlling FC voltages, results in voltages across the switches that are close to the ideal values and optimum FC voltage ripples. The versatility of the proposed solution comes at the price of the required measurement circuitry to sense the FC voltages. In return, however, the proposed controller is computationally efficient and can be easily implemented in an FPGA, partially using offline-generated look-up tables.

Alternatively, the future research should focus on the FC voltages estimation from the switching sequence and the output voltage since the FC voltages combined with the DC-link voltage appear in the output voltage during the Q2L transitions, which would enable ‘sensor-less’ FC voltages balancing.

The proposed closed-loop voltage balancing turns the Q2L-FCC into a robust versatile half-bridge power semiconductor stage for various hard-switched and soft-switched applications such as AC-DC rectifiers and isolated DC-DC converters, where the system voltages exceed the voltage ratings of available power semiconductors.