Conceptualization and Analysis of a Next-Generation Ultra-Compact 1.5-kW PCB-Integrated Wide-Input-Voltage-Range 12V-Output Industrial DC/DC Converter Module

Abstract

The next-generation industrial environment requires power supplies that are compact, efficient, low-cost, and ultra-reliable, even across mains failures, to power mission-critical electrified processes. Hold-up time requirements and the demand for ultra-high power density and minimum production costs, in particular, drive the need for power converters with (i) a wide input voltage range, to reduce the size of the hold-up capacitor, (ii) soft-switching over the full input voltage and load ranges, to achieve low losses that facilitate a compact realization, and (iii) complete PCB-integration for low-cost manufacturing. In this work, we conceptualize, design, model, fabricate, and characterize a $1.5$ $\mathrm{k}$$\mathrm{W}$, 12 $\mathrm{V}$-output DC/DC converter for industrial power supplies that is required to operate across a wide 300 $\mathrm{V}$–430 $\mathrm{V}$ input voltage range. This module utilizes an LLC-based control scheme for complete soft-switching and a snake-core transformer to divide the output current with a balanced flux among multiple secondary windings. Detailed loss models are derived for every component in the converter. The converter achieves close to 96% peak efficiency with a power density of 337 $\mathrm{W}$ ${\mathrm{in}}^{-3}$ ($20.6$ $\mathrm{k}$$\mathrm{W}$/${\mathrm{d}\mathrm{m}}^{-3}$), excellent matching to the derived loss models, and zero-voltage switching even down to zero load. The loss models are used to identify improvements to further boost efficiency, the most important of which is the minimization of delay times in synchronous rectification, and a subsequent improved $1.5$ $\mathrm{k}$$\mathrm{W}$ hardware module eliminates nearly 25% of converter losses for a peak efficiency of nearly 97% with a power density of 308 $\mathrm{W}$ ${\mathrm{in}}^{-3}$ ($18.8$ $\mathrm{k}$$\mathrm{W}$ ${\mathrm{dm}}^{-3}$). Two $1.5$ $\mathrm{k}$$\mathrm{W}$ modules are then paralleled to achieve 3 $\mathrm{k}$$\mathrm{W}$ output power at 12 $\mathrm{V}$ and 345 $\mathrm{W}$ ${\mathrm{in}}^{-3}$ ($21.1$ $\mathrm{k}$$\mathrm{W}$ ${\mathrm{dm}}^{-3}$) with ideal current sharing between the secondary outputs and no drop in efficiency from a single module, an important characteristic enabled by the novel snake-core transformer.

1. Introduction

The industrial environment of the future is increasingly electric, with factory automation and special-purpose electrified processes defining the next-generation of manufacturing environments, often referred to as Industry 4.0 [1]. Power supplies for these applications operate with highly-demanding specifications, especially on reliability and hold-up time, as mere moments of power supply downtime may translate to costly hours of downtime for the plant. For the grid-connected power supply of Figure 1a, the low-voltage output ($V_{\mathrm{o}}$) must bridge short mains faults and, with a complete mains failure, hold-up $V_{\mathrm{o}}$ long enough for a safe shutdown of the digital and physical systems (see Figure 1b). This is so critical for continuous line operation that batteries are integrated into commercially-available industrial power supplies in this class to extend hold-up time [2].

These supplies may drive, for example, CNC steppers or servo systems, and the low-voltage output must deliver hundreds of amperes of current with exacting demands that extend beyond the hold-up time requirements [3]: (i) power density, with real estate at a premium and supply cabinets already consuming space otherwise available for functional equipment, (ii) low initial and/or installation costs as the critical metric for adoption, and (iii) high and flat efficiency curves, with supplies rarely operating at full load and heat generation in cabinets driving cooling needs [2,4].

In this work, we focus on the high-step-down ratio DC/DC converters needed in these applications. The requirements of this converter module, with $1.5$ $\mathrm{k}$$\mathrm{W}$ output power at 12 $\mathrm{V}$, introduce significant challenges in design when striving for ultra-high power density (targeted for 300 $\mathrm{W}$ ${\mathrm{in}}^{-3}$, or $18.3$ $\mathrm{k}$$\mathrm{W}$ ${\mathrm{dm}}^{-3}$) and full PCB-integration (including magnetics), a requirement for low-cost and high-reliability. The strict height dimension of $1.2$ $\mathrm{c}$$\mathrm{m}$ (given with other key specifications in

Table 1. DC/DC module design specifications.

Full-load output power ($P_{\mathrm{o}}$)	$1.5$ $\mathrm{kW}$
Output voltage ($V_{\mathrm{o}}$)	12 $\mathrm{V}$
Full-load output current ($I_{\mathrm{o}}$)	125 $\mathrm{A}$
Power density	300 $\mathrm{W}$ ${\mathrm{in}}^{-3}$ ( $18.3$ $\mathrm{k}$$\mathrm{W}$ ${\mathrm{dm}}^{-3}$)
Footprint (l × w)	10 $\mathrm{c}$$\mathrm{m}$ × 7 $\mathrm{c}$$\mathrm{m}$
Height (h)	$1.2$ $\mathrm{c}$$\mathrm{m}$
Input voltage range ($V_{\mathrm{dc},\min }-V_{\mathrm{dc},2}$)	300 $\mathrm{V}$–430 $\mathrm{V}$
PCB-integrated	Yes
Full ZVS	Yes
Parallel-able	Yes

) further drives magnetics design complexity with only very thin form factors available for these PCB-integrated components.

The hold-up time requirement ($t_{\mathrm{e}}-t_{\mathrm{f}}=6 \mathrm{m}\mathrm{s}$) could be met with additional converters, for example with (i) a partial-power pre-regulation converter and a fixed-voltage-ratio DC/DC converter [5], (ii) a hold-up time extension circuit [6], or (iii) a reverse-feeding concept [7]. Each of these add complexity and size in the form of an additional power stage, and we instead seek to meet the 6 $\mathrm{m}$$\mathrm{s}$ hold-up time requirement through the combination of $C_{\mathrm{dc}}$ and a wide-input-voltage range DC/DC module. If we take a typical specific capacitance of 267 $\mathsf{\mu }$$\mathrm{F}$ ${\mathrm{in}}^{-3}$ (for box-volume, ultra-compact, 450 $\mathrm{V}$ electrolytic capacitors, e.g., 450USK1000MEFCSN35X55), $C_{\mathrm{dc}}=1 \mathrm{m}\mathrm{F}$ would already consume 15% of the allotted volume in a 100 $\mathrm{W}$ ${\mathrm{in}}^{-3}$ ($6.1$ $\mathrm{k}$$\mathrm{W}$ ${\mathrm{dm}}^{-3}$) next-generation power supply, and the DC/DC converter would need to operate from $V_{\mathrm{dc},\min }=300 \mathrm{V}$ to $V_{\mathrm{dc},2}=430 \mathrm{V}$, a wide-input-voltage range. We take this input voltage range as our requirement, knowing that we cannot achieve the required converter power density with any additional capacitance to narrow this range. With our power density specification prescribing such a high switching frequency that soft-switching is required, then, we encounter the major design challenge of the work: the control and topology of a wide-range, complete soft-switching DC/DC converter to meet, simultaneously, the hold-up time and power density specifications.

Indeed, upon reviewing the literature, there is no prior study that meets the demanding specifications of these next-generation Industry 4.0 power converters. In particular, wide-input-voltage range, complete soft-switching, and high-current 12 V output with PCB-integrated magnetics are rarely found together (see

Table 2. Survey of published converters near the design specifications of the DC/DC module considered in this paper. Efficiency is given at nominal load ($1.0P_{\mathrm{o}}$) and 50% of nominal load ($0.5P_{\mathrm{o}}$).

Ref.	Topology	Full ZVS?	${\mathit{v}}_{\mathbf{dc}}$	${\mathit{V}}_{\mathbf{o}}$/${\mathit{I}}_{\mathbf{o}}$	Power Density	Eff. ($1.0{\mathit{P}}_{\mathbf{o}}$)	Eff. ($0.5{\mathit{P}}_{\mathbf{o}}$)	PCB- int.?
[14,16]	LLC	Yes	380 $\mathrm{V}$	12 $\mathrm{V}$/83 $\mathrm{A}$	700 $\mathrm{W}$ ${\mathrm{in}}^{-3}$	$96.5$%	$97.1$%	Yes
[17]	LLC	Yes	380 $\mathrm{V}$	12 $\mathrm{V}$/67 $\mathrm{A}$	900 $\mathrm{W}$ ${\mathrm{in}}^{-3}$	$97.2$%	$97.6$%	Yes
[15]	LLC	Yes	200 $\mathrm{V}$–420 $\mathrm{V}$	12 $\mathrm{V}$/83 $\mathrm{A}$	—	$91.2$%	$96.0$%	No
[15]	PSFB	No	200 $\mathrm{V}$–420 $\mathrm{V}$	12 $\mathrm{V}$/83 $\mathrm{A}$	—	$92.4$%	$96.0$%	No
[21]	PSFB	Yes	270 $\mathrm{V}$	22 $\mathrm{V}$/68 $\mathrm{A}$	—	$93.2$%	$96.0$%	No
[22]	PSFB	Yes	230 $\mathrm{V}$–430 $\mathrm{V}$	14 $\mathrm{V}$/150 $\mathrm{A}$	170 $\mathrm{W}$ ${\mathrm{in}}^{-3}$ (target)	$95.0$%	$96.0$%	Yes
[19]	PSFB	Yes	330 $\mathrm{V}$–420 $\mathrm{V}$	12 $\mathrm{V}$/83 $\mathrm{A}$	300 $\mathrm{W}$ ${\mathrm{in}}^{-3}$ (package)	$97.8$%	$99.1$%	Yes
[18]	Double-clamp	Yes	160 $\mathrm{V}$–420 $\mathrm{V}$	$13.8$ $\mathrm{V}$/130 $\mathrm{A}$	900 $\mathrm{W}$ ${\mathrm{in}}^{-3}$ (package)	$93.0$%	$93.5$%	Yes
[8]	Half-bridge	No	150 $\mathrm{V}$–400 $\mathrm{V}$	12 $\mathrm{V}$/167 $\mathrm{A}$	—	$91.8$%	$94.7$%	No
[9]	DAB	No	240 $\mathrm{V}$–450 $\mathrm{V}$	12 $\mathrm{V}$/182 $\mathrm{A}$	25 $\mathrm{W}$ ${\mathrm{in}}^{-3}$	$93.5$%	$95.0$%	No
[10]	DSAB	No	350 $\mathrm{V}$–410 $\mathrm{V}$	12 $\mathrm{V}$/25 $\mathrm{A}$	≈$20 \mathrm{W}{\mathrm{in}}^{-3}$	$95.9$%	$97.0$%	Yes
[12]	LLC	Yes	280 $\mathrm{V}$–380 $\mathrm{V}$	48 $\mathrm{V}$/2 $\mathrm{A}$	≈$30 \mathrm{W}{\mathrm{in}}^{-3}$	$94.0$%	$95.0$%	Yes
[13]	Morphing LLC	Yes	100 $\mathrm{V}$–400 $\mathrm{V}$	48 $\mathrm{V}$/17 $\mathrm{A}$	—	$94.3$%	—	No
[20]	PSFB	Yes	300 $\mathrm{V}$–400 $\mathrm{V}$	50 $\mathrm{V}$/24 $\mathrm{A}$	—	$93.9$%	$93.9$%	No
Target		Yes	300 $\mathrm{V}$–430 $\mathrm{V}$	12 $\mathrm{V}$/125 $\mathrm{A}$	300 $\mathrm{W}$ ${\mathrm{in}}^{-3}$			Yes

). Buck-based topologies support a wide-input-voltage range, but are hard-switched (over at least part of the regime) and therefore have low efficiency [8,9,10,11]. LLC-based converters are soft-switched with high efficiencies even at high switching frequencies, but are limited by a narrow input voltage range [12,13,14,15,16,17] that, in this application, would result in an unreasonably-large DC-link capacitor to meet hold-up specifications. At the extreme of narrow input voltage ranges, DC transformers (“DCX”) with a fixed voltage conversion ratio require, at a minimum, a differential-power pre-regulation stage [5]. The only prior art with a wide-input range, soft-switching over the complete range, and high-current output with PCB-integrated magnetics has either a maximum efficiency of only 93% [18] or low power density when the necessary passives are included [19] ([19] also features lower output current, which is simpler to PCB-integrate). Finally, designs with higher output voltages (e.g., $V_{\mathrm{o}}=48 \mathrm{V}$ [12,13,20]) are much simpler to PCB integrate (with $16\times$ lower conduction losses on the secondary side) but do not meet the entrenched and ubiquitous 12 $\mathrm{V}$ buses that currently dominate industrial applications.

The goal here, then, is to conceptualize, design, model, and construct a next-generation industrial power supply that meets the demanding specifications of this high-reliability application while maximizing the DC/DC converter efficiency (Table 1), a combination that has not been realized previously in the literature. First, we identify a suitable low-complexity circuit topology and control scheme (Section 2.1) to operate across the wide-input-voltage range with complete soft-switching, implementing a new hybrid wide-input-range LLC control for a topology that includes a full-bridge primary and a matrix transformer for multiple high-current outputs. For each component—and especially for the PCB-integrated magnetics, including the novel snake-core transformer—we derive detailed loss and volume models that permit component-level Pareto optimizations, and present an optimal design for the 300 $\mathrm{W}$ ${\mathrm{in}}^{-3}$ power density target of the demonstrator module (the remainder of Section 2). In Section 3, we verify the design with a $1.5$ $\mathrm{k}$$\mathrm{W}$ demonstrator, achieving nearly 96% DC/DC efficiency, 337 $\mathrm{W}$ ${\mathrm{in}}^{-3}$ power density with PCB-integrated magnetics, excellent matching to the derived loss models, and zero-voltage switching even down to zero load. In Section 4, we find the efficiency limitations for the hardware prototype and analyze the sensitivity of this barrier to component designs and architectures, guiding a redesign of an improved converter module with 25% lower total losses. In Section 5, we characterize this improved hardware demonstrator and showcase ideal current sharing among the secondary phases with two paralleled modules, a critical characteristic for high-current outputs that is uniquely enabled by the snake-core architecture. Section 6 concludes the paper with a discussion of fundamental efficiency limits for these high-output-current, wide-input-voltage range converters that will be critical to the electrification of Industry 4.0.

2. DC/DC Converter Design

We first detail the design of the DC/DC converter module, which has the topology shown in Figure 2a, with the secondary split into four paralleled outputs to reduce the output current stress imposed on a single secondary winding and rectifier stage. We analyze the gain range and controllability before moving to the two most challenging passive components: the PCB-integrated transformer and primary inductor, both of which must achieve ultra-high copper utilization within the constraints of PCB fabrication methods. This copper utilization is so critical to the converter performance that intermediate test setups are built to validate the analytical approach and optimization procedures. Finally, we detail the capacitor and power semiconductor selection to complete the design analysis of this demanding wide-input-voltage range, high-output-current, PCB-integrated DC/DC converter.

2.1. Topology, Gain Analysis, and Control

As discussed in Section 1, the challenge is to combine the controllability of buck-based converters, which enables a wide-input-voltage range, with the high efficiency of LLC-based resonant topologies that feature soft-switching (and specifically zero-voltage-switching, or ZVS) across the full load and voltage ranges.

2.1.1. Topology

The topology challenges are driven by the combination of wide-input-voltage range (needed for hold-up time requirements) and complete soft-switching, as discussed in Section 1. We seek a low-complexity topology and control scheme, which eliminates approaches such as (i) DCX transformers, which require pre-regulation to fix the input voltage to the DC/DC module [5], (ii) additional hold-up time extensions circuits, which require a full additional converter module [6], and (iii) reverse-feeding for hold-up time, which adds significant control complexity to the DC/DC module [7]. Instead, we aim to use a soft-switched LLC approach that can be controlled—with minimal complexity—across a wide gain range while maintaining soft-switching, and draw inspiration from matrix transformers used in server power supplies (e.g., [14]) to divide the high output current among multiple windings and rectifiers.

A full-bridge topology, as shown in Figure 2a, is chosen to excite the primary-side resonant tank. Relative to the half-bridge topology, the full-bridge has half of the primary-side current for a given power (with a tank excitation of $\pm v_{\mathrm{dc}}$, rather than $\pm \frac{1}{2}{v}_{\mathrm{dc}}$ for the half-bridge) and an additional control variable in the phase-shift between the two bridge legs, during which a variable-length voltage of $0 \mathrm{V}$ can be applied to the tank. A center-tapped synchronous rectifier is selected for the secondary side, a topology that features a low semiconductor count, zero-voltage-switching, and no high-current output inductor. The equivalent circuit is shown in Figure 2b, including the LLC tank ($C_{\mathrm{r}}$, $L_{\mathrm{r}}$, and $L_{\mathrm{m}}$), the reflected, equivalent load resistance ($R_{\mathrm{p}}$), and the fundamental of the tank excitation ($v_{\mathrm{AB}}$). The proposed converter’s footprint is introduced in Figure 2c, where the matrix transformer with integrated synchronous rectifiers and output capacitors is preliminary built as a square block that sets the converter’s width (w) and height (h). The PCB inductor should also be square and therefore, together with the primary-side semiconductors and control circuitry, defines the footprint’s length (l).

2.1.2. Gain

For LLC converters, the fundamental-harmonic approximation (FHA) is typically used [23,24] to describe the gain, or the output-to-input voltage ratio ($v_{\mathrm{p}}/v_{\mathrm{AB}}$), as a function of the control variable: switching frequency ($f_{\mathrm{s}}$). The gain as a function of switching frequency (normalized by the transformer turns ratio, n) is shown in Figure 3, where the FHA is compared to the exact solution obtained through circuit simulation for the proposed design parameters. The FHA is used primarily for the design of the unity gain point and to assess the gain in the boost region, with margin implicit because the actual gain under boost conditions is always higher than that predicted by the FHA (as shown in Figure 3). Under the FHA, the gain can be approximated as:

$$\frac{n{V}_{\mathrm{o}}}{v_{\mathrm{dc}}}=\frac{(m-1){\left(\frac{f_{\mathrm{s}}}{f_{\mathrm{r}}}\right)}^2}{\sqrt{{\left[m{\left(\frac{f_{\mathrm{s}}}{f_{\mathrm{r}}}\right)}^2-1\right]}^2+Q^2{(m-1)}^2{\left(\frac{f_{\mathrm{s}}}{f_{\mathrm{r}}}\right)}^2{\left[{\left(\frac{f_{\mathrm{s}}}{f_{\mathrm{r}}}\right)}^2-1\right]}^2}}$$

(1)

$$f_{\mathrm{r}}=\frac{1}{2\pi \sqrt{L_{\mathrm{r}}{C}_{\mathrm{r}}}}$$

(2)

$$m=1+\frac{L_{\mathrm{m}}}{L_{\mathrm{r}}}$$

(3)

$$Q=\frac{Z_{\mathrm{r}}}{R_{\mathrm{p}}}$$

(4)

$$Z_{\mathrm{r}}=\sqrt{\frac{L_{\mathrm{r}}}{C_{\mathrm{r}}}}$$

(5)

$$R_{\mathrm{p}}=\frac{8n^2}{{\pi }^2}\frac{V_{\mathrm{o}}^2}{P_{\mathrm{o}}}.$$

(6)

Each parameter relates to a particular design constraint: the transformer turns ratio, n, defines the operation mode for the converter (buck, boost, or both), $L_{\mathrm{m}}$ restricts the maximum gain, $L_{\mathrm{r}}$ defines the selectivity of the tank [25] and therefore the required switching frequency range for a given gain, and $C_{\mathrm{r}}$ is used to tune the desired resonant frequency. Each of these parameters, though, also has constraints on its selected value: n must be a multiple of the number of output stages (secondary transformers) for symmetry, $L_{\mathrm{r}}$ must be optimized for low volume, $C_{\mathrm{r}}$ must have a withstand voltage that is achievable with commercially-available capacitors, and $L_{\mathrm{m}}$ should be large to minimize the magnetizing current and the associated conduction losses.

Here, we know that a combination of buck and boost modes will be required to achieve the wide-input-voltage range, and the nominal input voltage of $v_{\mathrm{dc}}=400 \mathrm{V}$ is placed closed to the resonant frequency, where $f_{\mathrm{s}}=f_{\mathrm{r}}$ and $n{V}_{\mathrm{o}}/v_{\mathrm{dc}}=1$ (see (1)). This results in $n=v_{\mathrm{dc}}/V_{\mathrm{o}}=400 \mathrm{V}/12 \mathrm{V}=33.33$, with $n=32$ chosen for a symmetric design of the matrix transformer ($n{V}_{\mathrm{o}}=384 \mathrm{V}$). From here, $L_{\mathrm{r}}=24 \mathsf{\mu }\mathrm{H}$ is selected to compromise between inductor volume and the maximum operating frequency at light load (with the inductor design detailed in Section 2.3), mandating $L_{\mathrm{m}}=110 \mathsf{\mu }\mathrm{H}$ to achieve the maximum gain at the minimum input voltage of $v_{\mathrm{dc}}=300 \mathrm{V}$. A resonant frequency of 310 $\mathrm{k}$$\mathrm{Hz}$ is selected to balance the demanding efficiency and power density metrics of Table 1, which results in $C_{\mathrm{r}}=11 \mathrm{n}\mathrm{F}$. This design achieves full ZVS at all load and input-voltage conditions, a requirement to approach the required metrics—a hard-switching half-bridge employing IGLD60R070D1 GaN HEMTs at $v_{\mathrm{dc}}=400 \mathrm{V}$ and 310 $\mathrm{k}$$\mathrm{Hz}$ would generate switching losses of one third of the allowable losses in the complete DC/DC converter for 96% efficiency at 50% load!

2.1.3. Control

Finally, returning to the goal of a simplicity of control that approaches that of buck-based converters, we propose a hybrid control loop and scheme (shown in Figure 4). Variable switching frequency control in continuous conduction mode (with the design tradeoffs between boundary and continuous conduction mode detailed in [26]) is implemented based on a comparison between the measured output voltage and requested output voltage, with the gain monotonic above the peak frequency around 200 $\mathrm{k}$$\mathrm{Hz}$ (see Figure 3). An off-the-shelf gate-driver IC with an embedded dead-time generator drives the GaN full-bridge ($g_1-g_4$) with the corresponding PWM signals from the MCU ($s_1-s_4$). A digital PI controller ($C_{\mathrm{PI}}$) drives the sensed output voltage ($V_{\mathrm{o}}$) to the reference value ($V_{\mathrm{o}}$*) by adjusting the period of the MCU timer to trigger $s_1-s_4$. When the control variable (u) has a lower value than the minimum user-defined switching period ($per$), the control leaves continuous conduction mode (CCM, Figure 4b) and enters discontinuous conduction mode (DCM, Figure 4c), where the frequency is now fixed and a phase shift between $s_1$/$s_2$ and $s_3$/$s_4$ is introduced. This simple control scheme achieves the wide-input-voltage range and complete ZVS with only an isolated low-voltage measurement, a 12 $\mathrm{V}$-to-$3.3$ $\mathrm{V}$ auxiliary supply, a hardware-implemented dead-time generator, and the 32-pin ST Arm Cortex M4 as the MCU.

2.2. PCB-Integrated Transformer

With the topology, control techniques, and gain range determined, we turn to the design of the passive components. With 125 $\mathrm{A}$ at the 12 $\mathrm{V}$ output and the automated manufacturing requirement for full PCB integration, the multi-output transformer requires an ultra-low AC-to-DC resistance ratio ($R_{\mathrm{ac}}/R_{\mathrm{dc}}$), high copper area within the constraints of the PCB geometry, and a tight, compact layout with the synchronous rectifier. The multi-output matrix transformer approach for high-current, low-voltage outputs is known from server power supplies (e.g., [17]), but does not achieve ideal flux balancing among multiple paralleled outputs [26,27]. Here, we expand on the novel snake-core transformer concept, implementing a compact, low-loss, and balanced transformer that achieves perfect current sharing among one or many modules (as showcased later, in Section 5).

Any multi-output transformer, including the snake-core transformer, with four sub-transformers (see Figure 2a) benefits more from the PCB integration if built with side symmetry, i.e., in a squared shape, as proposed in Figure 2c. This allows compactness of PCB windings and the shortest path for the magnetic flux (lower core losses). The transformer’s side length and height are defined by the given values of width (w) and height (h) of the converter, previously specified in Table 1.

2.2.1. Winding Optimization and Losses

Firstly, the number of turns for the secondary winding ($N_{\mathrm{s}}$) is optimized. With the winding geometry parameters shown in Figure 5a, the current density in the secondary winding is:

$$\begin{array}{c}\hfill \widehat{J}=\frac{\pi I_{\mathrm{o}}{N}_{\mathrm{s}}}{2A_{\mathrm{w}}}\end{array}$$

(7)

and the flux density in the core is:

$$\begin{array}{c}\hfill \widehat{B}=\frac{V_{\mathrm{o}}}{4f_{\mathrm{s}}{A}_{\mathrm{c}}{N}_{\mathrm{s}}}.\end{array}$$

(8)

With the high output current requirement, a single turn ($N_{\mathrm{s}}=1$) is optimal for each secondary-side winding, with winding loss minimized at the expense of increased core loss. The optimal number of sub-transformers is selected to balance the copper and core losses. We eliminate the choices with an odd number of secondary windings, which would yield an asymmetrical structure, a complex core shape, or much higher core losses. 1 or 2 sub-transformers results in much higher copper losses, while 8 sub-transformers would yield a complicated core structure with high core losses. Therefore, for the particular constraints of this design—and especially around PCB integration, which limits the available copper thickness—a proper copper-to-core loss ratio is achieved with 4 sub-transformers, as shown later with experimental results.

This multi-output, matrix structure with 4 paralleled outputs reduces the copper loss by a factor of 4 over a single output (again at the cost of increased core losses) with the same footprint area for the secondary-side winding ($A_{\mathrm{t}}$), as the current density reduces by a factor of 2 (see Figure 5b). Ultimately, the optimal $A_{\mathrm{w}}$-to-$A_{\mathrm{c}}$ ratio between winding window area and core cross-section area must be selected based on a Pareto-optimization from copper and core loss models, which are developed and detailed later in this section.

The high-current outputs must then be tightly-integrated into the remainder of the converter design. The transformer configuration, layer stackup, and secondary-side layout is detailed in Figure 6. In Figure 6a, a cutaway 3-D view shows the secondary-side semiconductors directly on top of the low-voltage windings (“LV Wind”) for low termination losses, an adjacent output capacitance ($C_{\mathrm{o}}$) to minimize the commutation loop, and the full-bridge excitation input and chain through $L_{\mathrm{r}}$ to the high-voltage winding (“HV Wind”). The core configuration is shown in Figure 6b, with the losses and design detailed in the next sub-section. Figure 6c shows the vertical stackup and Figure 6d shows the layer-by-layer copper for the 10-layer, $2.4$ $\mathrm{m}$$\mathrm{m}$ PCB that can be fabricated using standard processes, including the low-voltage, high-current layers of TL/L2 and L9/BL, the high-voltage layers of L5/L6, and the shielding layers of L3 and L8.

The shielding layers (connected to $v_{\mathrm{dc}}$-) are included to minimize the capacitance between the high-voltage and low-voltage sides of the transformer; these shielding layers, however, add common-mode capacitance that appears between the high-voltage excitation and high-voltage ground, or, analyzing the AC-equivalent circuit, add to the $C_{\mathrm{oss}}$ of the high-voltage switches. In order to reduce this undesired parasitic capacitance, layers L4 and L7 have been removed from the transformer’s layout, increasing the distances between L5/L6 and L3/L8. From the geometry and the permittivity of FR4 (${ϵ}_r=4.5$), we calculate $C_{\mathrm{pri}-\mathrm{shi}}=550 \mathrm{p}\mathrm{F}$ and measure $C_{\mathrm{pri}-\mathrm{shi}}=554 \mathrm{p}\mathrm{F}$ (with the bridge-legs shorted together, measured to high-voltage ground). Despite the removal of layers L4/L7, this is still a significant contribution to the $C_{\mathrm{oss}}$ of the selected high-voltage GaN switches and must be included in the ZVS and loss analyses.

The primary-side winding is then designed with the configuration shown in Figure 6d, with high-voltage windings around each core leg for high coupling and a balanced flux (design detailed in [27]). The total DC resistance of each multi-turn winding is:

$$R=\sum _{i=0}^{k-1}\frac{2\pi }{\sigma h_{\mathrm{Cu}}ln\left(r_{(\mathrm{i}+1)}/r_{\left(\mathrm{i}\right)}\right)},$$

(9)

with the optimal turn radii (see Figure 7a), adapted from [17]) as:

$$r_{\left(\mathrm{i}\right)}=\sqrt[k]{r_0^{(\mathrm{k}-\mathrm{i})}{r}_{\mathrm{k}}^{\left(\mathrm{i}\right)}},$$

(10)

where k is the number of turns per layer and per sub-transformer in the matrix structure. This optimized design is implemented for the high-voltage side windings to achieve the turns ratio (with $N_{\mathrm{s}}=1$) of $n=32$ selected in Section 2.1, which leads to $k=4$: 32 turns implemented in 2 PCB layers and wound around the 4 core limbs (4 sub-transformers, $T_1-T_4$ in Figure 2a).

With the winding a critical driver of efficiency and losses, a test setup is built to validate the spiral radii optimization and expected winding resistances. An impedance analyzer in the circuit of Figure 7c measures the transformer impedance ($Z_{\mathrm{p}}$) across frequency from the primary-side terminals with short-circuited secondary-side windings for two layer configurations: (i) both primary (HV) and secondary-side (LV) windings are built with the standard 2 oz copper thickness of 70 $\mathsf{\mu }$$\mathrm{m}$ and (ii) 270 $\mathsf{\mu }$$\mathrm{m}$ LV windings for reduced conduction losses. The results (shown as AC-to-DC resistance ratio) are reported in Figure 7b, with the theoretical approach well-validated by the experimental results. The measured $R_{\mathrm{ac}}$/$R_{\mathrm{dc}}$ values across frequency are modeled by empirical linear functions (dashed lines) for later use in the winding resistance calculation.

With this same test setup, the calculated resistances of the primary and secondary windings are compared to the measured values in

Table 3. Comparison between predicted and measured winding losses for the PCB-integrated transformer. All parameters at $T=25 {}^{\circ }\mathrm{C}$.

	Freq. (kHz)	${\mathit{R}}_{\mathbf{calc}}$ (kHz)	${\mathit{R}}_{\mathbf{meas}}$ (m$\mathbf{\Omega }$)	Error (%)
$R_{\mathrm{prim}}$	DC	244.2	256.5	−4.8
$R_{\sec }$	DC	0.2085	0.2166	−3.7
$R_{\mathrm{prim}}+n^2{R}_{\sec }$	300	755.2	758.0	−0.4
$R_{\mathrm{prim}}+n^2{R}_{\sec }$	500	892.5	906.6	−1.6
$R_{\mathrm{prim}}+n^2{R}_{\sec }$	700	1030	1027	0.3
$R_{\mathrm{L}2+\mathrm{L}9}$	DC	0.03622	0.03554	1.9

. Across the complete operating range of frequency, the predicted current-weighted sum of the primary and secondary resistance ($R_{\mathrm{prim}}+n^2{R}_{\sec }$) is within 2% of the measured value, indicating precise loss models for the windings that correctly describe the implemented PCB-integrated transformer and the frequency-dependent effects. The resistance of layers L2 and L9—that connect all sub-transformers in parallel (see Figure 6d)—was obtained by FEM simulations (COMSOL Multiphysics 5.4) with an error between measured and FEM-calculated values under 2% (cf. Table 3). With the winding optimized and the loss model validated, we move to the transformer core design and loss optimization.

2.2.2. Core Optimization and Losses

The matrix transformer is implemented with the snake-core proposed in [27] and expanded upon in [26], where the winding configuration—with a single, deterministic flux path through the high-permeability ferrite (TDK N49)—guarantees well-balanced flux among the paralleled secondary windings. The core configuration is shown in Figure 6b, with cylindrical through-PCB limbs to avoid current crowding on windings due to sharp edges, low-profile yokes following components’ height, and total required air gap distributed among core yokes, calculated as:

$$l_{\mathrm{g}}=\frac{{\mu }_0{A}_{\mathrm{c},\mathrm{yoke}}}{n^2{L}_{\mathrm{m}}}.$$

(11)

The core is built with different cross-sectional areas for the yokes and for the through-PCB limbs (see

Table 4. Design characteristics of the optimized transformer and inductor.

	Transformer	Inductor
Winding width	$8.6$ $\mathrm{m}$$\mathrm{m}$	$2.2$ $\mathrm{m}$$\mathrm{m}$
Limb area ($A_{\mathrm{c},\mathrm{limb}}$)	48 $\mathrm{m}$$\mathrm{m}$${}^2$	36 $\mathrm{m}$$\mathrm{m}$${}^2$
Yoke area * ($A_{\mathrm{c},\mathrm{yoke}}$)	71 $\mathrm{m}$$\mathrm{m}$${}^2$	149 $\mathrm{m}$$\mathrm{m}$${}^2$
Air-gap length ($l_{\mathrm{g}}$)	$0.83$ $\mathrm{m}$$\mathrm{m}$	$0.33$ $\mathrm{m}$$\mathrm{m}$

* at the air gap.

), with $A_{\mathrm{c},\mathrm{limb}}$ selected to optimize core and winding losses for a fixed total transformer area ($A_{\mathrm{t}}$)—Pareto optimization of Section 2.2.3—and $A_{\mathrm{c},\mathrm{yoke}}$ made as large as the combination of $A_{\mathrm{t}}$ and the specified converter height would allow. We recall that $L_{\mathrm{m}}=110 \mathsf{\mu }\mathrm{H}$ and $n=32$ were selected in Section 2.1 to meet the gain and voltage range specifications, yielding a total air gap of $l_{\mathrm{g}}=0.83 \mathrm{m}\mathrm{m}$.

Eddy-current losses and hysteresis losses are included in the core loss model. The flux density in the transformer core at a given operating point is given by (8), with the yoke and limb flux densities considered separately as their cross-sectional areas are different (see Table 4), resulting in $B_{\mathrm{limb}}=196 \mathrm{m}\mathrm{T}$ and $B_{\mathrm{yoke}}=143 \mathrm{m}\mathrm{T}$. The losses in each piece of the snake core are then summed for the total core losses. With the flux density known, the eddy current losses are then:

$$P_{\mathrm{eddy}}=V_{\mathrm{c}}\frac{\pi f_{\mathrm{s}}^2{\widehat{B}}^2{A}_{\mathrm{c}}}{4\rho },$$

(12)

with $\rho =17 \mathrm{m}\Omega$ being the N49-ferrite resistivity, and $V_{\mathrm{c}}$ the volume of each transformer piece. Hysteresis loss ($P_{\mathrm{hyst}}$) also scales with $V_{\mathrm{c}}$ and is modeled as a function ($P_{\mathrm{v}}$) of frequency ($f_{\mathrm{s}}$), flux density ($\widehat{B}$) and temperature (T):

$$P_{\mathrm{hyst}}=V_{\mathrm{c}}{P}_{\mathrm{v}}$$

(13)

$$P_{\mathrm{v}}=f(f_{\mathrm{s}},\widehat{B},T)$$

(14)

based on the manufacturer’s loss data (see Figure 8). Although the flux is triangular, modeling the hysteresis loss from a sinusoidal excitation is used as a reasonable and simplifying approximation [28].

To validate the model and the manufacturer’s measurements, measured core losses with varying flux amplitude are recorded in a calorimetric chamber fixed at 35 ${}^{\circ }\mathrm{C}$ using the methodology outlined in [29] (which has a maximum loss error of less than $0.5$ $\mathrm{W}$). The chamber—or ambient—temperature vary from application to application (can be even cooler in datacenter racks with air-conditioning or water cooling), so the key metric considered here is the temperature on the core’s surface, monitored to correctly calculate losses using the derived models. The comparison is detailed in

Table 5. Comparison between predicted and calorimetrically-measured core losses for the PCB-integrated transformer.

	#1	#2	#3	#4
$B_{\mathrm{limb}}$ ($\mathrm{T}$)	0.156	0.166	0.176	0.149
$B_{\mathrm{yoke}}$ ($\mathrm{T}$)	0.113	0.121	0.129	0.148
$T_{\mathrm{core}}$ (${}^{\circ }\mathrm{C}$)	85.9	92.4	103	105
$P_{\mathrm{hyst},\mathrm{limb},\mathrm{calc}}$ ($\mathrm{W}$)	1.01	1.64	2.77	1.73
$P_{\mathrm{hyst},\mathrm{yoke},\mathrm{calc}}$ ($\mathrm{W}$)	3.99	5.67	8.99	17.1
$P_{\mathrm{eddy},\mathrm{limb},\mathrm{calc}}$ ($\mathrm{W}$)	0.0033	0.0038	0.0043	0.0057
$P_{\mathrm{eddy},\mathrm{yoke},\mathrm{calc}}$ ($\mathrm{W}$)	0.0344	0.0391	0.0442	0.0581
$P_{\mathrm{total},\mathrm{calc}}$ ($\mathrm{W}$)	5.04	7.45	11.8	18.9
$P_{\mathrm{total},\mathrm{meas}}$ ($\mathrm{W}$)	4.61	6.91	10.7	17.5
Error (%)	9.3	7.8	10.3	8.0

, with the measurements matching the calculation within 10% across all measured operating points. With the core loss model validated, we move to a Pareto optimization between transformer footprint area and losses.

2.2.3. Pareto Optimization and Losses

For the height-constrained transformer of Figure 2c, the total footprint area can be increased or decreased with an associated improvement or penalty on losses. Further, the area allocated to copper and magnetic core trades off winding and core losses, and a Pareto optimization is performed to select the loss-optimal design for each candidate footprint. The core design tradeoff between total transformer losses and footprint area is shown in Figure 9a for nominal load and Figure 9b for 50% load. The designs that form the Pareto front shift materially between the two load conditions, with the selected design (footprint area of $26.4$ cm² and full load losses of $29.2$ $\mathrm{W}$) representing a Pareto-optimal design at full load and a sub-optimal design at 50 load. This indicates that the transformer design is one knob that can be tweaked to optimize for efficiency at different load conditions. Here we proceed with the Pareto-optimal design at the nominal load condition—as the whole system was designed considering full-load metrics as a first (conservative) design constraint—with the selected design marked in Figure 9a,b and detailed in Table 4. In Section 2.2, we show how selecting the optimal transformer 50% load improves losses at light load and changes the shape of the efficiency curve.

The implemented copper and core for the PCB-integrated, snake-core transformer are shown in Figure 6b,d, respectively. With the transformer loss models proposed and validated, we move to the design and loss modeling for the PCB-integrated resonant inductor, $L_{\mathrm{r}}$.

2.3. PCB-Integrated Inductor

Much like the transformer designed, optimized, and characterized in Section 2.2, the primary-side inductor must be PCB-integrated for compactness, manufacturability, and cost-effectiveness—but this comes with the penalty of increased losses relative to litz-wire inductors in the desired frequency range ($100 \mathrm{kHz}$–$1 \mathrm{MHz}$) [30]. This integration penalty—which is based on the lower fill factor, worse copper utilization ($R_{\mathrm{ac}}/R_{\mathrm{dc}}$ ratio), and other geometric constraints of PCBs relative to litz wire—can be mitigated through the compensating-fringing-field concept introduced in [25], where skin and proximity effects in a PCB-based inductor are minimized by using the otherwise-parasitic fringing fields caused by the air gap in the magnetic core.

We reuse the loss models detailed in Section 2.2 and combine them with the fringing-field effects of [25] to arrive at the complete winding and core losses for the primary-side inductor, which is then Pareto-optimized for the selected value of $L_{\mathrm{r}}=24 \mathsf{\mu }\mathrm{H}$ (driven by the desired gain ratio, as discussed in Section 2.1) between footprint area (directly related to volume) and total inductor losses. This optimization is shown in Figure 9c for nominal load and Figure 9d for 50% load, where we find that, unlike the PCB-integrated transformer, the Pareto-front analysis is load-independent, with the map merely shifted down on the loss axis between nominal load and 50% load. A footprint area of $4.11$ cm² is selected for a primary-side inductor loss of $7.2$ $\mathrm{W}$ at full load and $1.7$ $\mathrm{W}$ at 50% load. This selection represents a good trade-off between inductor footprint area and full-load losses—with enough space left for primary-side components and control circuitry (see Figure 2c), and the inductor already contributing to 12% of total losses for a hypothetical full-load efficiency of 96%.

The complete inductor, as implemented, is shown in Figure 10a, with a final footprint area slightly larger than the one Pareto-optimized to accommodate thermal interfaces [25]. Figure 10b shows the implemented layer-by-layer copper of the 10-layer PCB design. The selected design is marked in Figure 9c,d and detailed in Table 4.

We note here that some LLC converters utilize the leakage inductance of the transformer as the auxiliary inductance, but this approach (i) is not feasible with our required inductance of 24 $\mathsf{\mu }$$\mathrm{H}$ and a PCB-integrated transformer, which has very high coupling (and accordingly low leakage inductance), (ii) would make the benefits of the fringing-field approach [25] difficult to achieve, and (iii) prevents the Pareto-optimization of the resonant inductor alone, leading to higher losses.

2.4. Capacitor and Power Semiconductor Selection

With the control, topology, and PCB-integrated magnetics designs finalized, we can move to the selection of the input, resonant, and output capacitors and the primary- and secondary-side power semiconductors. The loss contributions to our detailed model are outlined in the power semiconductor sections, while our calculations indicate that the losses from all of the capacitors are negligible.

2.4.1. Output Capacitor Selection

With four secondary-side sub-transformers and two windings per sub-transformer, the sheer quantity of output capacitors (eight groups) make their selection critical to the design of the converter. An analytical solution may be derived for the voltage ripple specification based on the converter parameters and the required output capacitance, as:

$$\Delta v_{\mathrm{o}}=\frac{P_{\mathrm{o}}}{C_{\mathrm{o}}{V}_{\mathrm{o}}}\left\{\frac{1}{2f_{\mathrm{s}}}cos\left[{sin}^{-1}\left(\frac{2f_{\mathrm{s}}}{\pi f_{\mathrm{r}}}\right)\right]+\frac{1}{\pi f_{\mathrm{r}}}{sin}^{-1}\left(\frac{2f_{\mathrm{s}}}{\pi f_{\mathrm{r}}}\right)-\frac{1}{2f_{\mathrm{r}}}\right\}.$$

(15)

With the output ripple specified as under 2% in the worst-case, we select a total output capacitance of 640 $\mathsf{\mu }$$\mathrm{F}$, implemented as 4 20 $\mathsf{\mu }$$\mathrm{F}$ (at 12 $\mathrm{V}$) capacitors per group (C4532X7R1C336M250KC). This gives a worst-case full-power ripple of $\Delta v_{\mathrm{o}}=194 \mathrm{m}\mathrm{V}$ ($f_{\mathrm{s}}=210 \mathrm{kHz}$, $v_{\mathrm{dc}}=300 \mathrm{V}$, $P_{\mathrm{o}}=1.5 \mathrm{k}\mathrm{W}$) and a ripple of $\Delta v_{\mathrm{o}}=66.3 \mathrm{m}\mathrm{V}$ at nominal operation ($f_{\mathrm{s}}=310 \mathrm{kHz}$, $v_{\mathrm{dc}}=400 \mathrm{V}$, $P_{\mathrm{o}}=1.5 \mathrm{k}\mathrm{W}$).

2.4.2. Input Capacitor Selection

No analytical solution for calculating the input voltage ripple exists (the equation is transcendental), so the input capacitor value is selected from circuit simulations as $C_{\mathrm{dc}}=1 \mathsf{\mu }\mathrm{F}$. We select four capacitors, each with $C_{\mathrm{dc}}=0.28 \mathsf{\mu }\mathrm{F}$ at 400 $\mathrm{V}$, to achieve this capacitance (C5750X7T2W105K250KA).

2.4.3. Resonant Capacitor Selection

As detailed in Section 2, the resonant capacitance is selected as $C_{\mathrm{r}}=11 \mathrm{n}\mathrm{F}$ from the gain analysis. The resonant capacitor is implemented as 5 paralleled C0G capacitors, each contributing $2.2$ $\mathrm{n}$$\mathrm{F}$ (CGA4F4C0G2W222J085AA).

2.4.4. Primary-Side Semiconductors

The high-voltage power semiconductors must block up to the maximum input voltage of $v_{\mathrm{dc}}=430 \mathrm{V}$, and incur losses from conduction, resonant soft-switching, body-diode conduction, and gating, with the hard-switching contributions of $Q_{\mathrm{oss}}$ and $VI$ overlap eliminated by achieving ZVS across the complete load and voltage ranges and by a fast-turn-off gate drive. To minimize the remaining loss contributions, we select the 600 $\mathrm{V}$ GaN HEMT IGLD60R070D1, with 70 $\mathrm{m}$$\Omega$ nominal on-resistance and, like all GaN HEMTs, zero reverse-recovery losses. For the primary-side semiconductor modeling, the junction temperature is estimated based on load condition, with a linear spacing between 60 ${}^{\circ }\mathrm{C}$ (full load) and 40 ${}^{\circ }\mathrm{C}$ (10% load). From here, the losses are straightforwardly calculated and the breakdown is reported in Section 3. UCC21225A gate drivers are used with bootstrap power supplies, common-mode chokes to reduce noise on these supplies, and a series capacitor to introduce a negative gate drive voltage.

2.4.5. Secondary-Side Semiconductors

The low-voltage switching stage incurs high currents and therefore must rectify synchronously, underscoring its importance to the total losses of the converter. The devices must withstand $2V_{\mathrm{o}}=24 \mathrm{V}$, and we select the 40 $\mathrm{V}$ Si MOSFET TPW48004PL, with a nominal on-resistance of $0.65$ $\mathrm{m}$$\Omega$. The semiconductor junction temperature is again modeled based on load condition, with a linear spacing between 90 ${}^{\circ }\mathrm{C}$ (full load) and 50 ${}^{\circ }\mathrm{C}$ (10% load). As we analyze in depth when searching for further improvements in Section 4, minimizing the delay of the synchronous turn-on is critical to minimizing secondary-side losses, and we use a dedicated synchronous rectifier IC (NCP4306) to drive the MOSFETs based on a direct $v_{\mathrm{ds}}$ measurement. This stage is supplied by the output voltage to fully decouple the primary and secondary sides of the converter. Again, these MOSFETs are operated under ZVS and ZCS (a natural condition of synchronous rectification) and therefore only incur conduction, body-diode, and gating losses, the contributions of which are detailed in the next section.

3. Hardware Prototype

The design detailed in Section 2 is fabricated as a $1.5$ $\mathrm{k}$$\mathrm{W}$ hardware demonstrator, and is shown in Figure 11 with the summary of the final design values and implementations given in

Table 6. Key design values and implementation for components in the $1.5$ $\mathrm{k}$$\mathrm{W}$ hardware demonstrator of Figure 11.

Parameter	Design Value	Implementation
$S_{1-4}$	–	600 $\mathrm{V}$, 70 $\mathrm{m}$$\Omega$ GaN HEMT IGLD60R070D1
$S_{1-4}$ gate drivers	–	UCC21225A
$S_{5,6}$	–	40 $\mathrm{V}$, $0.65$ $\mathrm{m}$$\Omega$ Si MOSFET TPW48004PL
$S_{5,6}$ gate drivers	–	NCP4306 and UCC27511A, $v_{\mathrm{gate}}=6 \mathrm{V}$
$L_{\mathrm{r}}$	24 $\mathsf{\mu }$$\mathrm{H}$	PCB-integrated, fringing-field concept [25]
$C_{\mathrm{dc}}$	1 $\mathsf{\mu }$$\mathrm{F}$	$4 \times$ $0.28$ $\mathsf{\mu }$$\mathrm{F}$ C5750X7T2W105K250KA
$C_{\mathrm{out}}$	640 $\mathsf{\mu }$$\mathrm{F}$	$32 \times$ 20 $\mathsf{\mu }$$\mathrm{F}$ C4532X7R1C336M250KC
$C_{\mathrm{r}}$	11 $\mathrm{n}$$\mathrm{F}$	$5 \times$ $2.2$ $\mathrm{n}$$\mathrm{F}$ CGA4F4C0G2W222J085AA

. The DC/DC converter measures 96 $\mathrm{m}$$\mathrm{m}$ by 66 $\mathrm{m}$$\mathrm{m}$ by $11.5$ $\mathrm{m}$$\mathrm{m}$, with the high-voltage switching cell highlighted in the top-right of Figure 11, the snake-core transformer in the center of the converter, and the high-current, low-voltage output to $V_{\mathrm{o}}$ in the bottom-left. This converter includes the detailed layouts of the PCB snake-core transformer (Figure 6d) and the PCB inductor $L_{\mathrm{r}}$ (Figure 10b).

Key operating waveforms are captured at nominal (Figure 12a) and 50% (Figure 12b) load, indicating correct operation of both the high-voltage and low-voltage sides of the converter for a well-regulated output voltage of $V_{\mathrm{o}}=12 \mathrm{V}$. These measured waveforms show excellent agreement with circuit-simulation results, validating the model that is used as a waveform generator for the loss models. The selected control scheme maintains sinusoidal currents through the resonant network (shown with the $i_{\mathrm{r}}$ waveform captures) to minimize harmonic losses and simplify the frequency-dependent effects in the design, and soft-switching is achieved across the entire load range. The synchronous rectifier gate driver signals are shown in the bottom pane ($g_5$, $g_6$), where we see correct operation of the circuit with a simple zero-crossing detector—but an unmistakable (albeit short) time at the end of each conduction cycle (see the third pane, $v_{\mathrm{s},5}$ and $v_{\mathrm{s},6}$) where the paralleled body-diodes conduct rather than the MOSFETs. The effect of this timing mismatch sets a loss minimum for the high-current rectification, the effects of which are investigated more deeply in Section 4.

The measured DC/DC efficiency, from $v_{\mathrm{dc}}=300 \mathrm{V}$ and $v_{\mathrm{dc}}=400 \mathrm{V}$ to $V_{\mathrm{o}}=12 \mathrm{V}$, for the hardware demonstrator across output power is shown in Figure 13. The module delivers a flat and high efficiency above around 40% of nominal load for $v_{\mathrm{dc}}=400 \mathrm{V}$, with a maximum just below 96% efficiency near 1 $\mathrm{k}$$\mathrm{W}$ of output power. The detailed loss models developed for each component in Section 2 predict the complete converter efficiency quite accurately, with minute differences across most of the load range and less than 5% of the loss not captured by the model at the largest variation between calculation and measurement (at nominal load). These component-level loss models, further, support a detailed breakdown of the losses that are shown for nominal and 50% load in Figure 14.

At full load (Figure 14a), the transformer accounts for over 40% of the total losses, with the inductor, high-voltage logic, and GaN devices bringing the high-voltage losses to about 60% of the total converter dissipation. The low-voltage loss breakdown, however, highlights the challenges of high-current outputs with high power density (and therefore high switching frequency). Firstly, the low-voltage tracks contribute 10% of the losses alone, even with a careful design to maximize the copper and copper utilization in this path. Similarly, the synchronous rectifier diode alone accounts for $16.5$% of total converter losses, despite conducting for less than 10% of the on-time! At high switching frequencies and high output currents, the speed of the sensing, control, and gating of the synchronous rectifier switches is a major performance driver, and Section 4 analyzes efficiency limits as this delay decreases.

At 50% load (Figure 14b), as expected, the current-independent (or nearly current-independent) losses represent a larger fraction of the total loss budget, including the transformer core losses (33% of total losses), the GaN switching losses, and the synchronous rectifier gating losses. The synchronous rectifier diode losses remain at around 1/6 of the total losses, with these $VI$ losses simply related to the ratio of the forward drop to the output voltage and the percent of the period in which the diode conducts.

A thermal image of the converter at nominal load and nearly steady-state is shown in Figure 15. A small fan was used to blow air on the surface of the converter (air speed of approximately 1 $\mathrm{m}$ ${\mathrm{s}}^{-1}$) and keep the temperature within limits. The high-current output results in a relatively-hot low-voltage side of the converter—with losses from the transformer winding, transformer core, low-voltage tracks, and synchronous rectifier—but the maximum temperature remains below 71 ${}^{\circ }\mathrm{C}$. The hottest components are the gate drivers for the synchronous rectifier switches, which each dissipates around $0.5$ $\mathrm{W}$ in a small package that is located in a hot environment. In a commercial application, heat sinks should be installed to conduct heat from the hot surfaces of the transformer windings either onto a cooling plate or into air.

4. Efficiency Barriers

We combine simplified control techniques, novel PCB-integrated passive components, and detailed loss optimizations to showcase an efficient, power-dense, and wide-input-voltage-range DC/DC converter for industrial power supplies with stringent hold-up time and manufacturability requirements. This module achieves a flat efficiency curve with a peak of nearly 96% and a power density of 337 $\mathrm{W}$ ${\mathrm{in}}^{-3}$ with (i) only PCB-integrated magnetic components, (ii) soft-switching across the entirety of the operating envelope, and (iii) a wide-input-voltage range that achieves the hold-up time requirements while minimizing the volume of the DC-link bulk capacitor. Finally, the detailed loss models permit component- and converter-level optimizations, and we leverage these extensive models to identify the barriers to higher efficiency that may be overcome with a next-generation module. These improvements are evaluated in two distinct categories - firstly, we reevaluate operating parameters and converter design approaches, which may be optimized by the power electronics engineer. Secondly, we analyze what key component advances would improve efficiency, improvements that will likely be considered as inputs to the power electronics design.

Firstly, the selections of transformer turns ratio, switching frequency, and primary-side bridge configuration are revisited in Figure 16. The transformer turns ratio, we recall, determines the required gain range but also drives losses as its selection defines whether the converter nominally operates near resonance or away from resonance. Figure 16a confirms that $n=32$ is the optimal choice for efficiency across load, with lower turn counts especially penalized as the load is increased through higher conduction losses. The nominal switching frequency, characterized by the tank resonant frequency, can also be optimized across load range, as shown in Figure 16b, where we see that increasing the resonant frequency to $f_{\mathrm{r}}=500 \mathrm{kHz}$ can eliminate around 10% of the losses at 50% load. These models, though, exclude the extra losses incurred by the non-idealities in synchronous rectification timing, when the body diode conducts, and $f_{\mathrm{r}}=300 \mathrm{kHz}$ remains the ideal nominal switching frequency when these losses are included. Finally, a half-bridge decreases the number of semiconductors relative to a full-bridge, accruing gains in both area and number of devices in the conduction path, but the full-bridge has a more flexible control scheme (CCM and DCM operation are both possible, as shown in Figure 4) and less primary-side current. The half-bridge efficiency is marginally higher at light load, as shown in Figure 16c, but the full-bridge outperforms on an efficiency basis above around 75% load and improves the control scheme. In all three cases, the converter-scale improvements tap out at around 96% peak DC/DC efficiency, and we turn to explore component-level improvements to push down losses.

As we detail in Figure 14, the transformer and synchronous rectifier are the primary loss drivers across the load range, and are accordingly the components in which we first seek to reduce losses. Firstly, the transformer cross-sectional area can be increased in the limbs and yokes to lower the core losses at the expense of increased winding losses (with a fixed total volume). This benefit is shown in Figure 17, which highlights the Pareto front for 50% load, recalling from Figure 9b that the selected transformer was optimized at nominal load and was sub-optimal at light load. This design change increases the peak efficiency at light load, where core losses dominate over conduction-related losses, by up to 1%, as shown with the case labeled (i) in Figure 18a.

Even larger gains can be realized in the synchronous rectifier; replacing the low-voltage MOSFETs with the new 40 $\mathrm{V}$ MOSFET from Infineon, IQE013N04LM6, reduces the driver losses by $5\times$, from nearly 4 $\mathrm{W}$ to $0.8$ $\mathrm{W}$, by dropping the gate driver voltage from 12 $\mathrm{V}$ to 6 $\mathrm{V}$ and requiring a lower gating charge (recalling $P_{\mathrm{gate}}=f_{\mathrm{s}}{C}_{\mathrm{gate}}{V}_{\mathrm{drive}}{V}_{\mathrm{gate}}$). This improvement is shown as case (ii) in Figure 18a. Finally, as discussed previously, reducing the body-diode conduction time significantly improves converter efficiency; cutting this time by 50%, in combination with the other two improvements, pushes the efficiency over $96.5$%, as shown by case (iii). Close-to-ideal synchronous rectification, though, is difficult to achieve at high switching frequencies with existing discrete components; speeding this sense and actuation might require either integrated synchronous rectifier ICs or, at a minimum, Kelvin-source connections on high-current MOSFETs to support direct $v_{\mathrm{ds}}$ measurements. The loss breakdown at 50% load with these three improvements is shown in Figure 18b, with the total losses reduced from $35.3$ $\mathrm{W}$ (Figure 14b) to $26.4$ $\mathrm{W}$, driven by reductions in transformer core losses ($3.6 \mathrm{W}$), synchronous rectifier gate driver losses ($3.2 \mathrm{W}$), and synchronous rectifier body diode losses ($4.5 \mathrm{W}$).

With the key module-level improvements characterized and identified—and, indeed, improvements identified that can eliminate 26% of the total converter losses—we move to fabricate and characterize an improved $1.5$ $\mathrm{k}$$\mathrm{W}$ module in the next Section. With this improved demonstrator, we subsequently leverage the snake-core transformer to achieve ideal current sharing with two paralleled modules for an output power of 3 $\mathrm{k}$$\mathrm{W}$.

5. Paralleled and Next-Generation DC/DC Modules

5.1. Next-Generation DC/DC Module

Firstly, a next-generation DC/DC module is fabricated with the critical changes proposed in Section 4 to improve efficiency. The updated module includes, with references to Figure 2 and a component summary in

Table 7. Key design values and implementation for components in the Improved $1.5$ $\mathrm{k}$$\mathrm{W}$ hardware demonstrator of Figure 19.

Parameter	Design Value	Implementation
$S_{1-4}$	–	600 $\mathrm{V}$, 70 $\mathrm{m}$$\Omega$ GaN HEMT IGLD60R070D1
$S_{1-4}$ gate drivers	–	UCC21225A
$S_{5,6}$	–	40 $\mathrm{V}$, $1.35$ $\mathrm{m}$$\Omega$ Si MOSFET IQE013N04LM6
$S_{5,6}$ gate drivers	–	SRK2001A and 1EDN7511B, $v_{\mathrm{gate}}=6 \mathrm{V}$
$L_{\mathrm{r}}$	24 $\mathsf{\mu }$$\mathrm{H}$	PCB-integrated, fringing-field concept [25]
$C_{\mathrm{dc}}$	1 $\mathsf{\mu }$$\mathrm{F}$	$4 \times$ $0.28$ $\mathsf{\mu }$$\mathrm{F}$ C5750X7T2W105K250KA
$C_{\mathrm{out}}$	640 $\mathsf{\mu }$$\mathrm{F}$	$32 \times$20 $\mathsf{\mu }$$\mathrm{F}$ C4532X7R1C336M250KC
$C_{\mathrm{r}}$	11 $\mathrm{n}$$\mathrm{F}$	$5 \times$ $2.2$ $\mathrm{n}$$\mathrm{F}$ C3216C0G2J222J115AA

:

• New LV-side switches ($S_{5,6}$), with IQE013N04LM6 featuring lower gate charge and driven by a 6 $\mathrm{V}$ gate voltage (supplied by a LDO) rather than a 12 $\mathrm{V}$ gate voltage;
• An updated rectifier integrated circuit (SRK2001A), that reduces the body diode conduction time by up to 25%;
• Larger transformer limb (65 $\mathrm{m}$$\mathrm{m}$${}^2$) and yoke (93 $\mathrm{m}$$\mathrm{m}$${}^2$) cross-sectional areas (see Table 4 for previous values), which lowers core losses but also slightly reduces power density through a larger core height.

This updated converter is shown as ”Module 1” in Figure 19, and measures $89.5$ $\mathrm{m}$$\mathrm{m}$ × $66.0$ $\mathrm{m}$$\mathrm{m}$ × $13.5$ $\mathrm{m}$$\mathrm{m}$, for an $8.6$% reduction in power density to 308 $\mathrm{W}$ ${\mathrm{in}}^{-3}$. This minor reduction in power density, though, accompanies a large increase in efficiency across the load range, as shown in Figure 20: at 10% load, the efficiency increases from $87.2$% to $92.3$%, and at 50% load, total converter losses are reduced by the predicted 26% for an efficiency increase from $95.6$% to $96.7$% (see Figure 21 for a detailed loss budget).

5.2. Paralleled DC/DC Modules

With the improvements identified in Section 4 demonstrated in hardware for a significant increase in overall efficiency, we move to coupling two modules to highlight one key benefit of the snake-core transformer—ideal current sharing—and reach 3 $\mathrm{k}$$\mathrm{W}$ of output power, demonstrating a path to higher output powers and currents with the modular approach.

The modules could be coupled in four configurations, with the input connections configured as “input series” (IS) or “input parallel” (IP) and the outputs independently configured as “output series” (OS) or “output parallel” (OP). The output series configurations (ISOS and IPOS) are not preferred for high-output-current applications, as each module is only configured to half of the total output voltage and therefore each module must provide the full output current. An input-series-output-parallel (ISOP) configuration features natural current sharing [31], at the expense of higher input currents per module and, for this application, switches rated to the awkward and non-commercial voltage level of 300 $\mathrm{V}$.

In this application, then, the input-parallel-output-parallel (IPOP) module coupling is preferred, with simple scaling at the expense of complications in power sharing, where even minor mismatches in resonant tank impedance leads to poor current sharing between modules [32]. To work around this fundamental problem, which is especially pernicious at high output currents, a few concepts can be considered. Firstly, digital or analog output current controllers that force equal power sharing through modulation are possible, but require additional sensing circuits, control loops, and computational power and complexity. In [33,34], coupled inductors are used to force equal current sharing, but these cannot be arbitrarily modularized and cannot benefit from the fringing-field approach used here [25] to realize high-efficiency PCB inductors. Finally, the resonant capacitors or inductors can be electrically connected [32,35], which achieves good power balancing with a simple implementation but does not improve the power density or core losses.

The proposed snake-core transformer, however, fundamentally solves the power sharing issue that bedevils IPOP modularity, with a single flux path that forces ideal magnetic coupling between modules for even power sharing, lower core losses, and a boost in power density for a single core shared between two modules. The two-module topology is shown in Figure 22, highlighting the direct magnetic coupling through a single flux path between the two modules.

This single flux path—the critical innovation of the snake-core—can be visualized through an equivalent circuit model of the magnetic reluctance, shown in Figure 23 for a conventional matrix transformer (Figure 23a) and for the snake-core transformer (Figure 23b). With a high-permeability core, the snake-core transformer can be modeled with a single flux path through each winding, so mismatches in the number of turns or core reluctances cannot affect the current sharing between phases or modules. With the matrix transformer, alternatively, additional flux paths exist across the core yokes, so even small mismatches (in turns or reluctance) can result in major current imbalances, and, potentially, to operational instability.

The benefits of the snake-core transformer, and by association the reluctance model, are validated in situ by artificially unbalancing the reluctance in one core leg of a matrix transformer with the addition of around 10% more air gap. In Figure 24a, the snake-core transformer maintains ideal current sharing between the phases and modules with the same flux penetrating all windings, while in Figure 24b,c, a traditional matrix transformer is tested, resulting in poor current sharing (especially during and near switching transitions) and signs of instability even before the artificial air gap is added. In real-world conditions, then, with variations in core materials and PCB manufacturing processes inevitable, the snake-core transformer uniquely provides a straightforward and reliable path to module coupling for high-current outputs.

The two paralleled modules are implemented in Figure 19, with the transformer core shared for higher power density and reduced core losses. The measured efficiency for the combined 3 $\mathrm{k}$$\mathrm{W}$ DC/DC converter is given in Figure 20 as the “3 $\mathrm{k}$$\mathrm{W}$ Coupled System”, with the expected gains in efficiency from reduced core losses boosting the $1.5$ $\mathrm{k}$$\mathrm{W}$ efficiency by half percentage point at light load. The paralleled converter reaches nearly 97% peak efficiency and outputs 250 $\mathrm{A}$ at 12 $\mathrm{V}$ for 3 $\mathrm{k}$$\mathrm{W}$ output power, paving the way to higher-current applications for the next-generation industrial environment.

6. Conclusions

Compact, reliable, and efficient power supplies are critical to unlocking the electrification of Industry 4.0, including power for CNC steppers, servo motor drives, and, as the power is scaled, for charging electrified material handling systems like forklifts and tuggers. These industrial power supplies must be realized under a challenging set of specifications, including long hold-up times that result in a wide-input-voltage range, complete PCB-integration with limited available heights, and high output currents at low voltages.

In this work, we conceptualize, analyze, and demonstrate a $1.5$ $\mathrm{k}$$\mathrm{W}$, 12 $\mathrm{V}$-output DC/DC converter module for industrial applications. This converter achieves nearly 96% peak efficiency with a power density over 300 $\mathrm{W}$ ${\mathrm{in}}^{-3}$ ($18.3$ $\mathrm{k}$$\mathrm{W}$ ${\mathrm{dm}}^{-3}$) while achieving the application-specific requirements: complete PCB integration, soft-switching over the entire operating range, and a wide-input-voltage from 300 $\mathrm{V}$ to 430 $\mathrm{V}$. This demonstrator met the key requirements, but further component- and converter-level improvements were subsequently identified using the detailed loss models derived in the design optimization stage. We implement the key improvements, including expanding the snake-core-transformer core area and improving the synchronous rectifier speed and device selection, and eliminate 25% of the total converter losses in a second-generation demonstrator that achieves nearly 97% peak efficiency. Finally, the benefits of the proposed snake-core transformer are showcased by paralleling two DC/DC modules with ideal current sharing among the secondary outputs—which cannot be achieved with conventional matrix transformers—for 3 $\mathrm{k}$$\mathrm{W}$ output power with an improvement in efficiency over a single module and a power density of 345 $\mathrm{W}$ ${\mathrm{in}}^{-3}$ ($21.1$ $\mathrm{k}$$\mathrm{W}$ ${\mathrm{dm}}^{-3}$).

To keep pushing Industry 4.0 towards its increasingly-electric future, power supplies that are soft-switched, wide-input-voltage range, fully PCB-integrated, efficient, power dense, and high-output-current are required. This work highlights key innovations —with experimental demonstrations—that unlock these critical power requirements, with a particular emphasis on the snake-core transformer innovation to support modular power scaling with ideal current sharing.