# Evaluation of the Different Numerical Formats for HIL Models of Power Converters after the Adoption of VHDL-2008 by Xilinx

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Materials and Methods

#### 2.1. Buck Power Converter

#### 2.2. HIL Model Equations

#### 2.3. Numerical Formats

#### 2.4. Model Evaluation

## 3. Experiments, Results and Discussion

#### 3.1. Buck Converter HIL Model Simulation

#### 3.2. Synthesis and Implementation Requirements in Terms of Word Length

#### 3.3. Synthesis and Implementation Requirements in Terms of the Rounding and Overflow Modes

## 4. Conclusions

## Author Contributions

## Funding

## Conflicts of Interest

## References

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**Figure 3.**(

**a**) Input current, $iIn$, (${i}_{L}$ when Q: ’ON’); and (

**b**) output voltage, ${v}_{o}$, (${v}_{C}$) for the golden HIL model of the proposed buck converter.

Signal | OPT | WL |
---|---|---|

${i}_{L}$ | Q6.18 | 25 |

${v}_{C}$ | Q5.19 | 25 |

$dtC$ | Q-13.24 | 12 |

$dtL$ | Q-10.21 | 12 |

$IncI$ | Q-4.18 | 15 |

$IncV$ | Q-6.19 | 14 |

$Iaux$ | Q6.8 | 15 |

$Vaux$ | Q5.6 | 12 |

${V}_{in}Aux$ | Q5.6 | 12 |

$iInAux$ | Q6.5 | 12 |

$voutAux$ | Q5.6 | 12 |

$IoutAux$ | Q3.8 | 12 |

$vC\_FB$ | Q5.6 | 12 |

$iL\_FB$ | Q6.8 | 15 |

**Table 2.**Mean absolute (MAE) and relative error (MRE) in the state variable ${i}_{L}$ and ${v}_{C}$ for the different numerical formats (NFs), word lengths (WLs) and rounding and overflow modes.

NF | WL | Round and Overflow Modes | MAE | MRE | ||
---|---|---|---|---|---|---|

${\mathit{v}}_{\mathit{C}}$ | ${\mathit{i}}_{\mathit{L}}$ | ${\mathit{v}}_{\mathit{C}}$ | ${\mathit{i}}_{\mathit{L}}$ | |||

Fixed | 32 | Round, Saturate | 0.0040 | 0.0039 | 0.0008 | 0.0020 |

32 | Wrap, Truncate | 0.0077 | 0.0093 | 0.0015 | 0.0047 | |

64 | Round, Saturate | 0.0040 | 0.0039 | 0.0008 | 0.0020 | |

64 | Wrap, Truncate | 0.0077 | 0.0094 | 0.0015 | 0.0047 | |

OPT | Round, Saturate | 0.0047 | 0.0042 | 0.0009 | 0.0025 | |

OPT | Wrap, Truncate | 0.0041 | 0.0049 | 0.0008 | 0.0021 | |

Float | 32 | Round nearest | 0.0002 | 0.0001 | 0.0000 | 0.0000 |

32 | Round zero | 0.0011 | 0.0014 | 0.0005 | 0.0007 | |

64 | Round nearest | 0.0002 | 0.0001 | 0.0000 | 0.0000 | |

64 | Round zero | 0.0005 | 0.0005 | 0.0001 | 0.0002 |

**Table 3.**Hardware needs in terms of speed (T${}_{CLK\_min}$) and area (LUTs and FFs) with and wihtout DSPs, when floating-point NF is considered with different WLs and default rounding modes in VHDL-2008.

Parameter | Float32 | Float64 | ||
---|---|---|---|---|

T${}_{\mathit{CLK}\_\mathit{min}}$ (ns) | 83.356 | 84.719 | 124.612 | 116.746 |

DSP | 4 | 0 | 18 | 0 |

LUT | 8683 | 9675 | 20,378 | 24,296 |

FF | 64 | 64 | 128 | 128 |

**Table 4.**Hardware needs in terms of speed (T${}_{CLK\_min}$) and area (LUTs and FFs) with and without DSPs, considering the fixed-point NF with different WLs and default rounding modes in VHDL-2008.

IEEE Libraries of VHDL-2008 | ||||||
---|---|---|---|---|---|---|

Parameter | Fixed OPT | Fixed32 | Fixed64 | |||

T${}_{CLK\_min}$ (ns) | 16.880 | 17.745 | 16.940 | 20.587 | 31.674 | 34.800 |

DSP | 2 | 0 | 6 | 0 | 32 | 0 |

LUT | 242 | 426 | 368 | 1287 | 1225 | 5925 |

FF | 50 | 50 | 64 | 64 | 128 | 128 |

IEEE_Proposed Libraries of VHDL-93 | ||||||

Parameter | Fixed OPT | Fixed32 | Fixed64 | |||

T${}_{CLK\_min}$ (ns) | 17.602 | 17.745 | 17.405 | 20.701 | 32.743 | 34.873 |

DSP | 2 | 0 | 6 | 0 | 32 | 0 |

LUT | 241 | 426 | 370 | 1293 | 1216 | 5928 |

FF | 50 | 50 | 64 | 64 | 128 | 128 |

**Table 5.**Hardware needs in terms of speed (T${}_{CLK\_min}$) and area (LUTs and FFs) with and wihtout DSPs, for different WLs and rounding modes when the floating-point NF is used in VHDL-2008.

Round-Nearest | ||||
---|---|---|---|---|

Parameter | Float32 | Float64 | ||

T${}_{CLK\_min}$ (ns) | 83.356 | 84.719 | 124.612 | 116.746 |

DSP | 4 | 0 | 18 | 0 |

LUT | 8683 | 9675 | 20,378 | 24,296 |

FF | 64 | 64 | 128 | 128 |

Round-Zero | ||||

Parameter | Float32 | Float64 | ||

T${}_{CLK\_min}$ (ns) | 62.564 | 69.217 | 84.093 | 97.730 |

DSP | 4 | 0 | 18 | 0 |

LUT | 4185 | 4782 | 11,754 | 14,850 |

FF | 64 | 64 | 128 | 128 |

**Table 6.**Hardware needs in terms of speed (T${}_{CLK\_min}$) and area (LUTs and FFs) with and without DSPs, for different WLs, as rounding and overflow modes when the fixed-point NF is used in VHDL-2008.

Round and Saturate | ||||||
---|---|---|---|---|---|---|

Parameter | Fixed OPT | Fixed32 | Fixed64 | |||

T${}_{CLK\_min}$ (ns) | 16.880 | 17.745 | 16.940 | 20.587 | 31.674 | 34.800 |

DSP | 2 | 0 | 6 | 0 | 32 | 0 |

LUT | 242 | 426 | 368 | 1287 | 1225 | 5925 |

FF | 50 | 50 | 64 | 64 | 128 | 128 |

Truncate and Wrap | ||||||

Parameter | Fixed OPT | Fixed32 | Fixed64 | |||

T${}_{CLK\_min}$ (ns) | 8.558 | 8.576 | 10.525 | 13.863 | 16.933 | 20.462 |

DSP | 2 | 0 | 6 | 0 | 32 | 0 |

LUT | 114 | 311 | 241 | 1083 | 731 | 4668 |

FF | 50 | 50 | 64 | 64 | 128 | 128 |

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**MDPI and ACS Style**

Cirugeda-Roldán, E.M.; Martínez-García, M.S.; Sanchez, A.; de Castro, A.
Evaluation of the Different Numerical Formats for HIL Models of Power Converters after the Adoption of VHDL-2008 by Xilinx. *Electronics* **2021**, *10*, 1952.
https://doi.org/10.3390/electronics10161952

**AMA Style**

Cirugeda-Roldán EM, Martínez-García MS, Sanchez A, de Castro A.
Evaluation of the Different Numerical Formats for HIL Models of Power Converters after the Adoption of VHDL-2008 by Xilinx. *Electronics*. 2021; 10(16):1952.
https://doi.org/10.3390/electronics10161952

**Chicago/Turabian Style**

Cirugeda-Roldán, Eva M., María Sofía Martínez-García, Alberto Sanchez, and Angel de Castro.
2021. "Evaluation of the Different Numerical Formats for HIL Models of Power Converters after the Adoption of VHDL-2008 by Xilinx" *Electronics* 10, no. 16: 1952.
https://doi.org/10.3390/electronics10161952