Evaluation of Low-Frequency Noise in MOSFETs Used as a Key Component in Semiconductor Memory Devices

Abstract

Methods for evaluating low-frequency noise, such as 1/f noise and random telegraph noise, and evaluation results are described. Variability and fluctuation are critical in miniaturized semiconductor devices because signal voltage must be reduced in such devices. Especially, the signal voltage in multi-bit memories must be small. One of the most serious issues in metal-oxide-semiconductor field-effect-transistors (MOSFETs) is low-frequency noise, which occurs when the signal current flows at the interface of different materials, such as SiO₂/Si. Variability of low-frequency noise increases with MOSFET shrinkage. To assess the effect of this noise on MOSFETs, we must first understand their characteristics statistically, and then, sufficient samples must be accurately evaluated in a short period. This study compares statistical evaluation methods of low-frequency noise to the trend of conventional evaluation methods, and this study’s findings are presented.

1. Introduction

Semiconductor devices have been basically progressed with the shrinking of MOSFETs (metal-oxide-semiconductor field-effect-transistors), which are used as the key component in them. The shrinkage has been performed following the rule of the constant electric field in MOSFETs, which decreases signal voltage [1,2]. In addition, power consumption of electronic devices has skyrocketed because the amount of digital data generated is growing at a rate faster than Moor’s law [3,4]. The reduction of power consumption strongly requires decreasing supply voltage of MOSFETs because power consumption (P) is proportional to the square of the supply voltage (V_dd) as follows [5].

$$\mathrm{P}={\mathrm{C}}_{\mathrm{L}}{\mathrm{V}}_{\mathrm{dd}}^2\mathrm{f}$$

(1)

where C_L represents the load capacitor and f represents the switching frequency of the circuit. The growth of clock frequency in the leading edge logic devices has stopped by exceeding the heat extraction capability. However, the downscaling has been continued to reduce the cost. In the other devices, the downscaling the device size has also been continued to reduce the power consumption and the other reasons. As a result, as the device size is reduced, the signal voltage of MOSFETs decreases. Memory devices’ power consumption and supply voltage also have to be reduced [6,7,8,9] because of the same reasons as the logic devices and reducing a leakage current. On the other hand, a decrease in signal voltage degrades the reliability of electronic circuits, including analog and digital devices.

The logic (bit) error rate (LER) is given by the following equation.

$$\mathrm{LER}={\mathrm{P}}_0{{\displaystyle \int }}_{-\infty }^{\mathsf{\alpha }}{\mathrm{f}}_0\left(\mathrm{x}\right)\mathrm{dx}+{\mathrm{P}}_1{{\displaystyle \int }}_{\mathsf{\alpha }}^{\infty }{\mathrm{f}}_1\left(\mathrm{x}\right)\mathrm{dx}$$

(2)

where P₀ and P₁ represent the probabilities of signals “0” and “1”, respectively, α represents the identification level between “0” and “1”, and f₀(x) and f₁(x) represent noise amplitude densities superimposed on “0” and “1”, respectively. If f₀ and f₁ are Gaussian noise, the following equations apply.

$${\mathrm{f}}_0\left(\mathrm{x}\right)=\frac{1}{\sqrt{2{\mathsf{\pi }\mathsf{\sigma }}^2}}{\mathrm{e}}^{-\frac{{\mathrm{x}}^2}{2{\mathsf{\sigma }}^2}},{\mathrm{f}}_1\left(\mathrm{x}\right)=\frac{1}{\sqrt{2{\mathsf{\pi }\mathsf{\sigma }}^2}}{\mathrm{e}}^{-\frac{{\left(\mathrm{x}-{\mathrm{A}}_{\mathrm{S}}\right)}^2}{2{\mathsf{\sigma }}^2}}$$

(3)

where A_S represents the signal amplitude and σ represents the standard deviation of the noise. When P₀ = P₁ = 1/2 and α = A_S/2 are assumed, the LER is given by the following equation from Equations (2) and (3).

$$\mathrm{LER}=\frac{1}{2}\mathrm{erfc}\left(\frac{{\mathrm{A}}_{\mathrm{S}}}{2\sqrt{2{\mathsf{\sigma }}^2}}\right)$$

(4)

$$\mathrm{erfc}\left(\mathrm{x}\right)=1-\mathrm{erf}\left(\mathrm{x}\right)=1-\frac{2}{\sqrt{\mathsf{\pi }}}{{\displaystyle \int }}_0^{\mathrm{x}}{\mathrm{e}}^{-{\mathrm{t}}^2}\mathrm{dt}=\frac{2}{\sqrt{\mathsf{\pi }}}{{\displaystyle \int }}_{\mathrm{x}}^{\infty }{\mathrm{e}}^{-{\mathrm{t}}^2}\mathrm{dt}$$

(5)

When Nyquist transmission rate is the same as the signal band, the signal to noise (S/N) ratio (dB) is given by the following equation.

$$\frac{\mathrm{S}}{\mathrm{N}}=\frac{{\mathrm{E}}_{\mathrm{b}}}{{\mathrm{N}}_0}=20\log \left(\frac{{\mathrm{A}}_{\mathrm{S}}}{\mathsf{\sigma }}\right)$$

(6)

where E_b and N₀ represent signal and noise energy per second, respectively. From Equations (4) and (6), the LER is given by the S/N ratio as follows [10].

$$\mathrm{LER}=\frac{1}{2}\mathrm{erfc}\left\{\frac{1}{2\sqrt{2}}{10}^{\frac{1}{20}\left(\frac{\mathrm{S}}{\mathrm{N}}\right)}\right\}$$

(7)

Figure 1 shows the LER as a function of S/N (dB) and A/σ ratios [10]. The LER decreases with an increase in S/N (A_S/σ) ratio. On the other hand, to guarantee that a system does not make a mistake even once during the operation period, the LER should be reduced as shown in the following equation.

$$\mathrm{LER}\le \frac{1}{{\mathrm{N}}_{\mathrm{L}}\times \mathrm{F}\times \mathrm{T}}$$

(8)

where N_L, F, and T represent the number of logic gates in a chip, the number of operations per second, and the guarantee period, respectively. For example, the LER should be less than 3 × 10⁻²⁶ for a circuit with 10⁸ logic gates, 10⁹ Hz operations, and a 10-year (3 × 10⁸ s) operation period, and then the S/N (A_S/σ) ratio should be greater than 26.5 dB (21.1).

For example, we consider signal electrons required from a no error operation. Figure 2 shows (a) Variation in the number of electrons as a function of the number of signal electrons. (b) Logic error rate as a function of the number of signal electrons. When a signal is constructed by a constant number of electrons (N_e), the standard deviation of the number of electrons is (N_e)^1/2, and then the A/σ ratio is (N_e)^1/2. As a result, the number of electrons must be greater than 445 to maintain an S/N (A_S/σ) ratio of 26.5 dB (21.1). If the number of signal electrons is 1, the LER must be equal to 0.3. Then, such a system produces the wrong output once every three calculations.

The electronic circuit will be influenced by noise, such as thermal noise, quantum noise, and flicker noise. The noise voltage (v_nf) in 1/f noise is defined by the following equation.

$${\mathrm{v}}_{\mathrm{nf}}=\sqrt{\frac{{\mathrm{K}}_{\mathrm{F}}}{{\mathrm{C}}_{\mathrm{OX}}\times \mathrm{L}\times \mathrm{W}}\ln \left(\frac{{\mathrm{f}}_{\mathrm{H}}}{{\mathrm{f}}_{\mathrm{L}}}\right)}$$

(9)

where K_F represents the flicker noise coefficient, f_L~f_H is the frequency period for device operation, C_OX, L, and W represent the gate oxide capacitance, gate length, and gate width of a MOSFET, respectively. Noise increases with device shrinkage because v_nf is inversely proportional to $\sqrt{{\mathrm{C}}_{\mathrm{OX}}\mathrm{LW}}$ [11,12,13,14]. It has been pointed out that 1/f noise may influence not only analog devices, but also digital devices when device shrinkage and the decreasing signal voltage are moved on [15]. Random telegraph noise (RTN), another low-frequency noise also affects electronic devices, such as CMOS image sensor [16,17,18,19,20,21], static random access memory (SRAM) [22,23,24,25], dynamic random access memory (DRAM) [25], and flash memory [26,27,28,29,30,31,32]. Low-frequency noise, such as 1/f noise and RTN, have high variability [33,34] because they must be statistical phenomena by nature, and statistical analysis is required to fully understand this phenomenon. The conventional evaluations of the noise in MOSFETs have performed with a few sample numbers, and then we could understand only typical noise characteristics of MOSFETs having relatively large noise. However, we need statistical information of the noise for the design of LSI. Then, low-frequency noise statistical evaluation methods and evaluation results are described in this study.

2. Evaluation Methods

2.1. Test Pattern for Noise Evaluation

The test structure is constructed using 0.22 μm, 1-poly 2-metal standard CMOS technology and includes n-MOSFETs of various gate sizes [35,36,37,38] as shown in

Table 1. Number of n-MOSFETs for each transistor size.

Gate Length (μm)	Gate Width (μm)	Number of MOSFETs	Supply Voltage (V)
0.22	0.28	131,072 (128 × 1024)	2.5
0.22	0.30	131,072
0.24	0.30	131,072
0.24	1.5	131,072
0.24	15	131,072
0.4	1.5	32,768 (128 × 256)
0.4	15	32,768
1.2	0.3	65,536 (64 × 1024)
1.2	1.5	65,536
4.0	0.30	65,536
4.0	1.5	65,536
0.24	0.30	32,768 (AR:100)
0.24	0.30	4096 (16 × 256, AR:1000)
0.24	0.30	1344 (32 × 42, AR:10000)
0.4	1.5	131,072	3.3
0.4	15	32,768
1.2	15	16,384 (64 × 256)
4.0	15	16,384

AR: Antenna ratio.

. The measured MOSFETs are arrayed in 1024 rows and 1776 columns (total number of MOSFETs: 1217856) in a chip at 5 μm intervals. The size of the MOSFETs, and their number, and location in a chip are shown in Table 1. The test chip has an area of 5.5 mm × 14 mm. The gate insulator is formed by pyrogenic oxidation and is 5.8 nm thick.

A schematic block diagram of a test pattern is shown in Figure 3a [35,37,39,40]. This is composed of MOSFETs measured in arrayed unit cells, vertical and horizontal shift registers for addressing measured MOSFETs, MOSFETs located on each column for current control of measured MOSFET, analog memories for storing the source voltage of the measured MOSFETs within one line, and a source follower circuit for amplifying the output signal. The drain (V_D) and gate (V_G) voltage in measured MOSFETs and the gate voltage applied to current source MOSFETs (V_REF) are supplied from the external voltage source simultaneously. V_DD and V_SS are the supply voltages in the peripheral circuits and ground voltage, respectively. The measured MOSFET and current source transistor construct a source follower circuit using a select transistor. This test structure uses simple peripheral circuits. Therefore, it can be used to evaluate various MOSFETs with varying gate lengths, gate widths, gate insulator films, thicknesses, and other characteristics. Figure 3b shows the circuit schematic of a unit cell and current source transistor in Figure 1, which is the principle of this measurement. A unit cell is constructed with a measured MOSFET and a select transistor. When the current source transistor operates at a saturation region, I_REF is independent of the voltage between the source and drain in the current source transistor (V_out). When the gate bias of the select transistor (Φ_x) is applied from a vertical shift register, I_REF flows into the measured MOSFET. The output voltage (V_out) is indicated as follows.

$${\mathrm{V}}_{\mathrm{gs}}={\mathrm{V}}_{\mathrm{G}}-{\mathrm{V}}_{\mathrm{out}}-{\mathrm{I}}_{\mathrm{REF}}·{\mathrm{R}}_{\mathrm{select}}\approx {\mathrm{V}}_{\mathrm{G}}-{\mathrm{V}}_{\mathrm{out}}$$

(10)

where R_select is the channel resistance of the select switch transistor. The select transistor must be operated in the linear region to have sufficient high channel conductivity compared with the measured MOSFET, and then, I_REF∙R_select can be neglected. The output signal can be obtained as a source voltage for each measured MOSFET by shift register scanning, and then 1.2 million MOSFETs can be measured within approximately 0.7 s. The electrical characteristics of the measured MOSFETs can be observed as the V_gs included in the output voltage V_out (Figure 3b). In this frame measurement mode, each MOSFET can be measured every 0.7 s. This test pattern has another measurement mode, which can measure a specific MOSFET every 1 μs.

2.2. Extraction of Amplitude and Time Constant of RTN

Two-level type RTN is characterized by only three parameters, which are the mean time to capture (<τ_c>), mean time to emission (<τ_e>), and amplitude (ΔV_gs). The time constants correspond to two physical states of a trap, that is, τ_c and τ_e represent spans in a low V_gs level (carrier trapping state) and high V_gs level (carrier emission state), respectively (Figure 4a). The RTN amplitude ΔV_gs is defined as the difference between two normal distributions in a voltage histogram (Figure 4b). We extract the time constants by fitting the distributions of τ_c and τ_e to the exponential distribution (Ae^−t/<τ>) because the phenomenon is governed by the Poisson process. The time constants can be extracted with μs accuracy using the specific MOSFET measurement mode.

The time constant ratio <τ_e>/<τ_c> is also an important parameter in RTN because the energy level of a trap that causes RTN is related to the constant ratio as follows [12,41,42,43].

$$\frac{<{\mathsf{\tau }}_{\mathrm{c}}>}{<{\mathsf{\tau }}_{\mathrm{e}}>}=\mathrm{gexp}\left(\frac{{\mathrm{E}}_{\mathrm{T}}-{\mathrm{E}}_{\mathrm{F}}}{\mathrm{kT}}\right)$$

(11)

where E_T and E_F represent the energy of the trap and Fermi energy of the channel, respectively; k, T, and g represent Boltzmann constant, temperature, and degeneracy factor, respectively, where g is assumed to 1. Then, the energy of the trap level is indicated by (12).

$${\mathrm{E}}_{\mathrm{T}}-{\mathrm{E}}_{\mathrm{F}}=\mathrm{kTln}\left(\frac{<{\mathsf{\tau }}_{\mathrm{c}}>}{<{\mathsf{\tau }}_{\mathrm{e}}>}\right)$$

(12)

We can use the frame measurement mode to extract the time constant ratio, and the 1.2 million MOSFETs can be measured 10,000 times in 7000 s (sampling period = 0.7 s). An average of the time constant ratio <τ_e>/<τ_c> is the same as Count-L/Count-H (shown in Figure 4b), where Count-L and count-H are the numbers of low and high states, respectively [41,42,43,44]. When the time constant is greater than a sampling frequency of 0.7 s, the detected number of transition times is the same as the transition time of RTS characteristics. However, when the time constant is less than 0.7 s, the detected number of transition times is less than the real one; however, it is proportional to the real one because the absolute value of the time constant, which is less than the sampling frequency, cannot be extracted in this measurement. Then, the number of transition times is defined as the detected ones in the sampling frequency of 0.7 s.

2.3. Root Mean Square of RTN Waveform

The root mean square (RMS) of the signal waveform is often used for the representative parameter of noise [45], and the RMS of the output voltage V_RMS is defined as follows in this study.

$${\mathrm{V}}_{\mathrm{RMS}}=\sqrt{\frac{{\sum }_{\mathrm{i}=1}^{\mathrm{N}}{\left({\mathrm{V}}_{\mathrm{out},\mathrm{i}}-\overline{{\mathrm{V}}_{\mathrm{out}}}\right)}^2}{\mathrm{N}-1}}=\mathrm{A}\frac{\sqrt{<{\mathsf{\tau }}_{\mathrm{e}}><{\mathsf{\tau }}_{\mathrm{c}}>}}{<{\mathsf{\tau }}_{\mathrm{e}}>+<{\mathsf{\tau }}_{\mathrm{c}}>}$$

(13)

where ${\mathrm{V}}_{\mathrm{out},\mathrm{i}}$, $\overline{{\mathrm{V}}_{\mathrm{out}}}$, N, and A are the output voltage at ith sampling, average of ${\mathrm{V}}_{\mathrm{out}}$, sampling numbers, and the amplitude of two-state RTN, respectively. Using V_RMS, we can obtain MOSFETs with high noise from many measured MOSFETs. Figure 5 shows the relationship between V_RMS and RTN waveform. The waveform with large RTN corresponds to large V_RMS.

3. Results and Discussion

3.1. Statistical Evaluation of RTN Characteristics

The 1/f noise increases with downscaling of MOSFETs, as mentioned above, and RTN also increase with the downscaling [12,36,37]. Figure 6 shows the Gumbel plot of V_RMS for the various MOSFET sizes [36,37]. A large V_RMS can be observed in small-size MOSFETs (L/W = 0.22/0.28, 0.22/0.3, 0.24/0.3 μm). In this experiment, noise cannot be observed in large MOSFETs because the floor noise is relatively high at ~2.5 mV.

Figure 7a shows the Gumbel plot of V_RMS for the various I_DS varied from 0.13 to 12.7 μA. The sizes of MOSFETs are L/W = 0.22/0.28 μm and V_BS = −1.0 V [39]. The data in (a) and (b) were measured by the frame and specific MOSFET measurement modes, respectively. The number of MOSFETs with large noise increases with decreasing I_DS, which is controlled by V_gs. This means that the event probability of large noise increases with decreasing V_gs because the number of channel electrons decreases with decreasing V_gs, and then the effect of a trapped electron charge becomes large with decreasing number of channel electrons. The number of channel electrons also decreases with the shrinkage of transistor size shown in Figure 6, and then, the probability increases with decreasing channel size. Figure 7b shows the waveform of typical MOSFETs for I_DS of 0.13, 0.38, and 1.3 μA [39]. The time constants and amplitude are modulated by I_DS. With increasing I_DS (V_gs), amplitude and τ_c decrease, whereas τ_e slightly increases. An increase in V_gs decreases E_T-E_F, and then, the time to capture decreases as shown in Equation (11). The difference between the modulation of τ_e and τ_c is discussed later. The modulation of amplitude is caused by a decrease in the number of electrons, as discussed above. It is considered that decreasing the time to capture and increasing amplitude with decreasing V_gs increases the event probability of large noise. Figure 8a shows the Gumbel plot of V_RMS for the various back bias (V_BS). V_BS varied from −0.075 to −1.38 V, and Figure 8b shows the waveform of typical MOSFETs for V_BS of 0.6 1.0 and 1.3 V [39]. The probability increases with the absolute value of V_BS in (a). In this experiment, I_DS was constant at 1.0 μA, and this means that the number of electrons was almost the same for each V_BS. Increasing V_BS caused channel percolation [46,47,48,49], making the channel thickness narrow and percolated and increasing electron energy [50]. The probability is increased by channel percolation [46,47], and the varying electron energy modulates the time constants. In MOSFETs with RTN, the amplitude does not increase with increasing V_BS because the number of electrons is the same for each V_BS. This means that channel percolation increases the probability of RTN generation.

Figure 9 shows the Gumbel plot of the RTN amplitude for MOSFETs with varying channel doping [51]. The channel percolation is accelerated by increasing channel doping concentration [46,47,48]. This figure shows that the probability of the number of MOSFETs with large amplitude increases with doping concentration. RTN is increased by channel doping as well as doping the concentration near the source and drain regions. Figure 10 shows the Gumbel plot of V_RMS for various Halo implantation concentrations [52]. The number of MOSFETs with large RTN increases with an increase in Halo implantation concentration. This indicates that the high dose in the channel region or near the source/drain region results in high RTN because of channel percolation enhancement.

Figure 11 shows the energy band diagrams and energy distribution of traps causing RTN for V_gs of 0.57, 0.53, and 0.46 V, respectively [41,42]. The difference between E_T and E_F for electrons is calculated using Equation (11). The blue shading and red solid bars in Figure 11 show the energy distribution of traps causing RTN in each measurement condition and common traps in all conditions, respectively. Although the shape of the distribution of each V_gs is almost the same, and the energy of common traps in all V_gs increases with decreasing V_gs. The conduction band edge (E_C), the bottom sub-band energy (E_sub), and 2nd sub-band energy (E_2nd) in the inversion layer and E_F are indicated in Figure 11 [50]. The energy levels of sub-bands were calculated using Equation (14) [50].

$${\mathrm{E}}_{\mathrm{j}}={\left[\frac{3{\mathrm{hqE}}_{\mathrm{s}}}{4\sqrt{2{\mathrm{m}}_{\mathrm{x}}}}\left(\mathrm{j}+\frac{3}{4}\right)\right]}^{\raisebox{1ex}{$2$}\!\left/ \!\raisebox{-1ex}{$3$}\right.},\mathrm{j}=0,1,$$

(14)

where E_s is the electric field, h and m_x represent Planck’s constant and effective mass of electrons, respectively. E_j is jth sub-band energy, and E_sub and E_2nd represent E₀ and E₁, respectively. The main energy distribution for each V_gs locates higher energy than the conduction band edge. It is considered that the energy level of traps is widely distributed, and the energy of the detected traps is determined by the electron energy in E_sub and E_2nd. Conversely, the energy of common traps in all V_gs increases with decreasing V_gs because the influence of trap energy on V_gs is larger than that of electron energy in the channel.

3.2. Multi-State RTN

Large V_RMS RTN includes both two-state and multi-state RTN [34,53,54,55,56], which is considered to be generated by multi-traps. The analysis of trap characteristics, such as time constants and amplitude, in multi-state RTN is more difficult than that of two-state. Figure 12 shows the appearance probability of RTN with two, three, four, and more than four states. A large RTN (V_RMS > 680 μV) was obtained by a frame measurement mode of the sampling period of 0.7 s/frame in I_DS = 1 μA. 131,072 MOSFETs (L/W = 0.22/0.28 μm) were measured, and 2575 MOSFETs with large V_RMS can be extracted. Then, we selected MOSFETs with large RTN and measured them by a specific measurement mode of a sampling period of 1 μs and a long sampling time of 10 min (sampling points = 6 × 10⁸) for the same bias condition [57,58]. Figure 13, Figure 14 and Figure 15 show the (a) waveform, (b) time lag plot (TLP), and (c) histogram for typical three-, four-, and six-state RTN. The number of peaks and the transition of each state can be understood via TLP [53,54,56].

Figure 13, Figure 14 and Figure 15 show the (a) waveform, (b) time lag plot (TLP), and (c) histogram for typical three-, four-, and six-state RTN. The number of peaks and the transition of each state can be understood via TLP [53,54,56]. Figure 13, Figure 14 and Figure 15b show the relationship of ith and (i + 10)th V_gs for the constant IDS. As shown in Figure 13b, transitions occur not from the lowest state to the highest state, but only via the medium state. When the trapping probability of some traps is even, the number of states should be even, and the transition from one position to the next can occur. To begin with, an odd number of states implies that the trapping probability for each trap is not independent of each other. A similar transition phenomenon occurs even in a four-state case. As shown in Figure 14b, transitions did not occur from the lowest state to the highest state or from the second-lowest state to the second-highest state. This also means that there are more than two traps, and the probability of trapping for each trap is not independent of each other. The characteristics of multi-trap RTN can be understood via TLP and waveforms [56]; however, these analyses become more difficult as the number of states increases.

3.3. Time Constants in Individual RTN

As the extraction of multi-trap phenomena is difficult, as discussed in Section 3.2, we discuss the time constants and amplitude only in two-state RTN [59]. Figure 16 shows (a) τ_c and (b) τ_e as a function of I_DS, respectively. These data are measured at I_DS of 0.1, 0.3, 1.0, 3.0, and 5.0 μA. The data in Figure 16 show how parameters from all two-level RTN can be extracted in common under four or five I_DS, and thus, the number of selected data points was 22.

Figure 17a shows τ_c/τ_e and E_T-E_F as a function of I_DS and Figure 17b band diagram of MOS structure for changing V_GS (I_DS). τ_c/τ_e and E_T-E_F are calculated from the data in Figure 16 and Equation (12), respectively. τ_c and τ_e decrease and increase with an increase in I_DS (V_GS), and the absolute slope of τ_c is significantly larger than that of τ_e. Large trap energy (E_T) decreases with an increase in V_GS than that of channel electron (E_C: bottom energy of conduction band). Then, with increasing V_GS (I_DS), the energy barrier from the channel electron to the trap decreases and that from the trapped electron to the channel increases. As a result, the time to capture and time to emission decreases and increases, respectively, with increasing V_GS (I_DS). The transition probability depends on the energy barrier height between a trap and channel. τ_e depends only on the energy barrier because only one electron is captured in a trap. Meanwhile, τ_c depends not only on the energy barrier, but also on the number of electrons in a channel because the number of channel electrons increases as V_GS (I_DS) increases. Then, the dependency of τ_c on I_DS is more significant than that of τ_e. E_T-E_F in Figure 17 changed by approximately 175 mV during I_DS (V_GS) from 0.1 (0.53V) to 5.0 μA (0.75V). Based on these values, E_T-E_F changes by 0.18 V, whereas V_GS changes by 0.22 V. The distance between the traps and the channel was 4.6 nm due to the gate oxide thickness of 5.7 nm. However, τ_c depends not only on the trap energy, but also on the number of channel electrons; thus, E_T-E_F values cannot be calculated using Equation (12). The distance is considered to be shorter than the calculated value. τ_e values for almost all samples monotonically increased with increasing I_DS. This suggests that the distance from the trap to the channel is shorter than that to the gate electrode. The distance between the trap and channel is shorter than 2.85 nm, which is the center of the gate oxide thickness. Figure 18a,b show the amplitude and transition frequency as a function of I_DS for the same samples as those in Figure 16 and Figure 17, respectively. For a sufficiently long measuring period, the transition frequency (TF) was calculated using the following equation.

$$\mathrm{TF}\approx \frac{{\mathrm{N}}_{\mathrm{e}}}{{\mathsf{\tau }}_{\mathrm{e}}}\approx \frac{{\mathrm{N}}_{\mathrm{c}}}{{\mathsf{\tau }}_{\mathrm{c}}}$$

(15)

The amplitude decreases and the TF increases with an increase in I_DS for almost all samples. This is caused by the increase in the number of channel electrons as I_DS increases. However, the amplitude and TF of some samples did not exhibit monotony, which is due to the percolation channel effect [46,47,48,49]. The distance between the channel and trap changes as I_DS (V_GS) changes because of the formation of the percolation channel.

3.4. Effect of Drain Current on Appearance Probability and Amplitude

Figure 19 shows the Gumbel plot of the V_RMS for 18,048 MOSFETs. I_DS varied from 0.1 to 20 μA. The floor noise in this experiment was smaller than the others and was approximately 35 μV_RMS [60]. In Figure 7, V_RMS decreases with an increase in I_DS for all V_RMS. In Figure 19, larger V_RMS can also be observed in small I_DS in relatively large V_RMS regions. However, the higher appearance probability in large I_DS than that in small I_DS for the small V_RMS region of less than 500 μV could not be observed in Figure 7 because the floor noise was approximately 1 mV in that experiment. The amplitude characteristics are the same as the V_RMS characteristics, and the distribution of the time constants is the same for all conditions [60]. Figure 20 shows the frequency of RTN with two, three, and more than three states in 18,048 MOSFETs. The frequency of all states increases with I_DS.

It is assumed that the probability that electrons and percolation paths are close to each other increases as I_DS increases, increasing the number of electrons in the channel and the number of percolation paths. Figure 21 shows the Gumbel plot for the amplitude of two-state RTN. Notably, frequency sometimes increases with an increase in I_DS even though the effect of trapped electrons on the channel decreases with an increase in the electron density in the channel.

3.5. Modulation of Time Constants

In Section 3.3, the time constants were measured under constant conditions. The differences between time constants and VRMS in continuous on-state and periodically switched conditions are discussed in this section [61]. As shown in Figure 16, V_GS dependance on τ_c is larger than that of τ_e, and this suggests that the cycle period (τ_c + τ_e) in on-state is longer than that in off-state because the V_GS of off-state is smaller than that of on-state. Figure 21a,b show the time constant relationship between continuous on-state and periodically switched conditions. In the periodically switched condition, MOSFETs cycled for 10.6 msec in 700 ms, which was a measurement cycle. Although τ_e of almost all samples are the same in both conditions, τ_c of some samples in the periodically switched condition is larger than that in continuous on-state. Figure 22 shows (a) histogram of the V_RMS difference between continuous on-state and periodically off-state (ΔV_RMS) and (b) schematic waveform of RTN in continuous on-state and periodically off-state, respectively. Though V_RMS of 5% samples was increased, that of 95% was not changed or decreased in the periodically switched condition. As a result, V_RMS decreased in the periodically switched condition, with a few exceptions. This suggests that V_RMS can be reduced by the modulation of operation conditions, even in the same MOSFET.

3.6. Device Structure Dependence of RTN

In the above results and discussions in Section 3.1, Section 3.2, Section 3.3, Section 3.4 and Section 3.5, the dependance of RTN characteristics on operation conditions is mainly described. In Section 3.6, the dependance of RTN characteristics on the structure of MOSFETs, such as buried channel MOSFETs and asymmetric source–drain structure MOSFETs, are described [57,62,63,64,65].

3.6.1. Buried Channel MOSFETs

Figure 23 shows the structure of buried channel MOSFETs studied in this work. To discuss the effects of n-Si layer widths and the distance between the channel and SiO₂/Si interface, n-Si layer width was varied to be 0, 10, 25, and 60 nm for standard, narrow, middle, and deep samples formed by arsenic ion implantation, respectively, and the high-energy ion implantation created not only a deep channel, but also a wide channel in the vertical direction to the SiO₂/Si interface. Figure 24 and Figure 25 show the Gumbel plots of V_RMS for the standard, narrow, middle, and deep samples and the V_BS dependance of V_RMS for the narrow, middle, and deep samples, respectively [57,65].

The channel length and width were 0.22 and 0.28 μm, respectively, I_DS was 100 nA, and V_BS in Figure 24 was −1.5 V and varied from −1.0 V to −2.0 V in Figure 25, respectively. The V_RMS values for the standard and Narrow samples are the same, and the frequency of large V_RMS decreases with an increase in n-Si width and/or depth. This means that RTN cannot be decreased by the 20 nm buried channel, but can be decreased by forming a buried channel of 40 nm and more. By increasing the back bias, V_RMS increases for all samples, and the effect of V_BS remarkably appeared for the wide sample. By applying the back bias, the channel pushes onto the SiO₂/Si interface, and the channel thickness decreases. The buried channel is extremely effective for decreasing RTN because the channel is separated from SiO₂/Si interface and the wide channel becomes difficult to form the percolation path. Furthermore, the buried channel MOSFET in the isolated well was employed to evaluate V_BS dependance [64], and V_BS can be varied from 0 V in this structure because the well voltage can be changed freely. The gate length and gate width of the MOSFETs are 0.32 and 0.32 μm, respectively, I_DS was 1 μA, vs. was 1.5 V, and V_well of the normal well and isolated well were 0 and 1.5 V, respectively; thus, V_BS was set at −1.5 and 0 V for the normal well and isolated well, respectively.

Figure 26 shows the Gumbel plot of the V_RMS for the buried channel and surface channel MOSFETs with the back bias conditions of 0 and −1.5 V. V_RMS of the buried channel MOSFETs at V_BS = −1.5 V is significantly less than those of surface channel; however, that at V_BS = 0 V is larger than those of the surface channel even though those of the surface channel do not depend on V_BS. Figure 27 shows the normal probability plot of the subthreshold swing for the same sample of Figure 26. The subthreshold swing of buried channel MOSFETs with V_BS = 0 is much smaller than the others. A strong relationship between the subthreshold swing and V_RMS has been reported [64]. The result strongly suggests that the increase in V_RMS is enlarged by the physical origin, which increases the subthreshold swing, and the origin is an enhancement of the percolation path formation [64]. Note that RTN has to be enhanced by a minimal small gate control effect on the channel. Furthermore, the variability of the threshold voltage is increased using the buried channel MOSFETs; thus, we cannot introduce buried channel MOSFETs when the fixed pattern noise is critical for device performance.

3.6.2. Asymmetry Source and Drain Width MOSFETs

Figure 28 shows the layout structure of rectangular and trapezoidal shape MOSFETs used in this experiment [62,63]. In the trapezoidal MOSFETs, when current flows from the left to right direction, the source has a wide gate width, and when current flows from the right to left direction, the source has a shallow gate width. The Gumbel plots of V_RMS for trapezoidal ((a)W_D < W_S and (b) W_S < W_D) and (c) rectangular MOSFETs are shown in Figure 29 [62]. The gate width of rectangular MOSFETs was set as the average of the gate width of trapezoidal MOSFETs. I_DS was varied from 0.1 to 11 μA for constant V_BS of −1.9 V and V_DS of 1.4 V. In (c) rectangular MOSFETs, similar phenomena, as shown in Figure 19, are obtained. In contrast, in the trapezoidal MOSFETs, V_RMS increases with an increase in I_DS (V_GS), and those of W_D < W_S are larger than those of W_S < W_D. V_DS is larger than V_GS in this experiment. MOSFETs were operated in the saturation region, and the channel formed near the source. Increasing I_DS increases electron density in the channel, and the electron density at the source of MOSFETs with W_D < W_S is less than that with W_S < W_D. These characteristics indicate that the influence of a charged trap reduces at a high carrier density condition [39,60,62]. This means that the electron density and the location in the channel are important factors affecting RTN characteristics. RTN characteristics were evaluated for various V_DS using rectangular and trapezoidal MOSFETs.

Figure 30 shows the Gumbel plots of V_RMS for trapezoidal ((a) W_D < W_S and (b) W_S < W_D) and (c) rectangular MOSFETs. V_DS was varied from 0.1 V to 1.4 V for constant I_DS of 10 μA and V_BS of −1.9 V [63]. The V_DS dependance of V_RMS for the (c) rectangular and (b) trapezoidal with W_S < W_D MOSFETs is the same, and V_RMS increases as V_DS increases, monotonically. The dependance of (b) trapezoidal with W_S < W_D on V_DS is larger than that of rectangular MOSFETs. In contrast, V_RMS increases with an increase in V_DS at less than 0.3 V; however, V_RMS decreases with an increase in V_DS at >0.3V for trapezoidal MOSFETs with W_S > W_D. When V_DS is smaller than the pinch-off voltage (V_GS-V_TH = 0.3 V in this experiment), the channel is uniformly formed under the gate oxide, and the channel vanishes at the drain edge at the pinch-off voltage. The vanished region expands with increasing V_DS. On the other hand, I_DS was set at a constant of 10 μA, and this means that V_GS decreases as V_DS increases at less than a pinch-off voltage of 0.3V. In rectangular MOSFETs, V_RMS increases with a decrease in V_GS, which is the same effect as shown in Figure 7. In trapezoidal MOSFETs with W_S < W_D, V_DS dependance was enhanced by reducing the channel width. In trapezoidal MOSFETs with W_D < W_S, V_DS dependance is the same as others at less V_DS than a pinch-off voltage of 0.3 V. However, the opposite dependency is obtained at larger V_DS than the pinch-off voltage. It is considered that the apparent gate width of MOSFETs (W_D < W_S) increases when the pinch-off point reaches the source, and then, the size effect of V_RMS shown in Figure 6 is obtained. These data imply that the noise strength depends heavily on operation conditions, which means that the location and electron density in a channel are critical for RTN generation.

Although using trapezoidal MOSFETs in real electronic devices is difficult, changing the shape of MOSFETs is very useful to obtain much information about RTN characteristics. For example, the effect of trap at the isolation edge can be evaluated using octagonal MOSFETs, which have only a gate edge and no shallow trench isolation edge [62].

3.6.3. MOSFETs with Atomically Flat Gate Insulator/Si Interface

The roughness of the interface between the gate insulator and Si is essential for MOSFETs. The interface roughness degrades not only electron mobility [66,67,68,69,70,71] and gate dielectric reliability [72,73,74], but also noise generation [71,75,76]. An atomically flat interface [77,78,79,80,81,82,83,84] is effective for reducing low-frequency noise [79,83,84,85,86,87].

Figure 31 shows images of an atomically flat surface and as-received Si(100) measured by atomic force microscopy (AFM). The atomically flat surface was formed in the active region with shallow trench isolation and was measured after the gate oxide formation and following oxide stripping [84]. The average roughness (Ra) of the conventional surface is 0.12 nm, which is the same as the initial surface of Si(100). In an atomically flat surface, a step and terrace structure can be obtained, and the step height is the same as the monoatomic step length of Si(100) of 0.135 nm. The terrace width (L) is defined by the following equation using the off-angle (θ) to the just (100) orientation. The average roughness in the trace of the atomically flat interface was less than 0.04 nm, which is the detection limit of our AFM system.

$$\mathrm{L}=\frac{0.135}{\tan \mathsf{\theta }}\left(\mathrm{nm}\right)$$

(16)

Figure 32 shows the Gumbel plot of V_RMS for the atomically flat and conventional SiO₂/Si interface [84]. The noise of the atomically flat interface is less than that of the conventional interface. This means that introducing the atomically flat interface is extremely effective for reducing RTN as well as 1/f noise [86,87,88]. The atomically flat surface was formed before gate oxidation in this experiment [84].

To implement the surface flattening process, a low temperature of less than 900 °C and low oxidation species, such as O₂ and H₂O, must be required [81,82,85]. There is another method for flattening the surface first and keeping it during the process steps preceding gate oxidation [85,87,88]. Other problems exist, such as STI edge shape and dopant segregation, and the solutions to these problems may affect not only MOSFET characteristics, but also noise [84]. The flattening process just before the gate oxidation is superior to the flattening process in the first step for introducing interface flattening between SiO₂ and Si, and this can be obtained by low temperature Ar annealing by reducing oxidation species.

4. Conclusions

The importance of low-frequency noise in LSI, and various effects on RTN, such as MOSFETs’ size, bias and operation conditions, and device structures, are described. The measurement technique using the array test circuit and the extraction of important parameters (time constants and amplitude) in RTN characteristics are also described. Time constants can be extracted essentially using classical equations; however, it is not as simple when downsizing MOSFETs and reducing the number of channel electrons, and the percolation path is formed. Variability of low-frequency noise increases with shrinkage of MOSFETs. In this paper, we evaluated relatively large planer MOSFETs (L = 0.22~0.4 μm), unfortunately. The size of MOSFETs has been downscaled to less than l0 nm and the structure has changed the planer to FinFET, recently. We have to continue the evaluation of such miniaturized and new structure devices. To assess the effect of this noise on MOSFETs, we have to understand their characteristics statistically, and then, sufficient samples must be accurately evaluated in a short period.