# CMOS Inverter as Analog Circuit: An Overview

^{1}

^{2}

## Abstract

**:**

## 1. Introduction

_{on}/I

_{off}ratio, as the computing capability has been constrained by the power consumption, instead of the speed of the transistor [1,2]. Such digital-driven scaling leads to several issues in analog circuit design. For instance, the intrinsic gain of transistor has been significantly reduced due to the short-channel effect. Moreover, the threshold voltage of transistor has not been scaled at the same rate of the supply voltage scaling, in order for suppressing the leakage current [3]. That means the “normalized” voltage headroom for analog circuit has been reduced. Therefore, adopting conventional gain-boosting techniques (i.e., cascode) becomes more and more difficult in modern CMOS technology [4]. What makes things worse is that the gate-overdrive voltage of analog circuits should be decreased as the voltage headroom reduces, which increases the sensitivity of analog circuits to the device mismatch [5]. We can observe such trend in Figure 1, which compares the stacked common-source (CS) amplifier to the non-stacked CS amplifier [6,7]. Figure 1a,b shows the normalized gain of CS amplifiers with respect to V

_{DD}/V

_{TH}and the normalized large-signal bandwidth with respect to the normalized current dissipation, respectively. The gain of the stacked topology decreases much steeper than that of the non-stacked, which means that the gain enhancement from the cascode topology becomes less attractive in the modern CMOS technology where the voltage headroom is reduced. Moreover, the achievable bandwidth of the stacked amplifier is much less than the non-stacked amplifier even when it dissipates more current, because the increased self-loading from the stacked transistor degrades the rise/fall time. In addition, [6] revealed that the input-referred noise becomes even worse in the stacked topology because the transconductance g

_{m}increases due to the reduced gate-overdrive voltage.

_{m}of PMOS as well as that of NMOS at the same time. When we compare the two circuits given in Figure 2, we can find that they have the same load capacitance, including the self-loading. However, in case of the CMOS inverter, the overall g

_{m}is the sum of g

_{mN}and g

_{mP}; thus, we can get a higher bandwidth. This aspect becomes much powerful in recent process technologies, where strained silicon technique enhances the PMOS current density as much as that of NMOS [10,11,12]. In fact, when we consider the sizing, the P/N ratio of the inverter for analog intent is different to the digital intent. In order technology where the strained silicon technique is not adopted, digital inverter has PMOS which is generally twice larger than NMOS, because we have to match the strength of PMOS and NMOS, since we assume that only one of the PMOS and NMOS is turned on at a time. However, in such analog inverter, the optimum is at around P/N ratio of unity, where we can achieve the highest g

_{m}per input capacitance [13]. Note that the PMOS and NMOS continuously run together in analog mode. That means we were not able to fully utilize the g

_{mP}in older technology nodes. In other words, the strained silicon boosts the current density of PMOS to be matched to that of NMOS, and therefore it makes the analog inverter become more powerful.

## 2. CMOS Inverter as an Amplifier

_{PD}. In addition, the signal-to-noise (SNR) is another main issue of concern. The total integrated noise due to the thermal noise of the resistor is given as to:

_{m}, so the pole at the input of CG amplifier is given as to:

_{PD}is generally much larger than the load capacitance of the CG amplifier. Since the 1/g

_{m}can be reduced by drawing more current by the current source (I

_{B}), we can achieve high gain as well as high bandwidth at the cost of power consumption. In addition, [51,52] proposed a regulated-cascode (RGC) TIA, which further improves the gain-bandwidth product of TIA. However, the effectiveness of such stacked configuration has been degraded due to the aforementioned scaling issue, now many researchers have ended up with the resistive feedback inverter TIA. The inverter-TIA still have a similar trade-off as the passive TIA; however, the input resistance of the resistive feedback inverter is R/(1 + A), where A is the gain of the inverter. That means that the trade-off is relaxed by the factor of A. Additionally, note that there is no other path that the photo-current can flow; the gain of this TIA equals R. Readers may consult [28] for a detailed history of TIA evolution.

_{PD}. Recent state-of-the-arts works in [15,24,29] have combined the series peaking and the inductive feedback, and therefore considerable high-bandwidth at a quite impressive energy efficiency is achieved. Moreover, the authors in [29] saved inductor area by incorporating T-coil inductive peaking.

## 3. High Speed Buffer

_{m}is the sum of g

_{mN}and g

_{mP}. Equation (5) leads to the transfer function as:

_{o}C

_{L}. That is, the resistive feedback increases the 3 dB bandwidth by 1/R

_{F}C

_{L}. Simulated bandwidth shown in Figure 9b verifies (7). Moreover, thanks to the negative feedback, this circuit is less sensitive to the PVT variations compared to the normal CMOS inverter.

- Since AC coupling completely blocks the DC component of the clock signal, the duty-cycle distortion does not propagate. Thanks to the self-biasing to the cross-over voltage, the duty-cycle is restored to the ideal value regardless of the input duty-cycle (Figure 11).
- Combined with the low-pass characteristic of the inverter, AC coupling results in a band-pass characteristic. Because a band-pass filter attenuates all out-of-band noise, it suppresses phase noise and jitter from the input clock [54].
- Because the clock buffer does not have to deal with a wide-band signal, the high-frequency cut-off frequency can be fairly high (<~1/10 of the clock frequency). Therefore, a small capacitor can be used [39].

_{F}is translated to the input resistance of R

_{F}/(1 + A

_{F}), where A

_{F}is the DC gain of the inverter. Then, we obtain:

_{L}is the load capacitance of the buffer. Figure 11 shows an example of the simulated duty-cycle transfer function of an AC-coupled inverter.

## 4. Output Driver for High-Speed Wireline Communication

_{swing}/100), whereas the parallel termination flows to 25 Ω (I = V

_{swing}/25). As a result, the parallel termination dissipates 4× higher current to achieve a same voltage swing. On the other hand, the main downside of SST driver originates to the fact that there is no ideal switch in IC. There are two types of practical SST implementation, N-over-N and P-over-N configurations, as shown in Figure 12. It is well known that the N-over-N works well only for low swing applications, whereas the P-over-N is appropriate for higher swing applications. Note that the P-over-N structure is a CMOS inverter. Basically, their approach is the same. Instead of using an ideal 0-Ω switch, they utilize the finite resistance of switch transistor; if the turn-on resistance equals to 50-Ω, a single transistor can work as the combination of the ideal switch and the resistor. The 50-Ω impedance is generally calibrated by adjusting the number of activated driver slices and the gate-overdrive voltage. The main challenge here is the non-linear nature of CMOS transistor does not let the transistors have a constant resistance over the swing range [42]. For example, when the output voltage increases, the V

_{DS}of the pull-down NMOS (M

_{N1}, M

_{N3}) increases and causes the NMOS to fall into the saturation region, where the output impedance becomes very high. Note that the linearity is a function of V

_{DS}, and the V

_{DS}range equals the output swing.

_{DS}of the transistors is reduced. The downside of this approach is the increased transistor size. If 25-Ω resistance is used, the size of transistor is doubled so that both the input capacitance and the output self-capacitance are doubled, each of which increases burdens of the pre-driver stage and degrades the bandwidth of the driver itself, respectively. Note that the transistors should operate in the linear region for better linearity, where the current density is much lower than that in the saturation region. Therefore, the device size is generally enormously large.

_{m}, instead of 1/g

_{ds}. That means we can achieve a high current density of the saturation region and a low output impedance from 1/g

_{m}as well. In addition, the g

_{m}is easy to be regulated by using a well-known constant-g

_{m}bias circuit [13,57].

_{in}is the input capacitance of the driver [50]. We can find that the feedback introduces both zero (at $\frac{1}{{R}_{F}{C}_{in}}$) and pole (at $\frac{{g}_{m}{r}_{o}+1}{{R}_{F}{C}_{in}}$). As a result, the output impedance becomes r

_{o}at a very high frequency. Therefore, a designer should carefully choose a proper R

_{F}such that guarantees the zero frequency is higher than the Nyquist frequency of the transmit data.

_{o}, the output impedance deviates from 1/g

_{m}, which is maintained by the constant-g

_{m}biasing, when the output swing increases. It also dissipates a higher current than that of the conventional SST driver due to the short-circuit current. However, as the data rate increases, the pre-driver’s dynamic switching power, which is consumed for driving high input capacitance, dramatically increases. Note that the dynamic power is proportional to the switching frequency and the capacitance, whereas the driver’s current consumption is fixed regardless of the data rate (I = V

_{swing}/100Ω). As a result, it surpasses the static power consumption of the output driver [42]. As a result, the pre-driver power reduction, thanks to the small input capacitance of the resistive-feedback SST driver, is able to fully compensate the increased static power.

## 5. Conclusions

## Funding

## Conflicts of Interest

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**Figure 10.**(

**a**) AC-coupled resistive feedback inverter and (

**b**) Miller approximation to calculate high-pass cut-off frequency.

**Figure 12.**Conceptual diagram of source-series terminated (SST) driver and practical implementation of N-over-N and P-over-N SST configurations.

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Bae, W.
CMOS Inverter as Analog Circuit: An Overview. *J. Low Power Electron. Appl.* **2019**, *9*, 26.
https://doi.org/10.3390/jlpea9030026

**AMA Style**

Bae W.
CMOS Inverter as Analog Circuit: An Overview. *Journal of Low Power Electronics and Applications*. 2019; 9(3):26.
https://doi.org/10.3390/jlpea9030026

**Chicago/Turabian Style**

Bae, Woorham.
2019. "CMOS Inverter as Analog Circuit: An Overview" *Journal of Low Power Electronics and Applications* 9, no. 3: 26.
https://doi.org/10.3390/jlpea9030026