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Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications

School of Electronics Engineering, Vellore Institute of Technology, Vellore 632014, India
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J. Low Power Electron. Appl. 2019, 9(3), 21; https://doi.org/10.3390/jlpea9030021
Received: 28 May 2019 / Revised: 24 June 2019 / Accepted: 30 June 2019 / Published: 2 July 2019
Due to the reduction in technology scaling, gate capacitance and charge storage in sensitive nodes are rapidly decreasing, making Complementary Metal Oxide Semiconductor (CMOS) circuits more sensitive to soft errors caused by radiation. In this paper, a low-power and high-speed single event upset radiation hardened latch is proposed. The proposed latch can withstand single event upsets completely when the high energy particle hit on any one of its intermediate nodes. The proposed latch structure comprises of four CMOS feedback schemes and a Muller C-element with clock gating technique. For the sake of comparison, the proposed and the existing latches in the literature are implemented in 45nm CMOS technology. From the post layout simulation results, it may be noted that the proposed latch achieves 8% low power consumption, 95% less delay, and a 94% reduction in power-delay-product compared to the existing single event upset resilient and single event tolerant latches. Monte Carlo simulations show that the proposed latch is less sensitive to process, voltage, and temperature variations in comparison with the existing hardened latches in the literature. View Full-Text
Keywords: clock gating; radiation hardened latch; reliability; single event transient; single event upset clock gating; radiation hardened latch; reliability; single event transient; single event upset
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S, S.K.; S, K. Design and Analysis of SEU Hardened Latch for Low Power and High Speed Applications. J. Low Power Electron. Appl. 2019, 9, 21.

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