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J. Low Power Electron. Appl. 2018, 8(4), 35;

Path Planning for Highly Automated Driving on Embedded GPUs

Hardware/Software Co-Design, Department of Computer Science, Friedrich-Alexander University Erlangen-Nürnberg (FAU), 91054 Erlangen, Germany
GIGATRONIK Ingolstadt GmbH, Ingolstadt, 85080 Gaimersheim, Germany
Pre-/Concept Development Automated Driving, AUDI AG, 85045 Ingolstadt, Germany
Author to whom correspondence should be addressed.
Received: 24 August 2018 / Revised: 21 September 2018 / Accepted: 28 September 2018 / Published: 2 October 2018
(This article belongs to the Special Issue Automotive Low Power Technologies)
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The sector of autonomous driving gains more and more importance for the car makers. A key enabler of such systems is the planning of the path the vehicle should take, but it can be very computationally burdensome finding a good one. Here, new architectures in Electronic Control Units (ECUs) are required, such as Graphics Processing Units (GPUs), because standard processors struggle to provide enough computing power. In this work, we present a novel parallelization of a path planning algorithm. We show how many paths can be reasonably planned under real-time requirements and how they can be rated. As an evaluation platform, an Nvidia Jetson board equipped with a Tegra K1 System-on-Chip (SoC) was used, whose GPU is also employed in the zFAS ECU of the AUDI AG. View Full-Text
Keywords: autonomous driving; path planning; embedded GPUs; parallelization autonomous driving; path planning; embedded GPUs; parallelization

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Fickenscher, J.; Schmidt, S.; Hannig, F.; Bouzouraa, M.E.; Teich, J. Path Planning for Highly Automated Driving on Embedded GPUs. J. Low Power Electron. Appl. 2018, 8, 35.

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J. Low Power Electron. Appl. EISSN 2079-9268 Published by MDPI AG, Basel, Switzerland RSS E-Mail Table of Contents Alert
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