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J. Low Power Electron. Appl. 2017, 7(4), 32; https://doi.org/10.3390/jlpea7040032

Forwarding Path Limitation and Instruction Allocation for In-Order Processor with ALU Cascading

1
Department of Computer Science, Faculty of Informatics, Kogakuin University, 1-24-2 Nishi-shinjuku, Shinjuku-ku, Tokyo 163-8677, Japan
2
Department of Computer Science and Engineering, Toyohashi University of Technology, 1-1 Hibarigaoka Tenpaku-cho, Toyohashi-shi, Aichi-ken 441-8580, Japan
3
Advanced Networking Division, Information Technology Center, Nagoya University, Furo-cho, Chikusa-ku, Nagoya-shi, Aichi-ken 464-8601, Japan
*
Author to whom correspondence should be addressed.
Received: 6 November 2017 / Revised: 5 December 2017 / Accepted: 12 December 2017 / Published: 14 December 2017
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Abstract

Much research focuses on many-core processors, which possess a vast number of cores. Their area, energy consumption, and performance have a tendency to be proportional to the number of cores. It is better to utilize in-order (IO) execution for better area/energy efficiency. However, expanding two-way IO to three-way IO offers very little improvement, since data dependency limits the effectiveness. In addition, if the core is changed from IO to out-of-order (OoO) execution to improve Instruction Per Cycle(IPC), area and energy consumption increases significantly. The combination of IO execution and Arithmetic Logic Unit(ALU) cascading is an effective solution to alleviate this problem. However, ALU cascading is implemented by complex bypass circuits because it requires a connection between all outputs and all inputs of all ALUs. The hardware complexity of the bypass circuits increases area, energy consumption, and delay. In this study, we proposed a mechanism that limits the number of the forwarding paths and allocates instructions to ALUs in accordance with the limited paths. This mechanism scales down bypass circuits to reduce the hardware complexity. Our evaluation results show that our proposed mechanism can reduce the area by 38.7%, the energy by 41.1%, and the delay by 23.2% with very little IPC loss on average, as compared with the conventional mechanism. View Full-Text
Keywords: ALU cascading; in-order execution; area/energy efficiency ALU cascading; in-order execution; area/energy efficiency
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Kobayashi, R.; Suzuki, A.; Shimada, H. Forwarding Path Limitation and Instruction Allocation for In-Order Processor with ALU Cascading. J. Low Power Electron. Appl. 2017, 7, 32.

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