Ultra-Low-Power ICs for the Internet of Things (2nd Edition)

After the success of the first edition [1], we are delighted to launch this second edition of our Special Issue focusing on Ultra-Low-Power (ULP) Integrated Circuits (ICs) operating within a tight power budget, which represent an essential element in building electronic devices that rely less and less on batteries. Our aim is, once again, to present novel IC design strategies to reduce the cost and power consumption of devices.

In this Special Issue, Tran et al., Pham et al., and Namdari et al. (Contributions 1–3) discuss IC solutions for biomedical applications. In particular, two capacitively coupled chopper instrumentation amplifiers (CCIAs) are presented as part of a 180 nm technology process for monitoring neural potentials. Tran et al. present a chopping ripple reduction to 0.36 mV, with an overall area of 0.123 mm² and a power consumption of 1.87 µW at a supply voltage of 1 V. Pham et al. show a programmable bandwidth from 0.2 to 10 kHz in an area of 0.083 mm² and an overall power consumption of 0.47 µW with two supply voltages at 0.2 V and 0.8 V.

A compact, universal, multi-mode Gm-C filter centered at 462 Hz using a 180 nn, with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW, is reported in the work by Namdari et al. (Contribution 3). The work by Nicolini et al. (Contribution 4) presents a 16-channel in-pixel neural analog front end, enhancing both the system common-mode rejection ratio (SCMRR) and the common-mode interference (CMI) range with a power consumption of 3.77 μW per channel in 180 nm technology nodes.

This Special Issue then addresses general-purpose IC blocks (i.e., Contributions 5–8).

Wang et al. (Contribution 5) design a novel low-power MOS-only voltage reference, showing 21.7 ppm/°C of variation in a temperature range from −40 °C to 120 °C, consuming 23.2 nW with a supply voltage of 0.8 V in 55 nm technology nodes.

Morell et al. (Contribution 6) propose a novel, stepwise charging driver circuit for four-phase adiabatic logic and validate it through an analysis in 15 nm FinFET technology nodes.

The work by Shah et al. (Contribution 7) describes a bulk-driven second-generation Current Conveyor (CCII) operating at 0.35 V, offering a linear current drive up to 2.5 µA, while consuming a total quiescent current of 2.86 µA.

Della Sala et al. (Contribution 8) report an approach to designing digital-based operational transconductance amplifiers (OTAs) by ensuring that the gates operate with a well-defined quiescent current and output voltage, meaning that they are resistant to PVT variations.

Regarding security applications, in their article, Zheng et al. (Contribution 9) propose an 8-Transistor (8T) power-gated Physically Unclonable Function (PUF) implemented in 65 nm technology, built to swiftly eliminate data remanence and maximize physical mismatch.

Among the faster and thus more power-hungry solutions, Naveed et al. (Contribution 10) present a multiplier and Siddiqui et al. (Contribution 11) present a VCO. Contribution 10 reports a delay-locked loop (DLL)-based frequency 8× multiplier with a 22 nm FDSOI power consumption of 130 µW at 0.8 V supply with a new simple duty cycle correction circuit that is XOR logic-based for frequency multiplication. In Contribution 11, a tunable quadrature differential LC CMOS voltage-controlled oscillator (VCO) with a D flip-flop (DFF) frequency divider, consuming 2.02 mW with a tuning range of 4.4 to 5.7 GHz and showing a phase noise of −118.36 dBc/Hz at a 1 MHz offset frequency with a 1.2 V supply voltage, is designed through a 65 nm technology process.

Last, but not least, Baker et al. (Contribution 12) review advancements in wireless short-range communication (i.e., Bluetooth, RFID, and NFC), adding further value to this second Special Issue volume.

In summary, these research publications explore a wide array of prospects inspired by these innovative designing techniques, covering a broad range of areas in the ULP/ULV IC field.