A High-Efficiency Piezoelectric Energy Harvesting and Management Circuit Based on Full-Bridge Rectification

Abstract

This paper presents a high-efficiency piezoelectric energy harvesting and management circuit utilizing a full-bridge rectifier (FBR) designed for powering wireless sensor nodes. The circuit comprises a rectifier bridge, a fully CMOS-based reference source, and an energy management system. The rectifier bridge uses a PMOS cross-coupled structure to greatly reduce the conduction voltage drop. The CMOS reference source provides the necessary reference voltage and current. The energy management system delivers a stable 1.8 V to the load and controls its operation in intermittent bursts. Fabricated with a 110 nm CMOS process, the circuit occupies an area of 0.6 mm², and is housed in a QFN32 package. Test results indicate that under 40 Hz frequency and 4 g acceleration vibrations, the chip’s energy extraction power reaches 234 $\mathsf{\mu }$W, with the load operating every 3 s at a supply voltage of 1.8 V. Thus, this FBR interface circuit efficiently harnesses the energy output from the piezoelectric energy harvester.

1. Introduction

With the rapid development of the Internet of Things (IoT), wireless sensor network technology has become increasingly sophisticated, expanding its range of applications. These networks are now extensively used in various fields, including military, education, environmental monitoring, and healthcare [1,2,3,4,5]. However, as the deployment of wireless sensor networks scales up, often comprising thousands of sensor nodes, the challenge of powering these nodes becomes significant. Traditional battery-powered methods pose several issues: limited lifespan, environmental pollution, and the need for manual maintenance and replacement, all of which increase the operational costs of wireless sensor networks. Furthermore, the bulky size of batteries can restrict the application of these networks in confined spaces. To overcome the limitations of traditional batteries, researchers are focusing on energy harvesting technologies that collect energy from the environment to power wireless sensor nodes [6,7,8].

Common environmental energy sources include solar, wind, thermal, and vibration energy [9,10,11,12]. Unlike other forms, vibration energy is ubiquitous, found in human movements, vehicle operations, and machinery activities. Vibration energy harvesting primarily relies on inertial forces, and can be enclosed within sealed spaces, making it suitable for extreme weather conditions or tight spaces without affecting the collection of environmental vibration energy. Additionally, vibration energy has a high density and is easy to capture [13,14,15]. There are three primary methods of vibration energy harvesting: electromagnetic, electrostatic, and piezoelectric. Among these, piezoelectric energy harvesters (PEH) convert vibration energy into electrical energy using the piezoelectric effect: when piezoelectric materials deform under external force, they generate alternating current by producing polarized charges on their surfaces [16]. PEHs are known for their simple structure, high energy density, and the ease with which they can be miniaturized using microfabrication processes.

Since the PEH output is alternating current, it cannot directly power loads. Additionally, advancements in microfabrication have reduced the size of PEHs, limiting their output power to the micro-watt range. Therefore, an energy harvesting and management circuit is necessary between the PEH output and the load. A practical solution involves using a Full-Bridge Rectifier (FBR) to capture the electrical energy generated by the PEH in a storage capacitor. High-efficiency energy harvesting and management circuits can maximize the utility of the PEH-generated energy, significantly extending the lifespan and operational range of wireless sensor networks, which is crucial for their applications [17,18,19,20].

Based on this analysis, this paper presents a piezoelectric energy harvesting and management circuit that uses an FBR as the interface circuit. By operating the cross-coupled PMOS transistors in the deep linear region at high input voltages, the source-drain voltage drop during conduction is significantly reduced, while diode-connected NMOS transistors prevent reverse current flow. The fully CMOS-structured reference source addresses low power consumption issues and includes tuning circuits to minimize its temperature coefficient. The energy management circuit ensures that sufficient energy is stored in the capacitor to power the load and provides a stable voltage for the load’s operation.

The paper is organized as follows. Section 2 analyzes the output energy modeling of the PEH. Section 3 and Section 4 detail the design and overall measurement results of the proposed piezoelectric energy harvesting and management circuit modules. Finally, Section 5 presents the conclusions.

2. Output Energy Modeling

A piezoelectric energy harvester (PEH) is a device that converts vibration energy into electrical energy using piezoelectric materials, based on the principle of the piezoelectric effect. The classic architecture for PEHs is the cantilever beam structure, as depicted in Figure 1, which consists of a base, cantilever beam, mass block, and piezoelectric material [21]. The equivalent model of a cantilever beam PEH can be regarded as an electromechanical coupling model [22], illustrated in Figure 2a. In this model, voltage V represents the external vibration strength, inductance L represents the equivalent mass M, capacitance C represents the reciprocal of the mechanical stiffness K, resistance R represents the mechanical damping D, transformer n represents the electromechanical coupling coefficient, and capacitance $C_P$ represents the inherent capacitance of the piezoelectric material. When the PEH vibrates stably at its natural resonance frequency $f_P$, the electromechanical coupling model shown in Figure 2a can be further simplified to the equivalent circuit shown in Figure 2b, which is a parallel circuit comprising a current source $I_P$, a resistor $R_P$, and a capacitor $C_P$. The expressions for $I_P$ and $R_P$ are as follows:

$$I_P=I_{P0}sin{\omega }_{P}t=I_{P0}sin2\pi f_{P}t$$

(1)

$$R_P=R/n^2$$

(2)

$$f_P=1/2\pi \sqrt{LC}$$

(3)

Figure 1. Structure of a cantilever beam PEH [23].

Figure 2. (a) Equivalent electrical model of a cantilever beam PEH, (b) equivalent circuit of (a) at resonance [23,24].

Among these, the value of resistor $R_P$ is significantly higher than 1/${\omega }_P$$C_P$, making its impact negligible in circuit design. In the open circuit state, the equivalent current source $I_P$ only loads the parasitic capacitance $C_P$, thus the PEH’s open circuit voltage waveform resembles the current source $I_P$’s waveform, with a 90° phase shift. Figure 3 illustrates the open circuit voltage waveform of the PEH, where voltage $V_P$ represents its open circuit voltage and $V_{P0}$ is its peak open circuit voltage.

$$V_{P0}={\displaystyle \frac{I_{P0}}{C_P{\omega }_P}}$$

(4)

Figure 3. Open circuit voltage waveform of a cantilever beam PEH.

Given that the equivalent current source of a cantilever beam PEH maintains a stable sine wave during steady oscillation, with nearly constant frequency and amplitude, the cantilever beam PEH can be considered a constant excitation source for its energy extraction circuit.

With continuous advancements in manufacturing processes, PEHs are moving towards miniaturization. Shrinking device sizes have resulted in cantilever beam PEHs having higher resonant frequencies, reaching hundreds or even thousands of hertz. However, environmental vibrations typically occur at lower frequencies, mostly below 100 Hz, which substantially differ from the PEHs’ resonant frequencies, thereby reducing the power generation efficiency of cantilever beam PEHs. To address these shortcomings, this paper utilizes a two-stage vibration structure PEH with up-conversion functionality [25,26,27], as illustrated in Figure 4.

Figure 4. Structure of a two-stage vibration structure PEH [26].

The energy harvester includes two stages of vibrators. The first stage is a U-shaped inductive vibrator with a mass block, designed to sense low-frequency environmental vibrations typically below 50 Hz. The second stage is a cantilever beam generating vibrator, with a natural resonance frequency usually above 100 Hz. At the corresponding ends of the inductive and generating vibrators, magnets are placed, arranged like poles facing each other to achieve magnetic coupling through repulsion.

This PEH uses magnetic coupling to realize “up-conversion”. When the environmental vibration intensity is weak, the inductive vibrator cannot overcome the magnetic repulsion between the magnets and can only perform minor vibrations around the equilibrium position, generating minimal electrical energy. As the vibration intensity increases, the vibration amplitudes of both vibrators grow. Once the vibration intensity surpasses a threshold, the inductive vibrator overcomes the magnetic repulsion, resulting in large vibration amplitudes and exciting the generating vibrator to oscillate at its natural resonance frequency, producing a substantial amount of electrical energy. This method significantly enhances power generation efficiency compared to cantilever beam PEHs.

Since the resonance frequency of the second-stage generating vibrator is much higher than the first-stage inductive vibrator’s vibration frequency, the generating vibrator in the cantilever beam structure experiences impulse excitation. Upon excitation, the generating vibrator performs damped oscillations at its natural resonance frequency, leading to an equivalent current source $I_P$ waveform, as shown in Figure 5. When the vibration intensity is below the threshold, the current is very weak. Once the intensity exceeds the threshold, the equivalent current source $I_P$ undergoes periodic damped oscillations. In Figure 5, two frequencies $f_1$ and $f_2$ are shown, representing the inductive stage vibration frequency (environmental vibration frequency) and the generating stage vibration frequency (generating stage’s natural resonance frequency), respectively, with $f_1\ll f_2$. Similarly, the open circuit voltage waveform of the two-stage vibration structure PEH resembles the current source $I_P$ waveform, with a 90° phase difference.

Figure 5. Equivalent current source $I_P$ waveform of the two-stage vibration structure PEH.

3. Circuit Implementation

Figure 6 illustrates the proposed architecture of the FBR and energy management circuit system. The PEH is represented as a parallel circuit of a current source $I_P$ and a capacitor $C_P$. The rectifier bridge converts the AC output from the PEH into DC, and a storage capacitor stores the rectified electrical energy. The reference source supplies the reference voltage and current for the dual-threshold management circuit and the low dropout regulator (LDO). The dual-threshold management circuit monitors the voltage of the storage capacitor and activates a switch to transfer the stored energy to subsequent circuits once the capacitor’s voltage is sufficiently high. Since the storage capacitor’s voltage is unstable and cannot directly power the load, an LDO is placed between the load and the storage capacitor. The rectifier bridge, reference source, dual-threshold management circuit, and LDO are integrated on-chip, while the storage capacitor is an off-chip tantalum capacitor. Due to the PEH’s miniaturized design, its output power is only in the micro-watt range. Therefore, the circuit’s power consumption must be minimized before the switch is activated, during the storage capacitor’s charging process. In this design, both the reference source and the dual-threshold management circuit are optimized for ultra-low power consumption.

Figure 6. Proposed full-bridge rectifier and energy management circuit system architecture.

3.1. Cross-Coupled Rectifier Bridge Circuit

The output of the PEH is in AC form and cannot be directly stored in a storage capacitor, necessitating an interface circuit for AC–DC conversion. The diode FBR circuit is one common method to achieve this, as shown in Figure 7. This circuit consists of four diodes, each with a forward voltage drop of $V_D$. When the input voltage $V_{IN}$ is positive and exceeds 2$V_D$, the circuit loop formed by diodes $D_1$ and $D_4$ conducts, allowing the output voltage $V_O$ to follow the input voltage $V_{IN}$. Conversely, when the input voltage $V_{IN}$ is negative and below -2$V_D$, the loop formed by diodes $D_2$ and $D_3$ conducts, with the output voltage $V_O$ inversely following the input voltage $V_{IN}$. Traditional rectifier bridges face two major drawbacks: firstly, when the input voltage $|V_{IN}|<2V_D$, all input energy is wasted; secondly, when $|V_{IN}|>2V_D$, the 2$V_D$ forward voltage drop results in significant energy loss. Thus, traditional rectifier bridges are not ideal for PEH-based energy harvesting systems.

Figure 7. Traditional rectifier bridge.

Transistor-based rectifier bridges, particularly cross-coupled designs, have become prevalent due to their low forward voltage drops. The rectifier bridge design in this work is shown in Figure 8 [28,29,30]. Transistors $M_{P1}$ and $M_{P2}$ are cross-coupled, while transistors $M_{N1}$ and $M_{N2}$ are diode-configured. Cross-coupled PMOS transistors operate in the deep linear region at higher input voltages, reducing the source-drain voltage drop significantly during conduction. The diode-connected NMOS transistors have a near-zero threshold voltage with a forward voltage drop around 200 mV, and they also prevent reverse current flow.

Figure 8. Gate cross-coupled rectifier bridge.

The input-output simulation waveforms of the cross-coupled rectifier bridge are shown in Figure 9. The waveforms indicate that when $|V_{IN}|>300$ mV, the rectifier bridge conducts, allowing the output voltage to follow the input voltage. After conduction, the voltage difference between input and output is less than 200 mV. Compared to traditional rectifier bridges, the cross-coupled design offers a lower turn-on voltage and reduced forward voltage drop.

Figure 9. Simulation results of the proposed cross-coupled rectifier bridge.

3.2. Reference Source Circuit

Given that all of the energy for the energy management chip is derived from the PEH, achieving optimal energy efficiency necessitates extremely low power consumption within the chip itself. The reference source, as a fundamental module in the energy management chip, provides the reference voltage and current for other circuit modules, thus determining the static power consumption of the entire chip [31,32,33,34]. The commonly used bandgap reference (BGR) based on BJTs has advantages such as low temperature coefficient, easy compensation, and stable performance. However, BGRs generally have high power consumption, and low-power BGR designs require large resistors and capacitors, which are unfavorable for integrated chip design. In this design, the traditional BJT-based BGR is replaced by a fully CMOS topology reference source. By leveraging sub-threshold transistor technology and the temperature characteristics of transistor threshold voltage, an ultra-low power reference circuit was developed, providing a reference current as low as 10∼20 nA, ensuring the ultra-low static power consumption of the energy management chip.

Figure 10 presents the fully CMOS low-power reference source used in this design [35], comprising a startup circuit, current generation circuit, active load circuit, and trimming circuit. The startup circuit includes transistors $M_{S0}$, $M_{S1}$, $M_{S2}$, and capacitor C. When $VDD$ is powered on, the voltage on C is zero, and the diode-connected transistor $M_{S1}$ charges C. When the voltage on C has not yet risen to $VDD$, transistor $M_{S2}$ injects charge into node $V_N$, initiating the circuit. After initiation, transistor $M_{S0}$ turns on to charge C, accelerating its charging. Once C is charged to $VDD$, the startup circuit shuts off, concluding the startup process. To ensure ample startup time, i.e., sufficient charging time for C, the size of transistor $M_{S1}$ is set to 1 $\mathsf{\mu }$m/10 $\mathsf{\mu }$m.

Figure 10. Fully CMOS low-power reference source [35].

The current generation circuit consists of transistors $M_{P0}$, $M_{P1}$, $M_{N0}$∼$M_{N3}$, and an operational amplifier. Under the negative feedback of the operational amplifier, the drain voltages of transistors $M_{P0}$ and $M_{P1}$ are equal, thus the currents through both transistors are equal, each being $I_R$. Transistor $M_{N3}$ operates in the saturation region, $M_{N2}$ in the linear region, and $M_{N0}$ and $M_{N1}$ in the sub-threshold region. The current–voltage relationship for a transistor in the sub-threshold region is expressed as

$$I_{DS}=I_0{\displaystyle \frac{W}{L}}exp\left({\displaystyle \frac{V_{GS}-V_{TH}}{\eta V_T}}\right)$$

(5)

where $\eta$ is the sub-threshold slope factor, $I_0$ is the reverse saturation current, and $I_0$ = $\mu C_{OX}$$(n-1)V_T^2\propto T^{2-m}$, $\mu$ = ${\mu }_0{(T/T_0)}^{-m}$.

From Equation (5), the source-drain voltage difference $V_{DS2}$ of transistor $M_{N2}$ is

$$V_{DS2}=V_{GS0}-V_{GS1}=\eta V_{T}ln\left({\displaystyle \frac{K_1}{K_0}}\right)$$

(6)

where $K_i={(W/L)}_i$

Transistor $M_{N2}$ operates in the linear region, thus it is equivalent to a resistor $R_{N2}$:

$$R_{N2}={\displaystyle \frac{1}{{\mu }_n{C}_{OX}{K}_2(V_{GS2}-V_{TH})}}$$

(7)

From Equations (6) and (7),

$$I_R={\displaystyle \frac{V_{DS2}}{R_{N2}}}=\eta V_T{\mu }_n{C}_{OX}{K}_2(V_{GS2}-V_{TH})ln({\displaystyle \frac{K_1}{K_0}})$$

(8)

$$\begin{array}{cc}\hfill V_{GS2}& =V_{GS3}+V_{GS0}-V_{GS1}\hfill \\ \hfill & =\sqrt{{\displaystyle \frac{2I_R}{{\mu }_n{C}_{OX}{K}_3}}}+V_{TH}+\eta V_{T}ln({\displaystyle \frac{K_1}{K_0}})\hfill \end{array}$$

(9)

Solving Equations (8) and (9) simultaneously yields

$$I_R=A^2{V}_T^2{\mu }_n{K}_2^{*}\left[{\displaystyle \frac{K_2^{*}+K_3^{*}}{K_3^{*}}}+\sqrt{{\left({\displaystyle \frac{K_2^{*}+K_3^{*}}{K_3^{*}}}\right)}^2-1}\right]\propto T^{2-m}$$

(10)

where $A=\eta ln(K_1/K_0)$ and $K_i^{*}=K_i{C}_{OX}$.

The active load circuit includes transistors $M_{P2}$∼$M_{P5}$, $M_{N4}$∼$M_{N10}$. Transistors $M_{P2}$∼$M_{P5}$ form a current mirror, replicating the current generated by the current generation circuit. Transistors $M_{N4}$∼$M_{N10}$ operate in the sub-threshold region, thus the reference voltage $V_{ref}$ is given by

$$\begin{array}{cc}\hfill V_{ref}& =V_{GS10}+V_{GS8}-V_{GS9}+V_{GS6}-V_{GS7}+V_{GS4}-V_{GS5}\hfill \\ \hfill & =V_{TH}+\eta V_{T}ln\left({\displaystyle \frac{24I_R{K}_5{K}_7{K}_9}{I_0{K}_4{K}_6{K}_8{K}_{10}}}\right)\hfill \\ \hfill & =V_{TH0}-\alpha T+\eta V_{T}ln\left({\displaystyle \frac{24I_R{K}_5{K}_7{K}_9}{I_0{K}_4{K}_6{K}_8{K}_{10}}}\right)\hfill \end{array}$$

(11)

where $V_{TH0}$ represents the transistor’s threshold voltage at 0 K, and $V_{TH}$ varies under different process corners, with $\alpha$ being the temperature coefficient.

Equation (11) shows that by adjusting the sizes of the transistors in the active load circuit, a nearly temperature-independent reference voltage $V_{ref}=V_{TH0}$ can be obtained. However, due to process variations, transistors with the same dimensions can have slight differences in parameters such as $\mu$, $C_{OX}$, and $V_{TH}$, and manufacturing inaccuracies can further affect transistor sizes. Therefore, a trimming circuit is necessary. As shown in Figure 10, by controlling the on/off states of transistors $M_{11}$∼$M_{15}$, the total current through the active load circuit can be adjusted to fine-tune the temperature coefficient of the reference voltage. To minimize power consumption, all transistors in the reference source circuit operate in the sub-threshold region (except for $M_{N2}$ and $M_{N3}$).

3.3. Energy Management Circuit

Wireless sensor nodes often include load modules such as power amplifiers and wireless transmitters, which typically require operating voltages between 2 V and 5 V and consume power in the milliwatt range, significantly higher than the output power of PEHs. Therefore, load modules cannot be directly connected to the storage capacitor; otherwise, they would drain the capacitor quickly and fail to operate properly. This requires the addition of an energy management circuit between the energy storage capacitor and the load module to achieve intermittent load driving. For stable load operation, the energy management circuit must ensure two functions: adequate energy storage in the capacitor to power the load for each operation cycle, and providing a stable voltage to the load.

The dual-threshold management circuit fulfills the first function, and it is used to detect the voltage across the energy storage capacitor and control its charging and discharging process. It has high ($V_H$) and low ($V_L$) thresholds, as shown in Figure 11. When the voltage $V_{RECT}$ on the storage capacitor is below the high threshold $V_H$, switch S remains off, and the capacitor charges. Once $V_{RECT}$ reaches $V_H$, S closes, allowing the capacitor to discharge rapidly. When the voltage $V_{RECT}$ drops to the low threshold $V_L$, S opens again, returning the capacitor to the charging state. Compared to the classic LTC3588-1 dedicated energy harvesting chip, the dual threshold management circuit added in the proposed chip simplifies the circuit structure by setting appropriate high and low threshold voltages based on the energy consumption requirements of the load during operation, converting energy value detection into voltage value detection, and achieving this function under extremely low power consumption conditions. Efficient and reliable energy management can be achieved by controlling the charging and discharging of energy storage capacitors. In this design, the high threshold is set to 4.2 V and the low threshold to 2.2 V. The LDO then stabilizes the voltage, providing a consistent 1.8 V to the load post-discharge.

Figure 11. Working process of the dual-threshold management circuit.

The proposed dual-threshold management circuit, shown in Figure 12, consists of a voltage divider circuit $D_1$, $D_2$, comparators $U_1$, $U_2$, and switching transistors $M_1$, $M_2$, and $M_P$. The voltage divider circuit $D_1$ and $D_2$ generate voltages $V_1$ and $V_2$, respectively, with $V_1<V_2$. The switching transistor $M_P$ is a power transistor with dimensions of 2500 $\mathsf{\mu }$m/1 $\mathsf{\mu }$m, and its gate is controlled by $U_2$, with its source-drain terminals connected to $C_{RECT}$ and the output. The comparators adopt a two-stage structure as shown in Figure 13. The first stage is a differential pair with a current mirror load, converting differential input to single-ended output. The second stage is a common-source amplifier with a current source load, providing large output swing and high gain. This structure is similar to a two-stage operational amplifier, but differs in that the comparator typically uses an open-loop configuration without compensation, resulting in high unity-gain bandwidth and response speed. Given the reference voltage value around 700 mV and the transistor operating voltage, PMOS transistors are chosen for the input pair. To meet power consumption requirements, the comparator’s bias current is provided by the reference source, with each branch current set to 20 nA, totaling 80 nA. The voltage divider circuit is implemented using resistors.

Figure 12. Proposed dual-threshold management circuit.

Figure 13. Proposed two-stage comparator.

Since the storage capacitor’s voltage is not constant and varies over time, a voltage regulation module is required to provide a stable and clean power supply to the load before delivering energy. The regulation module generally includes a switching power supply and an LDO. Compared to switching power supplies, LDOs offer lower output ripple and fewer external components, making them suitable for this system. The LDO circuit is shown in Figure 14, consisting of a folded cascode operational amplifier, a power transistor $M_{PASS}$, and a resistor divider feedback loop. The LDO operates as a negative feedback loop, where the output voltage $V_{out}$ generates a feedback voltage $V_f$ through the resistor divider circuit. The feedback voltage $V_f$ is compared with the reference voltage $V_{ref}$ in the folded cascode operational amplifier. The amplifier’s output controls the gate of the power transistor $M_{PASS}$, thereby regulating the output voltage.

Figure 14. Proposed LDO circuit.

Figure 15 shows the simulation waveform of the proposed energy management circuit. The voltage $V_{RECT}$ is set as a periodic signal, as shown by the red waveform in Figure 15, rising linearly from 2 V to 4.5 V within 0–2 s, and then falling linearly from 4.5 V to 2 V within 2–4 s. When $V_{RECT}$ is below 4.2 V, the voltage $V_1$ generated by the voltage divider circuit $D_1$ is lower than $V_{ref}$, causing comparator $U_1$ to output a low level, turning off the switching transistor $M_1$. The voltage $V_2$ generated by the voltage divider circuit $D_2$ is zero, causing comparator $U_2$ to output a low level, turning off the switching transistor $M_2$ and the power transistor $M_{PASS}$. When $V_{RECT}$ rises above 4.2 V, $V_1$ exceeds $V_{ref}$, causing $U_1$ to output a high level, turning on the switching transistor $M_1$. The $V_2$ also exceeds $V_{ref}$, causing $U_2$ to output a high level, turning on the switching transistor $M_2$ and $M_{PASS}$, and the LDO outputs a voltage of 1.8 V. When $V_{RECT}$ drops below 2.2 V, both $V_1$ and $V_2$ are lower than $V_{ref}$, causing $U_1$ and $U_2$ to output low levels, turning off the switching transistors $M_1$, $M_2$, and the power transistor $M_{PASS}$, resulting in zero LDO output voltage.

Figure 15. Simulation waveform of the proposed energy management circuit.

3.4. System-Level Simulation

The individual circuit modules were integrated into an overall system and simulated using the Cadence Spectre simulation tool. Currently, the parasitic capacitance values of miniaturized PEHs are mostly below 50 nF. Therefore, the parasitic capacitance $C_P$ was set to 20 nF for the simulation. Considering the two-stage vibration structure of the PEH, the first-stage inductive vibrator senses environmental vibrations with a frequency $f_1$ matching the environmental vibration frequency, while the second-stage generating vibrator operates at its natural resonance frequency $f_2$. The equivalent current source characteristics are as analyzed in Section 2. For the simulation, $f_1$ was set to 40 Hz, $f_2$ to 400 Hz, and the peak value of the vibrating current source $I_P$ was set to 300 $\mathsf{\mu }$A. The waveform is shown as the red waveform in Figure 16. In addition to setting PEH parameters, the off-chip storage capacitor $C_{RECT}$ was set to 100 $\mathsf{\mu }$F, and the load resistor $R_L$ was set to 600 Ω.

Figure 16. PEH output characteristics simulation under the FBR interface circuit.

The system’s operational state was simulated and analyzed, including the PEH output characteristics, the voltage $V_{RECT}$ of the storage capacitor, and the load voltage $V_L$. Figure 16 shows the PEH output characteristics simulation waveform under the FBR interface circuit. Figure 17 shows the enlarged view of the simulation waveform in Figure 16, including the equivalent current source $I_P$, the current $I_{RECT}$ flowing into the storage capacitor, and the voltage $V_P$.

Figure 17. Enlarged view of the simulation waveform in Figure 16.

From Figure 16 and Figure 17, it can be observed that when the FBR interface circuit is in operation, a considerable portion of the current generated by the equivalent current source $I_P$ is used for charging and discharging the parasitic capacitance $C_P$ to turn on the rectifier bridge, with only a part of the current flowing into the storage capacitor. As the voltage on the storage capacitor increases, the voltage $V_P$ required to turn on the rectifier bridge also increases, leading to even higher energy losses due to charging and discharging $C_P$. When $I_P$ decays to a sufficiently low level, all its current is used for charging and discharging the parasitic capacitance, with no current flowing into the storage capacitor.

Figure 18 shows the waveforms of the storage capacitor voltage $V_{RECT}$ and the load voltage $V_L$ in the system-level simulation. The $V_{RECT}$ on the storage capacitor starts rising from 0, and when it reaches the high threshold of 4.2 V, the storage capacitor begins to discharge, providing a regulated 1.8 V to the load through the LDO. When the storage capacitor voltage drops to the low threshold of 2.2 V, the storage capacitor stops discharging, and the load voltage drops to 0. The load operates intermittently, with an operation cycle of approximately 5.82 s. From the previous analysis, it is clear that the system can effectively achieve both energy harvesting and power management.

Figure 18. System simulation waveform of the storage capacitor voltage $V_{RECT}$ and load voltage $V_L$.

In addition to analyzing the system’s operational state, it is essential to evaluate the energy extraction power. During normal operation, the peak voltage of the PEH output voltage $V_P$ varies, making it impossible for the FBR interface circuit to determine a maximum power point. Therefore, the energy extraction power $P_{FBR}$ of the FBR interface circuit is represented by the average energy obtained by the storage capacitor between the high and low voltage thresholds,

$$P_{FBR}={\displaystyle \frac{C_{RECT}(V_H^2-V_L^2)}{2\Delta t_1}}\approx 110\mathsf{\mu }W$$

(12)

where $\Delta t_1$ is the load’s intermittent operation period.

From the simulation, the average output power $P_{PEH}$ of the PEH over the period $\Delta t_1$ is

$$P_{PEH}={\displaystyle \frac{\int V_P\ast I_{RECT}}{\Delta t_1}}\approx 119\mathsf{\mu }W$$

(13)

Thus, the energy transmission efficiency of the FBR interface circuit is approximately 92.4%.

4. Measurement Results

The circuit was designed using a 110 nm CMOS process. Figure 19a shows the chip under a microscope, and Figure 19b shows the chip packaged in a QFN32 package, with the packaged chip size being 4 × 4 mm². The size of the piezoelectric energy harvester is much larger than the designed energy harvesting and management chip, so it can only be soldered on a PCB board for testing and cannot be integrated together.

Figure 19. (a) Microscopic view of the chip’s bonding wires. (b) Energy harvesting and management chip in QFN32 package.

The physical image of the piezoelectric vibration energy harvester used in this experiment is shown in Figure 20. It is packaged in an organic glass tube shell with copper foil leading out the electrode. The size of the packaged device is 21.0 × 14.0 × 11.0 mm³. When it is actually applied in wireless monitoring sensing systems, the fixed outer frame required for packaging needs to be removed, and the core structural area is only 17.0 × 8.0 mm². The size and material parameters of the device are shown in Table 1.

Figure 20. Physical picture of piezoelectric vibration energy harvester.

Table 1. Dimensions and material parameters of piezoelectric vibration energy harvester.

Parameter	Symbol	Value
Two-stage vibrator spacing	G	0.8 mm
Base thickness of beryllium bronze sheet	$h_s$	100.0 $\mathsf{\mu }$m
PZT thickness	$h_p$	60.0 $\mathsf{\mu }$m
PZT length	$L_p$	5.0 mm
Low-frequency-induced vibrator length	$L_1$	12.5 mm
High-frequency power generation vibrator length	$L_2$	11.0 mm
Low-frequency-induced vibrator width	$b_1$	8.0 mm
High-frequency power generation vibrator width	$b_2$	4.5 mm
Piezoelectric coupling coefficient	$d_{31}$	−5.0 × 10 m/V
PZT dielectric constant	${\epsilon }_r$	4500
Magnetic residual magnetic	$T_{mag}$	950.0$m_T$
Quality block quality	$m_1$	350.0$m_g$

In this test, the storage capacitor value was 100 $\mathsf{\mu }$F, the load current was set to 3 mA, i.e., the load resistance was 600 Ω, the vibration frequency of the shaker was set to 40 Hz, and the vibration acceleration was set to 4 g. Figure 21a shows the measured waveforms of the storage capacitor voltage $V_{RECT}$ and the load voltage $V_L$. Figure 21b shows an enlarged view of the waveforms in Figure 21a. The measured waveforms indicate that the chip’s operation is consistent with the simulation, demonstrating the ability to perform piezoelectric energy harvesting and power management. The storage capacitor switches between charging and discharging states, with the dual-threshold management circuit effectively detecting voltage changes on the storage capacitor and controlling its discharge. The measured high threshold is approximately 4.4 V, and the low threshold is approximately 2.3 V. The LDO provides a stable output voltage of 1.8 V during the storage capacitor discharge. The load operates intermittently, with an operation cycle of approximately 3 s. Therefore, under the above test conditions, the chip’s energy extraction power is approximately 234 $\mathsf{\mu }$W.

Figure 21. (a) Measured waveforms of the chip. (b) Enlarged view of the measured waveforms.

According to the actual test results, the high and low thresholds of the dual threshold management circuit are slightly different from those in the simulation, and it is speculated that there are two reasons for this. Firstly, there are process errors in actual film production. The voltage divider circuit is composed of multiple identical resistors connected in series. In actual chip fabrication, due to process errors, there may be differences in the resistance values of multiple resistors, resulting in slight differences between the high and low thresholds in actual testing and simulation. Secondly, chip packaging brings parasitic parameters that affect chip operation, resulting in slight differences between high and low thresholds and simulation. Although the high and low thresholds of the dual threshold management circuit differ slightly from those in simulation, the difference is small and within the expected error range, it does not affect the normal operation of the chip.

Table 2 compares the performance of the FBR interface circuit designed in this work with that in other references. It can be seen from the comparison that the FBR interface circuit designed in this work has a higher energy extraction power and lower power consumption.

Table 2. Performance summary and comparison.

Ref.	[36]	[37]	[38]	This Work
Year	2010	2017	2017	2024
Process	0.35 $\mathsf{\mu }$m	0.25 $\mathsf{\mu }$m	0.35 $\mathsf{\mu }$m	0.11 $\mathsf{\mu }$m
Structure	FBR	SSHI	SSHC	FBR
Parasitic Capacitance $C_P$	12 nF	19 nF	45 nF	20 nF
Vibration Frequency	225 Hz	144 Hz	92 Hz	400 Hz
Presence of Maximum Power Point	No	No	No	No
Power Consumption	<2 $\mathsf{\mu }$W	11.5 $\mathsf{\mu }$W	≈1.7 $\mathsf{\mu }$W	<1 $\mathsf{\mu }$W
Energy Extraction Power	32.5 $\mathsf{\mu }$W	136 $\mathsf{\mu }$W	161.8 $\mathsf{\mu }$W	234 $\mathsf{\mu }$W

5. Conclusions

This paper presents the system design of an FBR and energy management circuit, including a rectifier bridge, a fully CMOS reference source, and an energy management circuit. The rectifier bridge employs a PMOS cross-coupled structure to reduce the conduction voltage drop, thereby minimizing energy transmission losses. The traditional BJT-based BGR is abandoned in favor of a fully CMOS topology reference source in this design. Utilizing sub-threshold transistor technology and the temperature characteristics of transistor threshold voltage, an ultra-low power reference circuit is achieved, ensuring ultra-low static power consumption for the energy management chip. The dual-threshold energy management circuit converts energy value detection into voltage detection through the proper setting of high and low thresholds, significantly simplifying the circuit structure and achieving this function under ultra-low power conditions. The circuit is fabricated using a 110 nm CMOS process. Measurement results show that under a vibration frequency of 40 Hz and a vibration acceleration amplitude of 4 g, the chip’s energy extraction power is 234 $\mathsf{\mu }$W, and the load operates every 3 s with a stable power supply voltage of 1.8 V during operation. Therefore, this FBR interface circuit can effectively extract electrical energy from the PEH output.