A Low-Power BL Path Design for NAND Flash Based on an Existing NAND Interface
Round 1
Reviewer 1 Report
Comments and Suggestions for AuthorsThe authors proposed low-power BL path design for NAND Flash by exploiting VDDQ for the BL precharging sequence. The idea may be effective in terms of power consumption reduction, but there are some points to be clearly addressed.
1. In the sensing circuit of NAND Flash, controlling the coupling between the neighboring BLs or neighboring SNs plays crucial role for the accurate sensing of BL current and SN voltage. To stabilize the BL and SN voltage, considerable latency is required which may critically affect the total read time of NAND Flash.
In this paper, authors showed simulation and experimental result with SN voltage changing scheme from 1.2V to 2V just before turning on the SNS, with ignorable 100ns delay increase consequently. Because the authors are presenting the sensing scheme with suddenly changing SN voltage at the sensing operation, the whole sensing circuit must be accurately modeled and designed. However, as shown in Fig. 10, it seems BL and SN capacitance models are just connected with ground node, not with neighboring nodes. And I guess the mimicking BLs at the designed chip may have same configuration. Can it be simply modeled like this? Clear explanation or the correction is required.
2. At the beginning of the section 5.1 and Table 2, “C” should be changed to “BL capacitance” or “CBL” to deliver the clear meaning to the readers.
Comments for author File: 
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Author Response
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Reviewer 2 Report
Comments and Suggestions for AuthorsSee the attached file.
Comments for author File: Comments.pdf
The English Language should to be improved in some parts of the paper.
Author Response
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Author Response File: Author Response.pdf
Round 2
Reviewer 1 Report
Comments and Suggestions for AuthorsI would agree this paper to be accepted as present form.
