# A 1.1 V 25 ppm/°C Relaxation Oscillator with 0.045%/V Line Sensitivity for Low Power Applications

^{*}

## Abstract

**:**

## 1. Introduction

## 2. Review of Reported Relaxation Oscillator

_{REF_H}and V

_{REF_L}) in the reported work. V

_{REF_H}is connected to the non-inverting input of the comparator, and the voltage (V

_{osc}) across the capacitor is initially zero. The capacitor (C

_{osc}) is first charged by I

_{REF}until V

_{osc}reaches V

_{REF_H}. Then C

_{osc}starts to discharge with constant current I

_{REF}while V

_{REF_L}is connected to the comparator. When V

_{osc}is lower than V

_{REF_L}, C

_{osc}is charged, and V

_{osc}is again compared with V

_{REF_H}. The delay generation units prevent the oscillator from entering metastability.

_{0}in the reference generator needs to work in a saturation region, thus, for reliable temperature compensation, the current flowing through it is not allowed to be reduced to a small value. At this juncture, an operational amplifier is also utilized to provide a high loop gain to minimize the circuit sensitivity with respect to the supply variation. This suggests an additional current consumption source. Therefore, high current consumption becomes the main limitation of this circuit technique.

_{2}flows though resistor R to generate the reference voltage at the non-inverting input of the comparator, and capacitor C

_{1}is charged by constant current I

_{1}. After the voltage across C

_{1}becomes bigger than the reference voltage, ϕ transits to logic high; thus, the capacitor C

_{2}begins to be charged, and the reference voltage is connected to the inverting input of the comparator until the charging operation for C

_{2}is completed to make ϕ logic low again.

_{1}and I

_{2}can be reused at different phases, and only one comparator [22] is needed. All the currents, including the bias current for the comparator, can be achieved from one current source, hence the current consumption is minimized. Because the reference voltage is connected to different inputs of the comparator at different phases, the offset of the comparator increases the period at one phase, while decreasing the period at another phase. Thus, the offset can be cancelled out as long as the two capacitors are identical and the two charging currents are assumed the same. However, because of the restricted drain-to-source voltage headroom for each transistor working in a low supply environment, the transistor is subject to more stressing, resulting in not having good matching characteristics. On top of that, the mismatch effect between I

_{1}and I

_{2}is unavoidable. The current mismatch leads to the residual offset of the comparator that cannot be cancelled out completely. Ultimately, an error in the reference voltage exists between the different phases.

_{r}) across the composite resistors and the voltage (V

_{c}) across the capacitor. Initially, V

_{c}, V

_{cmp}, and V

_{rst}are logic low, and the capacitor is charged by constant current I

_{r}until V

_{c}becomes larger than V

_{r}to change V

_{cmp}from low to high, which causes V

_{rst}to transition to high to discharge the capacitor. After the discharge action has been completed, V

_{cmp}and V

_{rst}become low to allow the current I

_{r}to charge the capacitor again.

_{c}and I

_{r}is independent of temperature and supply variations, and the temperature effect on the metal-oxide-metal (MoM) capacitor is negligible. In addition, the offset voltage in transistors M

_{0}and M

_{1}can be cancelled out by flipping M

_{0}and M

_{1}at every half cycle. Therefore, a good T.C. and good line sensitivity of the output frequency can be obtained due to good thermal stability through the use of a stable composite resistor and capacitor, in conjunction with offset cancellation using the chopping technique. However, it may be difficult to reduce the current consumption due to the operational amplifier which exhibits good transient response for powering the fast-switching clock buffers and the need for a complicated replica-biasing circuit. Hence, this design also suffers from the problem of relatively high supply current consumption.

## 3. Proposed Relaxation Oscillator

#### 3.1. Topology of the Relaxation Oscillator

_{REF}, while the lower supply current consumption is further addressed in the proposed work. The oscillator comprises a reference generator, two comparators (Comp. 1 and Comp. 2), an S-R latch, four switches, and two capacitors (C

_{1}and C

_{2}). The reference generator generates a stable reference voltage (V

_{REF}) and a reference current (I

_{REF}), charging two capacitors with a constant current.

_{1}is charged by I

_{REF}. After the voltage (V

_{C}

_{1}) across C

_{1}reaches V

_{REF}, the output of Comp.1 transits to high, which allows Q to become high and Q_bar to become low. Then C

_{1}starts to discharge, while C

_{2}is charged by I

_{REF}. The inputs of the SR latch are both low when I

_{REF}is charging C

_{2}, so that the outputs of the SR latch remain constant until the voltage (V

_{C}

_{2}) rises to V

_{REF}. At this juncture, Q transits to low, while Q_bar transits to high, allowing C

_{1}to be charged again and C

_{2}to discharge. The output Q of the SR latch will generate a rail-to-rail square wave with the desired frequency. As capacitors are charged by a constant current, the duration of the high level and low level of the square wave are dependent on the charging time of each capacitor; hence, the 50% duty cycle can be achieved by using two identical capacitors. The output frequency can be expressed as

_{ROSC}is the output frequency, and C is the capacitance of C

_{1}and C

_{2}. From (1), the accuracy of the output frequency is dependent on the accuracy of V

_{REF}and I

_{REF}. From the design considerations, the reference generator and the comparator are the key components in circuit design. Two nonideal effects exist in the relaxation oscillator circuit. They are the delay and offset of the comparator. Regarding the comparator’s delay, it is not critical because of the low frequency specification and the moderate precision requirement in its application. With a careful designing of the comparator, the temperature-dependent delay of the comparator can be minimized to cause less impact to the circuit, and ultimately, on the output frequency. Pertaining to the comparator’s offset, it is also addressed in the design phase with an appropriate choice of critical device sizes so that the offset effect to the circuit is acceptable, without significantly jeopardizing the oscillator’s performance.

#### 3.2. Reference Generator

_{REF}) and the reference current (I

_{REF}), is depicted in Figure 6. The reference voltage generator is based on the two-transistor topology [25] and the cascode current mirror. This is achieved by employing voltage-to-current and current-to-voltage conversions to produce V

_{REF}

_{.}This is then followed by another voltage-to-current converter with a composite resistor [26] and V

_{REF}to generate the reference current I

_{REF}.

_{1}, M

_{2}, M

_{3}, and M

_{4}work in the weak inversion region, where M

_{1}and M

_{3}are identically designed native transistors with a negative threshold voltage, whereas M

_{2}and M

_{4}are identical standard transistors. It is given that, for a sub-threshold biased MOSFET, its drain current is

_{ox}is the gate-oxide capacitance, η is the subthreshold slope factor, V

_{T}is the thermal voltage, W is transistor’s channel width, L is transistor’s channel length, V

_{GS}is the gate-to-source voltage, V

_{TH}is the threshold voltage, and V

_{DS}is the drain-to-source voltage. When V

_{DS}is larger than 100 mV (4 V

_{T}), the effect of V

_{DS}on I

_{sub}is negligible; hence, the current I

_{sub}can be approximated as

_{1}and M

_{2}are the same, we can obtain

_{1}and M

_{2}is the same as that of M

_{3}and M

_{4}due to the identical current copying action in the cascode current mirror M

_{5}–M

_{8}. Hence, the V

_{GS}of M

_{2}is identical to that of M

_{4}, which is the V

_{REF}. When the gates of M

_{1}and M

_{3}are connected to a ground, it suggests that the V

_{GS}of M

_{1}and M

_{3}are identical negative reference voltages. Thus, V

_{REF}can be obtained as

_{TH}is given as [7]

_{TH}

_{0}is the threshold voltage at room temperature (300 K), and $\kappa $ is the temperature coefficient of the threshold voltage. Therefore, the T.C. of V

_{REF}is as follows:

_{1}and M

_{2}, while M

_{3}and M

_{4}remain the same size as M

_{1}and M

_{2}, respectively, the temperature compensation can be achieved to permit V

_{REF}in the first-order temperature compensation. Finally, it yields

_{REF}has a good power supply rejection (PSR) at low frequency. Since the effect of ΔV

_{DD}on the flowing currents, M

_{2}and M

_{4}are negligible, as long as their V

_{DS}values are larger than 100mV, while the transistors have a long channel length to reduce the drain-induced barrier lowering (DIBL) effect on V

_{TH}

_{1}~V

_{TH}

_{4}. Besides, the negative feedback formed by M

_{3}, M

_{4}, and M

_{9}can further stabilize V

_{REF}.

_{REF}driving a temperature-compensated composite resistor (R

_{s}). Of particular note, R

_{s}comprises the series connection of an n-poly resistor (R

_{n}) and a p-poly resistor (R

_{p}), where R

_{n}is PTAT and R

_{p}is CTAT. The T.C. of R

_{p}, R

_{n}, and R

_{s}are given as follows:

_{Rs}can be rewritten as

_{Rp}is negative and TC

_{Rn}is positive. Thus, TC

_{Rs}can be made zero when choosing R

_{p}/R

_{n}equal to |TC

_{n}/TC

_{p}|. This indicates that R

_{s}can be independent of the first-order temperature effect. Therefore, the temperature-insensitive reference current (I

_{REF}) can be obtained with the temperature-insensitive voltage and the composite resistor.

_{s}is independent of V

_{DD}, V

_{REF}is insensitive to the change in V

_{DD}. As a result, I

_{REF}is also insensitive to the supply variations.

_{1}is used as a frequency compensation for the negative feedback loop which is formed by M

_{3}, M

_{4}, and M

_{9}. In addition, the capacitor C

_{2}is used to stabilize V

_{REF}when the switches in Figure 4 are turned on and off. This is because the voltage change will be coupled to the gate of M

_{9}by the parasitic capacitors. The current mirror pairs M

_{5}–M

_{8}and M

_{10}–M

_{13}have a long channel length to reduce the current mismatch.

_{DS}headroom for the current mirror pair in Figure 6 at the SS corner under a low temperature, due to the increase in V

_{TH}.

#### 3.3. Comparator

_{3}–M

_{6}and M

_{13}–M

_{16}, is used to produce gain enhancement as well as to reduce the delay in the comparator, the outputs of which are followed by the current mirror high-gain stage consisting of M

_{7}–M

_{12}and M

_{15}–M

_{20}. Finally, the CMOS inverter, formed by M

_{23}and M

_{24}, aims to sharpen the output square waveform and provide the driving capability of the comparator.

_{3}–M

_{6}, the aspect ratio of M

_{3}is larger than that of M

_{5}. In small-signal analysis, the output impedance is obtained as

_{mi}is the respective transistor’s transconductance and r

_{Oi}is the respective transistor’s output resistance, with i = 3 or 5. From (14), R

_{O1}is increased from 1/g

_{m}

_{3}to 1/(g

_{m}

_{3}–g

_{m}

_{5}) to increase the voltage gain because of the positive feedback allowing M

_{5}to behave as a negative resistance. When there is a voltage change on the drain of M

_{3}, the positive feedback introduced by M

_{5}can accelerate this change, causing faster output response to reduce the delay in the comparator.

_{17}–M

_{20}are used to reduce the effect of supply variation ΔV

_{DD}on the delay in the comparator. For M

_{7}and M

_{17}in small-signal analysis, the change in V

_{DS}

_{7}caused by ΔV

_{DD}can be approximated as [27]

_{DS}on M

_{7}–M

_{10}can be ignored when V

_{DD}varies. This means the current change in each branch caused by channel length modulation and DIBL can be minimized with cascode transistors. Moreover, the bias current for the comparator is directly copied from I

_{REF}, with the cascode current mirror in different ratios. This avoids the need for an extra bias branch, which would cause an increase in supply current consumption.

_{GS}of the MOS transistor working under weak inversion is expressed as

_{GS}exhibits CTAT behavior. M

_{3}is in the diode connection, meaning that V

_{DS}

_{3}is equal to V

_{GS}

_{3}. When the temperature increases, V

_{DS}

_{3}(or V

_{GS}

_{3}) in the diode-connected topology is significantly reduced with respect to V

_{DS}

_{7}. Thus, the mismatch between the drain-to-source voltage of the transistors can lead to a rising current to allow for the delay in the comparator to decrease from 285.3 ns to 278.8 ns as the temperature increases, as shown in Figure 8. This feature is particularly useful for the delay compensation arising from the observation of the increase in delay through the leakage current of the switches, as depicted in Figure 4. As a result, the thermal stability of the oscillator circuit is enhanced. This will be further discussed in the next subsection. Of particularly note, the leakage current in the advanced technology node can be a serious issue.

_{min}). Although the parasitic capacitors in the large-size transistors will enlarge the response time, the delay, which is around 0.28 µs, including the hysteresis, contributes 3.6% of the oscillation period. Therefore, it is considered acceptable, with a low output frequency and a moderate precision requirement. Based on the result, the comparator offset cancellation scheme is not implemented in this work. The sizes of each component pertaining to the comparator in Figure 6 are given in Table 2.

#### 3.4. Leakage Current in Switches and Delay Compensation

_{REF}is quite small, the leakage currents in the advanced technology node, flowing through the switch transistors, can be significant when charging C

_{1}and C

_{2}. With the increase in temperature, the delay caused by the transistor switches is increased from 1.9 ns to 9.8 ns, as shown in Figure 11, and this effect is particularly pronounced. Therefore, this will cause the reduction in the output frequency. Thus, according to the reverse short-channel effect, high threshold-voltage transistors with the smallest channel length can be used as switches. This is also in conjunction with introducing the body effect in pmos to maximize the threshold voltage. Finally, the leakage current effect can be reduced by introducing the CTAT delay, as discussed in Section 3.3, such that the output frequency can be kept constant. The size of each transistor and capacitor shown in Figure 10 are given in Table 3.

## 4. Results and Discussions

_{DD}= 1.1 V under room temperature, and the transient simulation result of the output signal is depicted in Figure 12. All analog-biased transistors in the proposed ROSC work in the subthreshold region, the bias current of the comparators can be made small for low frequency design, and the current derives from the dedicated I

_{REF}instead of from the addition of an extra current source. This permits the current consumption of 552 nA at room temperature in a typical corner. However, there is always a performance tradeoff between I

_{REF}and low current consumption.

_{DS}. Therefore, the proposed ROSC can still work properly when the supply is slightly lower than 1.1 V. Considering the operation margin, 1.1 V is regarded as the minimum supply voltage for the oscillator. Regarding the low T.C. values achieved by the ROSC with respect to those of prior-art works, the T.C. improvement is attributed to the compensation for the delay drift resulting from temperature, as seen in Figure 8 and Figure 11. By calculation, without the delay compensation, this T.C. will increase to about 19.1 ppm/°C.

^{2}, or 153 µm × 153 µm.

_{REF}with good PSR at low frequency and the cascode transistors shielding the variation of supply in the comparators to stabilize the response time.

_{1}and C

_{2}in Figure 10. The process variation displays the moderate value, which is targeted for moderate precision applications. However, to cater to a precision design, this can be achieved by trimming the passive MoM capacitors C

_{1}and C

_{2}, which are less affected by temperature.

## 5. Conclusions

## Author Contributions

## Funding

## Data Availability Statement

## Conflicts of Interest

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**Figure 1.**Tradeoff performance of reported relaxation oscillators: (

**a**) T.C. versus power; (

**b**) line sensitivity versus power.

**Figure 2.**A CMOS relaxation oscillator with a merged window comparator: (

**a**) reference generator; (

**b**) block diagram.

**Figure 4.**A self-chopped relaxation oscillator with adaptive supply generation: (

**a**) block diagram; (

**b**) clock buffer.

**Figure 13.**Temperature characteristic of output frequency at different process corners under the 1.1 V supply: (

**a**) @TT corner; (

**b**) @SS corner; (

**c**) @FF corner.

**Figure 14.**Temperature characteristic of output frequency at different process corners under the 1 V supply: (

**a**) @TT corner; (

**b**) @SS corner; (

**c**) @FF corner.

**Figure 15.**Temperature characteristic of output frequency with simulated parasitic capacitors at the TT corner.

**Figure 17.**Supply dependence of output frequency at different process corners: (

**a**) @TT corner; (

**b**) @SS corner; (

**c**) @FF corner.

Component | Size | Component | Size |
---|---|---|---|

M_{1,3} | 10/15 (µm/µm) | M_{10,12} | 28/12 (µm/µm) |

M_{2} | 2.04/1 (µm/µm) | M_{11,13} | 7/2 (µm/µm) |

M_{4} | 2.05/1 (µm/µm) | R_{1} | 433.3 kΩ |

M_{5,7} | 5/4 (µm/µm) | R_{2} | 1.366 MΩ |

M_{6,8} | 6/2 (µm/µm) | C_{1} | 1.5 pF |

M_{9} | 1.5/1 (µm/µm) | C_{2} | 4 pF |

Component | Size | Component | Size |
---|---|---|---|

M_{1,2} | 1/0.6 (µm/µm) | M_{15,16} | 0.5/0.6 (µm/µm) |

M_{3,4} | 1/1.2 (µm/µm) | M_{17,18} | 0.3/0.3 (µm/µm) |

M_{5,6} | 0.8/1.2 (µm/µm) | M_{19,20} | 0.3/0.3 (µm/µm) |

M_{7,8} | 0.5/0.6 (µm/µm) | M_{21} | 20/12 (µm/µm) |

M_{9,10} | 0.5/0.6 (µm/µm) | M_{22} | 5/2 (µm/µm) |

M_{11,12} | 1/1.2 (µm/µm) | M_{23} | 0.36/0.12 (µm/µm) |

M_{13,14} | 1.2/1.2 (µm/µm) | M_{24} | 0.12/0.12 (µm/µm) |

**Table 3.**Size of components in Figure 10.

Component | Size | Component | Size |
---|---|---|---|

M_{1,2} | 0.12/0.04 (µm/µm) | C_{1,2} | 1.49 pF |

M_{3,4} | 0.36/0.04 (µm/µm) |

Parameter | [7] 2016 | [8] 2017 | [9] 2020 | [10] 2012 | [19] 2017 | [20] 2013 | This Work |
---|---|---|---|---|---|---|---|

Technology | 65 nm | 65 nm | 40 nm | 60 nm | 65 nm | 65 nm | 40 nm |

Frequency (kHz) | 64.4 | 64.2 | 32.7 | 32.7 | 32.5 | 18.5 | 64.6 |

Supply Voltage (V) | 1.2 | 1.2 | 0.6 | 1.6 | 1.2 | 1 | 1.1 |

Current_TT (μA) | 3.6 | 7.47 | 0.067 | 2.8 | 0.225 | 0.12 | 0.55 |

T.C._TT (ppm/°C) | 144 | 14.7 | 21.7 | 32.4 | 138 | 22 | 12.4 |

T.C._MC (ppm/°C) | NA | NA | 35.5 | NA | NA | NA | 25 |

Temp. Range (°C) | −20–100 | −20–100 | −40–125 | −20–100 | −40–80 | 0–90 | −20–80 |

Line Sens. (%/V) | 0.91 | 0.188 | 0.5 | 0.125 | 1.39 | 1 | 0.045 |

Process Sen. (σ/µ)% without trimming | 3.66 | NA | 11.73 | NA | 10.4 | NA | 9.86 |

FoM (%) | 1.549 | 0.169 | 0.247 | 0.344 | 1.54 | 0.32 | 0.129 |

Result | Simulated | Simulated | Simulated | Measured | Simulated | Measured | Simulated |

**Table 5.**Performance comparison with previously reported ROSC works employing technology nodes with longer channel length.

Parameter | [1] 2013 | [23] 2010 | [28] 2014 | [29] 2007 | This Work |
---|---|---|---|---|---|

Technology | 180 nm | 350 nm | 180 nm | 350 nm | 40 nm |

Frequency (kHz) | 32.55 | 3.3 | 28 | 80 | 64.6 |

Supply Voltage (V) | 1 | 1 | 1.2 | 1 | 1.1 |

Current_TT (μA) | 0.47 | 0.066 | 0.033 | 1.06 | 0.55 |

T.C._TT (ppm/°C) | 120 | 260 | 95.5 | 842 | 12.4 |

T.C._MC (ppm/°C) | NA | NA | NA | NA | 25 |

Temp. Range (°C) | −40–100 | −20–80 | −20–80 | 0–80 | −20–80 |

Line Sens. (%/V) | 1.1 | 3.5 | 3 | 2.5 | 0.045 |

Process Sen. (σ/µ)% without trimming | 1.39 | NA | NA | 3.95 | 9.86 |

FoM (%) | 1.31 | 2.95 | 1.255 | 8.67 | 0.129 |

Result | Measured | Measured | Measured | Simulated | Simulated |

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## Share and Cite

**MDPI and ACS Style**

Liao, Y.; Chan, P.K.
A 1.1 V 25 ppm/°C Relaxation Oscillator with 0.045%/V Line Sensitivity for Low Power Applications. *J. Low Power Electron. Appl.* **2023**, *13*, 15.
https://doi.org/10.3390/jlpea13010015

**AMA Style**

Liao Y, Chan PK.
A 1.1 V 25 ppm/°C Relaxation Oscillator with 0.045%/V Line Sensitivity for Low Power Applications. *Journal of Low Power Electronics and Applications*. 2023; 13(1):15.
https://doi.org/10.3390/jlpea13010015

**Chicago/Turabian Style**

Liao, Yizhuo, and Pak Kwong Chan.
2023. "A 1.1 V 25 ppm/°C Relaxation Oscillator with 0.045%/V Line Sensitivity for Low Power Applications" *Journal of Low Power Electronics and Applications* 13, no. 1: 15.
https://doi.org/10.3390/jlpea13010015