Next Article in Journal
Computer Engineering Education Experiences with RISC-V Architectures—From Computer Architecture to Microcontrollers
Previous Article in Journal
A Subthreshold Layout Strategy for Faster and Lower Energy Complex Digital Circuits
 
 
Font Type:
Arial Georgia Verdana
Font Size:
Aa Aa Aa
Line Spacing:
Column Width:
Background:
Review

Review on the Basic Circuit Elements and Memristor Interpretation: Analysis, Technology and Applications

1
ImViA, Université de Bourgogne, 21078 Dijon, France
2
ELE-FAENG, Kano University of Science and Technology, Kano 3244, Nigeria
*
Author to whom correspondence should be addressed.
J. Low Power Electron. Appl. 2022, 12(3), 44; https://doi.org/10.3390/jlpea12030044
Submission received: 16 March 2022 / Revised: 23 May 2022 / Accepted: 11 July 2022 / Published: 3 August 2022

Abstract

:
Circuit or electronic components are useful elements allowing the realization of different circuit functionalities. The resistor, capacitor and inductor represent the three commonly known basic passive circuit elements owing to their fundamental nature relating them to the four circuit variables, namely voltage, magnetic flux, current and electric charge. The memory resistor (or memristor) was claimed to be the fourth basic passive circuit element, complementing the resistor, capacitor and inductor. This paper presents a review on the four basic passive circuit elements. After a brief recall on the first three known basic passive circuit elements, a thorough description of the memristor follows. Memristor sparks interest in the scientific community due to its interesting features, for example nano-scalability, memory capability, conductance modulation, connection flexibility and compatibility with CMOS technology, etc. These features among many others are currently in high demand on an industrial scale. For this reason, thousands of memristor-based applications are reported. Hence, the paper presents an in-depth overview of the philosophical argumentations of memristor, technologies and applications.

1. Introduction

Electronic engineering plays a crucial role in modern civilization in both the analogue and digital domains. This was made possible by the contribution of the circuit elements that are commonly called electronic components. Figure 1 shows some examples of electronic components. Depending on their interactions with the other parts of the circuit, electronic components are often placed into two categories, namely, active and passive circuit elements. Active circuit elements are capable of generating electrical energy or power gain to the other parts of the circuit which include for example, transistors, operational amplifiers, integrated circuits, voltage and current sources, etc. Passive circuit elements can only use or dissipate the available power sources, for example resistor, capacitor, inductor, thermistor, light-dependent resistor (LDR), etc. In general, active circuit elements are capable of generating electrical power while passive circuit elements can only store, use or deny the generated power. Additionally, a transistor is an active device owing to its ability to generate power gain. These circuit elements altogether form electronic components (see Figure 1) that have been a major bedrock for modern civilization owing to their tremendous contribution in the advancement of electronic industries. The three branches in Figure 1, illustrate the generalized evolution of the electronic components accordingly. The first, second and third branches give, respectively, the fundamental circuit elements, semiconductor devices and many other components designed to achieve various circuit functionalities.
The transistor has been the leading component in electronic gadgets due to its reliable capabilities in switching, amplification and micro-scalability. The performances of an electronic device are improved by incorporating smaller and faster circuit components. This approach serves many purposes, for example portability and improved power consumption because fewer components are involved. However, transistor scaling is challenging as they are presently few nano-meters in size, hence the need for an alternative to transistors for future electronic systems design. Scalability of electronic components becomes an important factor in order to meet the increasing demand of reliable digital electronic systems. Currently, nano-scalability is one of the main challenges in the nanoelectronics industries [1], especially due to the high demand of faster and more reliable systems (small, medium and large scales). For seven decades, transistors have been the leading component contributing to the exponential advancement in electronic systems and designs [2]. However, modern transistors suffer from nano-scalability issues owing to their infinitesimal dimensions [3]. The performance of devices and systems improves with the reduction in the size of their constitutive circuitries [4] and often brings forth advantages such as reliability, lower power consumption, speed, cheapness, portability, etc., thanks to memristor nano-scalability.
The memristor is a two-terminal nonlinear dynamic electronic device and is typically a passive nano-device whose conductivity is controlled by the time-integral of the applied voltage (also known as flux) across it or the time-integral of the current (also known as charge) flowing through it. This new component was first envisioned by circuit theorist Leon Chua in 1971 and it is proclaimed to be the fourth basic passive circuit element (alongside the resistor, capacitor and inductor) having interesting features that make it suitable for various applications. For example: high-density memory applications, bio-electronics or bio-inspired applications, storage and processing of big data, and image recognition and processing. It is impossible to completely discard the transistor due to the emergence of the memristor because it is an active device while the memristor is a passive one. However, using both of them in a circuit will tremendously improve its performance, because one memristor can replace multiple transistors.
Memristive behaviour has been observed experimentally for two centuries but remained unidentified because no one had ever thought of the contingency of the fourth basic circuit element in electronics. The first human-made memristor dated in 1801 by English chemist Humphry Davy [5], in which the fingerprint of a memristor manifested experimentally with a carbon arc discharge lamp (incandescent light) and was considered as the first artificial electric light source. Some devices and systems were shown to possess the now well-known signature of a memristive device (pinched hysteresis loop) owing to their inholding inertia [6] which occurs from the movement of mobile ions or oxygen vacancies, the formation and splitting of conductive filaments and phase-change transition of some materials for data storage, e.g., sputtered Ge 2 Sb 2 Te 5 films [7,8]. This inertia causes latency in the system mechanism, resulting in the exhibition of its memory effects. Contemporarily, the memory effect is also seen in nano devices [9] in which the dynamics of electrons and ions depend on the previous history of the device.
Leon Chua [10] observed from symmetrical argument of the circuit elements (shown in Figure 2) that for the sake of completeness there should be a fourth passive circuit element in addition to the conventional resistor, capacitor and inductor. He theorized the existence of the memristor and its electromagnetic interpretation. However, the memristor differs from the three other passive circuit elements in the sense that it is a nonlinear element and capable of storing information. As clearly presented in [10], some theories were established supporting the existence of the fourth basic circuit element, its electromagnetic interpretation and some promising applications. Few years later, Chua and Kang [11] elaborated a broader class of nonlinear systems called the memristive systems, as discussed in Section 3.
Although the principle theories of memristor exist [10], its realization remained a mystery for nearly four decades. Then in 2008 [12], a team of researchers from the Hewlett Packard (HP) laboratory led by Stanley Williams published a paper in Nature Journal announcing their successful realization of a two-terminal solid-state device bearing the characteristics of the memristor described by L. Chua in 1971 [10]. This discovery, which is described as accidental while working on nano crossbar grid [3], paved the way for more awareness that continued to attract the global attention of many researchers, engineers and scientists, therefore exploring more possible features of the memristor in terms of applications and technologies. Some memristor technologies include the Redox reaction, Ferro-electricity, Organic chemistry, etc., and will be discussed in Section 4. The conventional resistance to the flow of charges through a conducting material or wire is often analogously described to flowing water through a pipe of uniform cross-sectional area. The analogy of memristance with respect to the flowing charge is seen in flowing water through a pipe having a variable diameter [13,14]. The volume of water flowing through the pipe increases with increasing of the pipe’s diameter, hence the water encounters a lower resistance path, while it decreases with decreasing of the pipe’s diameter, hence encountering a higher resistance path.
The memristor is seen as the most promising element, not only capable of replacing transistors for some applications, but also to revolutionize electronic industries virtually in every facet of electronic systems, design and applications [3]. Hence, memristor becomes a suitable component for nanotechnology. The most common properties that make memristor a good candidate for future technologies are: Nano-scalability, Memory capabilities, Conductance modulation and Nonlinearities whose contemporary demand is at its peak. For example, transistors suffer nano-scalability limitations due to their finite dimensions while it would be required that they can be of infinitesimal dimensions. Therefore, they cannot effectively undergo any further reduction in size as they are presently a few nano-meters [15]. As stated by Gordon Moore, co-founder of Intel corporation, “The number of transistors incorporated in a chip should approximately double every 24 months”and hence is called Moore’s Law. This law holds only if the sizes of chips associated with circuitries keep reducing, otherwise the law will cease to be true. Transistors are tiny electrical switches, forming the fundamental unit that drives all electronic gadgets. As the transistors become smaller, they also become faster and require less electricity to operate. Clearly, there will be a limit when transistors cannot undergo any further reduction in size, which seems to be different with memristor nano-scalability.
However, the memristor discovery in [12] is still under criticism as some researchers are not convinced about the memristor [16,17]. The researchers in [18], tried to prove that the real memristor stated in [10] is not identifiable and even an impossibility. Intuitively, the three known basic passive circuit elements (resistor R, inductor L and capacitor C) are unquestionably independent of one another and they are in existence naturally, hence referred to as the fundamental circuit elements. However, on the other hand, the claim for memristor as the fourth fundamental circuit element is challenging owing to its one-to-one resistor dependencies [19]. Namely, it bears the exact same unit of measurement as the ohm Ω and a deductive-like expression, as:
M = V i = d ϕ d t d q d t = d ϕ d q = M ( q ) ,
it very much resembles a resistor, hence memristor is the portmanteau of memory resistor. Here M ( q ) is the memristance and it is expressed in ohms ( Ω ) as is a resistor.
Notwithstanding, the fact that a memristor cannot be realized by any simple combination of the three basic circuit elements (R, L and C) proves that the memristor is actually a fundamental circuit element [3]. Although its position as the fourth fundamental passive circuit element is challenging [18,19], the memristor bears a massive technological impact and it appears to be a good candidate for numerous designs and applications. Moreover, since its inception in 2008, thousands of publications were published on memristor technologies and applications (too many to be cited) and in doing so, they affirmed memristor as the fourth basic circuit element. The number of memristor publications grows exponentially, hence outweighing the few criticisms.
This study is organized as follows. Section 2 presents briefly the three known basic passive circuit elements and is then followed by the memristor argumentation as the fourth basic passive circuit element and its description by mode of excitation. Section 3 presents memristor insights and its strong philosophical criticism, especially when it is referred to as the fourth basic passive circuit element. Section 4 introduces the memristor technologies and a thorough description and analysis of TiO 2 memristor. Section 5 presents analog and SPICE models of the memristor useful for demonstrations and simulation of memristor-based applications. Section 6 presents the modeling of memristor as a function of the flowing charge through it. Section 7 presents some interesting application areas of the memristor. Finally, the results and the contents of this paper are discussed in Section 8.

2. The Basic Passive Circuit Elements and Memristor Argumentation

This section presents briefly the three familiar fundamental passive circuit elements, namely resistor R, inductor L and capacitor C and is then followed by the memristor argumentation as the fourth fundamental passive circuit element. The voltage V and current i sources are the basic active circuit elements in the form of dependent or independent sources. We first recognize the relationship between electric voltage V and magnetic flux ϕ , as typically known from Faraday’s law, as:
V ( t ) = d ϕ ( t ) d t or equivalently : ϕ ( t ) = t V ( τ ) d ( τ ) ,
that is,
ϕ ( t ) = 0 t V ( τ ) d ( τ ) + ϕ 0 ,
where ϕ 0 = 0 V ( τ ) d τ , is the initial flux at time t = 0 and may be zero or nonzero. Similarly, the relationship between electric current i and electric charge q is conventionally known as;
i ( t ) = d q ( t ) d t or equivalently : q ( t ) = t i ( τ ) d ( τ )
q ( t ) = 0 t i ( τ ) d ( τ ) + q 0 ,
where q 0 = 0 i ( τ ) d τ is the initial charge at time t = 0 and may be zero or nonzero. Hence, these four variables, namely voltage V, current i, magnetic flux ϕ and electric charge q are called the fundamental circuit variables. Each pair of these four circuit variables are interrelated by the basic passive circuit elements via a constitutive relationship of the form f ^ ( m , n ) = 0 characterizing the port equations of their circuit functionality, where n and m are any of V, i, ϕ or q circuit variables.
Figure 2 illustrates the symmetry argument of the four basic circuit elements with respect to the four circuit variables. In the case of resistor R, it can be seen that m and n are voltage and current, respectively, and is given by the constitutive relationship d V = R d i . Similarly, the constitutive relationships of capacitor C and inductor L are d q = C d V and d ϕ = L d i , respectively. However, there is a possible missing relationship between magnetic flux ϕ and electric charge q.
In 1971, Leon Chua proposed that for the sake of completeness there must be a fourth fundamental passive circuit element which gives the missing relationship between ϕ and q, thus having a constitutive relationship: f ^ ( ϕ , q ) = 0 or equivalently as d ϕ = M d q , where M is the Memristor, a portmanteau of ‘memory’and ‘resistor’. The naming of the fourth basic passive circuit element as memristor (memory resistor) portrays that it has the property of resistance with memory. This fact arises due to the peculiar nature of memristor to remember the history (memory effect) of its previous state (resistance), even after the power is disconnected and restarted from this previous state after the power is reconnected, irrespective of the duration upon which the power is ON or OFF (i.e., it could be a day, a month or years) [3]. This special property suggests the memristor as a promising element in memory applications.
These four circuit variables in conjunction with the four passive circuit elements produced a set of six possible equations, one equation more than the previous five already known equations, due to the presence of memristor. We know details about resistors, capacitors and inductors. Therefore, in the following, these familiar passive circuit elements are introduced briefly, while the memristor is evaluated comprehensively.

2.1. Resistor

The resistor is a passive two-terminal basic electronic component discovered by Georg Simon Ohm in 1827, in which, at a constant temperature, the current flowing through these terminals is directly proportional to the voltage drop across it. Resistance is an inherent property of a material that resists the flow of electric charge (or electric current) through it, dissipating power in the process as heat. It is measured in Ohm ( Ω ) named after the inventor. Resistors are components designed basically to offer resistance in the circuit, commonly used as a current-limiting device. Virtually every electronic circuit is composed of at least one or more resistors, either a real component or by choosing the type of the material itself (resistivity). Currently, there are many types of resistors suitable for different applications, for example: Fixed resistor, Rheostat or Variable resistor, Potentiometer (pre-set or post-set), Thermistor, Varistor, Thermocouple, Photo resistor or Light-Dependent Resistor (LDR), Voltage-Dependent Resistor (VDR), Barretter, Strain gauge, etc. Some of them are nonlinear such as: Thermistor, Varistor, Photo resistor, etc. Resistors are characterized by: the resistance, the tolerance, the maximum working voltage, the power rating, the temperature coefficient, the noise, and even an inductance effect [20].

2.2. Capacitor

The capacitor is the first passive two-terminal basic electronic component invented by Ewald Georg von Kleist in 1745. It comprises two conductive materials separated by a dielectric. The dielectric could be air or any appropriate insulation material. Condenser is almost synonymous to capacitor, condenser being for the circuit element, capacitance for the electric characteristic, and these terminologies are often used interchangeably. Capacitance characterizes the amount of charge stored in the condensator between two parallel conducting materials subject to potential difference, and is measured in Farad (F) often used with sub-multiple prefixes such as micro ( μ ), nano (n), pico (p), etc. As with resistors, there are many different types of capacitors used for different applications. For example: Ceramic capacitor, electrolytic, film, Tantalum, Silva Mica, variable, SMD capacitors, etc. Capacitors have been used extensively in areas such as: power conditioning, signal processing, energy storage, coupling, filters, tuning radios and resonance, sensors, output regulation of power supply, etc.

2.3. Inductor

The inductor is a passive two-terminal basic electronic component discovered by Michael Faraday in 1831. It is capable of storing energy in the form of a magnetic field due to the passage of an electric current through it. Any current-carrying conductor is associated with a magnetic field circulating around the conductor. The strength of the field or magnetic flux is directly proportional to the magnitude of the electric current flowing through it. A straight coil wire has one turn and as such, it has less inductance. Moreover, the generated magnetic field becomes more significant if the wire is coiled to a certain number of turns. However, the field is more concentrated if the coil is wound on a ferromagnetic material (or iron core format) and has a higher inductance. Additionally, due to the variation of the formed magnetic flux, a voltage (self-induced voltage source according to Faraday’s law) is induced in the coil and acts in such a way to oppose itself to any change in the current that causes it (according to Lenz’s law). Similarly, there are various types of inductors made in different sizes and shapes, and some are sorted by the kind of applications and the type of winding and core materials. Power inductors are larger than general purpose inductors. In addition to storage of energy, the inductor is used extensively in numerous applications, such as: transformers, induction motors, relays, radio tuning, television, filters, transmission systems, sensors and many other applications in conjunction with capacitors and resistors.

2.4. Memristor

Memristor is claimed to be the fourth basic circuit element [10] (alongside the resistor, capacitor and inductor). It is a nonlinear passive two-terminal electronic component defined by the relationship between the magnetic flux linkage ϕ and the electric charge q. The definition of a memristor is given by its pioneer [21], as: “any 2-terminals device, exhibiting a pinched hysteresis loop which always passes through the origin in the voltage-current plane when driven by any periodic input current source, or voltage source, with zero DC component. If the input is a current source, it is called a current-controlled memristor. If it is a voltage source, it is called a voltage-controlled memristor ”. The name memristor is the contraction of memory resistor owing to its peculiar nature to resist the flow of electric current (as achieved by a resistor) and at the same time to remember the last amount of charge passed through it at the time when the power was disconnected, hence to memorizing the previous device resistance. Memristor keeps track of its dynamic resistance with respect to the current or electric charge flowing through it.
From the memristor symbol, see Figure 3, the unmarked side (the plus sign terminal) and the marked side (the minus sign terminal) indicate, respectively, the higher and lower potential terminal [22]. Memristor is a non-symmetrical two-port element, the polarity reversal and its effect from the application perspective was demonstrated [23]. This is very important for someone to consider before using a memristor in certain applications, e.g., biomimetic system [24].
Recall that the magnetic flux ϕ represents the time-integral of voltage V ( t ) and the electric charge q is the time-integral of electric current i ( t ) , hence these quantities are to be determined between two reference points. The fact that memristor is always defined by the integral of its input and output quantities ( V ( t ) and or i ( t ) ), explains in essence why memristor remembers its previous resistance or has a memory effect. The constitutive relationship of a memristor is expressed as d ϕ = M ( q ) d q , where M is the memristance that is short-form for memory resistance. Memristance is the property of a memristor to remember its previous resistance state. It is defined by the functional relationship between magnetic flux ϕ and electric charge q, and is measured in Ohms ( Ω ), the same measurement unit as resistance. The instantaneous memristance can be deduced from the dynamic slope of the ϕ -q locus given in the ϕ -q plane as shown in Figure 4. The relationship between the magnetic flux ϕ and the electric charge q could be expressed in two forms depending on the modes of excitation, namely: ϕ = f M ( q ) for a charge-controlled memristor (i.e., memristor device excited by a current source) or q = f G ( ϕ ) for a flux-controlled memristor (i.e., memristor device excited by a voltage source), where f M and f G are nonlinear functions denoting memristance and memductance, respectively.
The resistance of the memristor (or memristance) changes dynamically with the amount and direction of current flowing through it. People often confuse memristance with resistance. However, memristor differs from resistor in the sense that:
  • It has entirely different constitutive relationship in comparison to resistor.
  • Its resistance changes according to the quantity of charges having previously passed through it.
  • Its resistance changes according to the direction of electric current flowing through it because it is not a bilateral device. Therefore, its connection mode matters.
  • It preserves the previous history of electricity, according to the charge passed through it previously, at any given time. In other words, it has memory of the previous electricity passed through it (memory effect).
  • It is nonlinear in nature.
  • It has pinched hysteresis loop in the voltage–current response in a circuit, depending on its initial condition. Moreover, memristor has different circuit response according to its initial condition.
  • It cannot be realized by any combination of the three known circuit elements (capacitor, resistor and inductor) and hence it can be considered as “fundamental”.
  • It has a unique nature for the relationship between magnetic flux and electric charge (which is not directly available by measurement).
  • It behaves differently in DC and AC conditions.
Nevertheless, the memristor and resistor share some similarities, for example:
  • Both offer resistance to the flow of electric current.
  • Their quantities (i.e., memristance and resistance) have the same unit of measurement, i.e., Ohms, symbol: Ω .
  • No phase shift in their voltage and current wave-forms, because V ( t ) = M ( q ) i ( t ) i ( t ) = 0 if V ( t ) = 0 and vice versa.
  • They both dissipate energy as heat (Joule effect). They are not loss-less devices, i.e., without preservation of energy. They are always associated with power (P) intake, i.e., P 0 .

3. The Memristor Insights and Its Philosophical Arguments

A broader class of nonlinear systems is reported [11], called memristive systems in which some nonlinear dynamic systems were found to exhibit memristive behavior. Additionally, systems whose resistance depends on its internal state (e.g., temperature) are believed to be memristive. Examples of these systems are: Thermistor, Discharge tube, Hodgkin–Huxley (or Ionic) System and Tungsten filament lamps. The memristive systems are generally described by one-port and state equations:
y = f ( x , u , t ) u , d x d t = g ( x , u , t ) ,
where u is the input to the system, y is the output of the system, x is a vector denoting the set of internal state variables of the system, f is a nonlinear vector function and g is a nonlinear scalar function. Equation (4) affirms that memristive systems are nonlinear systems because the function f depends nonlinearly on the dynamic state variable x and both functions (f, g) depend on the input u to the system. Notice that Equation (4) describes a time-variant system, so all the variables are also functions of time. For time-invariant memristive systems, Equation (4) is rewritten as follows:
y = f ( x , u ) u , d x d t = g ( x , u ) .
Moreover, an ideal memristor is considered as a special case of a memristive system which can be expressed as:
y = f ( x ) u , d x d t = g ( u ) ,
where the state variable x depends solely on the time-integral of the voltage applied across the device or the time-integral of the current flowing through it, for a flux-controlled and charge-controlled memristor, respectively.
In Figure 5, a two-terminal device under test ( D . U . T ) is subjected to a periodic input source s ( t ) , where s ( t ) could be voltage or current source as highlighted in the aforementioned definition of memristor. If the current–voltage response of Figure 5 on the left corresponds to that of Figure 5 on the right, for any s ( t ) source respecting the definition in [21], then the black box is called a memristor. More details to check whether a candidate system is indeed a memristive system are given in the following.

3.1. Fingerprints of a Memristor

Circuit elements such as the resistor, capacitor, inductor, etc., are often characterized by their voltage–current response (V-I characteristics) in any given circuit. Memristor is not an exception, it has a peculiar voltage–current response which is a unique identifier that distinguishes it from any other known circuit element. Hence, it is called the fingerprint of a memristor and is used to characterize a memristive system. The most three well-known memristor fingerprints are enumerated in [25,26,27], as:
  • The V-I response of a memristor (with positive memristance) is always a pinched hysteresis loop (Lissajous figure) when subjected to a bipolar periodic input signal without offset.
  • The hysteresis lobe area decreases monotonically when the excitation frequency increases.
  • For a fixed-input amplitude, the pinched hysteresis loop shrinks to a single-valued function as the frequency of the input supply tends to infinity.
Figure 6 illustrates the mentioned three figerprints of a memristor. More fingerprints of an ideal memristor are given in [26], including constitutive relationship (CR) between flux and charge and parameter versus state map (PSM) [28]. In fact, nine fingerprints of memristor are given in [26] including the three above mentioned and they give birth to a valid test for assessing a memristor device. In the following, we give the description of a pinched hysteresis loop and pinched hysteresis lobe area.

3.1.1. Pinched Hysteresis Loop (PHL)

The voltage–current response of a memristor in a circuit is always a pinched hysteresis loop [27,29]. As seen in Figure 6a, the maxima and minima of the current i ( t ) and voltage V ( t ) , through and across the memristor, respectively, are not reached simultaneously and this is the cause of the formation of the hysteresis lobe area. The term pinched hysteresis loop (or PHL) refers to a double-valued Lissajous figure in the voltage–current (V–I) plane which is always pinched at the origin for any given time, for any initial condition, for any input amplitude (voltage or current) and for any input frequency [28]. The term pinched also signifies that V ( t ) = 0 whenever i ( t ) = 0 and vice versa. In other words, for any given value of current i ( t ) , there will be two corresponding values of voltage V ( t ) except at i ( t ) = 0 . The converse is also true, for any given value of voltage V ( t ) , there will be two corresponding values of current i ( t ) except at V ( t ) = 0 . This can be observed from Figure 6a: it shows that current ( i ( t ) in orange) is zero whenever the voltage ( V ( t ) in black) is zero and as a result the hysteresis loop always passes through the origin, see Figure 6b.
It turns out that memristive systems exhibit two different kinds of PHL [25,26] depending upon the system’s constituents (i.e., f and g as defined in Equation (4) and the type of excitation (odd-type or even-type) [26]. The two types of PHL are Self-crossing PHL (also known as Transversal or crossing PHL) and Tangential PHL (also known as non-tranversal or non-crossing PHL).
i.
Self-crossing or transversal pinched hysteresis loop (SPHL): In this type of PHL, the locus cuts across at the origin (or pinched point). Additionally, one can see that the slope of the locus moving toward the origin is different from that of the locus leaving the origin. Figure 7a shows a typical transversal PHL. An example of memristive system with transversal pinched hysteresis loop is the mathematical model of HP memristor (presented in Section 4).
ii.
Tangential or non-transversal pinched hysteresis loop (TPHL): As the name implies, the locus does not cut across, rather it passes tangentially as confirmed by the arrow directions, see Figure 7b. Notice that it is still pinched at the origin, i.e., V ( t ) = 0 whenever i ( t ) = 0 and vice versa, however, there is always a fixed slope (for both the two slopes, i.e., R o f f and R o n ) when the locus moves toward the origin and immediately after leaving the origin. This observation is clear because the separate line slopes coincide together before reaching the origin and remain together even after leaving the origin until a certain amount of voltage or current is reached, then the loci separate and hence the hysteresis lobe area becomes visible, see Figure 7b.
There are many memristive systems whose current–voltage response is a tangential PHL, some of these systems being mentioned in [11,25,30]. Moreover, tangential PHL is met in the memristive behavior of plants (Aloe vera and Mimosa pudica) [31]. However, it is reported that the pinched hysteresis loop of an ideal memristor, memcapacitor and meminductor is always a self-crossing PHL [32]. It is even emphasized that self-crossing PHL is another signature or fingerprint of an ideal memristor. Moreover, TiO 2 memristor (from HP lab [12]) and SDC memristor (from KNOWM [33]) are examples of a memristor with a self-crossing PHL.

3.1.2. Pinched Hysteresis Lobe Area

The hysteresis lobe area decreases when the input frequency increases. Recall that the memristor is a nano device, therefore, a small input signal is enough to generate a large electric field to trigger the device according to: E = d V d x , when x is the internal state and corresponds to the displacement of charge carriers. Therefore, any small increment in the potential difference V leads to a large magnitude of electric field E to be generated. However, the resistance of the memristor depends on its internal state, hence any change in the input signal results in a behavioral change of its internal state as well. Therefore, for example considering an input current i ( t ) such that:
i ( t ) = I 0 s i n ( ω t ) ,
the flowing charge is:
q ( t ) = t I 0 s i n ( ω τ ) d τ , = Q 1 c o s ( ω t ) + q 0 ,
where q 0 = 0 I 0 s i n ( ω τ ) d τ is the initial charge just before the current starts to flow and Q = I 0 ω is the charge delivered by the current source during the first quarter of the period T = 2 π ω and the magnitude peak-to-peak of the flowed charge is given by:
2 I 0 ω = 2 Q .
For an ideal charged-controlled memristor, its state variable is rather the charge flowing through the device. It is obvious from Equation (9) that increasing the frequency ω for a fixed amplitude I 0 , leads q ( t ) peak-to-peak amplitude to decrease significantly and hence causes the shrinkage of the pinched hysteresis loop towards a linear graph.
Figure 8a shows the effect of increasing input frequency on the PHL lobe area of the memristor. The input frequency ω is considered in three steps ω 1 , ω 2 and ω 3 with the corresponding lobe areas A 1 , A 2 and A 3 , respectively, such that:
ω 1 < ω 2 < ω 3
and
A 1 ( ω 1 ) > A 2 ( ω 2 ) > A 3 ( ω 3 )
It follows that: as ω , A 0 , this behavior is shown in Figure 8b.
The pinched hysteresis lobe area can be calculated. Let us consider a memristor excited by a current source given by i ( t ) = I 0 s i n ( ω t ) with ω = 2 π T , T being the period. By considering a half cycle (i.e., T 2 ) of the input i ( t ) , the hysteresis loop is given in Figure 9, having an enclosed area A and surface boundary S, altogether enclosed in a triangle O C D [34,35,36].
The area A is obtained from the surface integral of the voltage with respect to the current, as:
A = S v s . d i .
Figure 10 shows the operating point of a memristor in the plane (q, ϕ ) starting with an initial charge q 0 , corresponding to an initial flux ϕ 0 , with the so-called shifted flux ϕ = ϕ ϕ 0 . Let us use a shifted charge q = q q 0 , then:
q = Q 1 c o s ( ω t ) .
From Equations (9) and (11), the operating point is within the interval [ q 0 , q 0 + 2 Q ] , hence the normalized form of the constitutive relationship becomes:
f ^ ( ϕ , q ) = 0 .
The corresponding normalized expression of the memristance-versus-state map, becomes:
M ( q ) = M ( q + q 0 ) = d ϕ ( q ) d q .
From Equations (7) and (8), the algebraic relation between the charge q and the current source i ( t ) is:
i 2 = ω 2 ( 2 Q q ) q .
From Equation (10), with v ( t ) = M ( q ( t ) ) i ( t ) , the area during the first half-cycle can be expressed as:
A = 1 2 0 T 2 M ( q ( t ) ) d ( i 2 ) d t d t .
The integration by parts gives:
A = 1 2 M ( q ( t ) ) i 2 ( t ) 0 T 2 1 2 0 T 2 M ˙ ( q ( t ) ) i 2 ( t ) d t ,
where the dot in M represents the derivative with respect to time. In [34], the authors consider that the memristance function M ( q ) can exhibit step discontinuity points q j in the charge interval [ 0 , 2 Q ], with j = 1 , 2 , , n , hence, they considered some step changes of the memristance at point q j . However, the following excludes the case of any discontinuities for M ( q ) . In this simplified case, the first term of Equation (14) is zero. Noting that d M d t = d M d q · d q d t = d M d q · i ( t ) , Equation (14) gives then:
A = 1 2 0 T 2 d M d q i 3 d t .
For example, the pinched hysteresis lobe area of the memristance expression is given in [34] and is described in the following. The given memristance function is rewritten as:
M ( q ) = R i δ R q q d ,
where δ R = R o f f R o n , R i = R o f f δ R q 0 q d is the initial memristance at time t = 0 and q d is the charge necessary for the modification of the memristance by the value δ R [34]. Since R i is constant, then d M d q = δ R q d . Using the current source (7), then:
A = 1 2 δ R q d I 0 3 0 T 2 s i n 3 ( ω t ) d t .
Using the identity: s i n 3 ( α ) = 3 4 s i n ( α ) 1 4 s i n ( 3 α ) , then 0 T 2 s i n 3 ( ω t ) d t = 4 3 ω and the area is finally expressed as:
A = 2 3 δ R ω I o 3 q d .
The area is independent of the initial memristance, however, it is directly proportional to the cubic power of the exciting current and inversely proportional to the input frequency. Note that Equation (17) is determined according to the mathematical model of HP memristor, thus q d is the charge required to move the tunneling dopant barrier between the doped and undoped region from x 0 toward x 1 (see Section 4 for more details).
Moreover, a generalized formulation for computating the hysteresis lobe area of mem-elements is reported in [35], taking into account whether the input is a voltage or current. Thus, for a mem-element having input u ( t ) , output y ( t ) , state variable x ( t ) and a differentiable function h ( x ) , this mem-element can be characterized by:
y ( t ) = h ( x ) u ( t ) , d x ( t ) d t = u ( t ) ,
where:
u ( t ) = U m a x s i n ( ω t ) .
Thus, the loop area during the first half-cycle is given by:
A = 1 2 0 T 2 d h ( x ) d x u 3 d t .

3.2. Memristor by Mode of Excitation

Depending on the type of excitation, memristor can be characterized as charge-controlled memristor (CCM) or flux-controlled memristor (FCM), see Figure 11.

3.2.1. Charge-Controlled Memristor (CCM)

For a charge-controlled memristor, the input applied to the memristor is a current source. The set-up is given in Figure 11a, whereby a current source i ( t ) is connected to a memristor M. Thus, the current flowing through the memristor will cause a voltage drop V m ( t ) across it. From Equation (4), the three variables u, x and y become i, q and v, respectively, q being the time domain integral of the input current i and v the output voltage of the memristor. Hence, the constitutive relation of charge-controlled memristor should always represent the flux ( ϕ ) dependence on the charge (q), as:
ϕ = ϕ ^ ( q ) .
Substituting the variables i, q and V into Equation (6), then:
V = M ( q ) i , d q d t = i .
Note that the notation ϕ ^ in Equation (20) stands for a function definition: it could be any letter, for example f, such that: ϕ = f ( q ) , so the (^) will often be removed in the following. Furthermore, notice that Equations (20) and (21) are identical, with M ( q ) a charge-controlled memristance whose expression can be obtained by differentiating both sides of Equation (20) with respect to t: d ϕ d t = d d t ϕ ^ ( q ) . As the right hand side is a composite function, it can be seen that:
d ϕ d t = d ϕ ( q ) d q × d q d t d ϕ d t = M ( q ) d q d t = M ( q ) i .
Therefore, M ( q ) = d ϕ ( q ) d q = d ϕ d q . This equation can be rewritten conveniently as:
d ϕ = M ( q ) d q .
Moreover, (22) also gives the voltage drop V m ( t ) (see Figure 11a) across the charge-controlled memristor M ( q ) : d ϕ d t = M ( q ) d q d t , such that:
V m ( t ) = M ( q ) i ( t ) .
Example 1.
Suppose a charge-controlled memristor is characterized by the cubic function as follows:
ϕ ( t ) = β q ( t ) + α 3 q ( t ) 3 ,
where the α and β are in W b . C 3 and W b . C 1 , respectively, ( W b and C mean Weber and Coulomb, respectively). Equation (25) is a modified version of the one used by Chua [28], by adding parametric coefficients α and β in order for the equation to be homogeneous. It implies that:
M ( q ) = d ϕ d q = β + α q ( t ) 2 .
Let the input current i ( t ) be: i ( t ) = I o s i n ( ω t ) , then the charge is computed as follows:
q ( t ) = t i ( τ ) d τ = q 0 + I o ω 1 c o s ( ω t ) .
Knowing q 0 and q ( t ) , then M ( q ) and V m ( t ) can be calculated from Equations (24) and (26), respectively. Hence, q 0 is the memristor initial charge that determines its previous state. Figure 12 shows some examples for I o = 1 A , f = 4 H z , α = 1 W b . C 3 , β = 1 m W b . C 1 and two different values of q 0 as 0 C and 0.05 C , respectively, shown by Figure 12a,b.
It is expected that taking different values for q 0 , the operating point in Figure 12(a1) will be changed, as will the hysteresis curve of Figure 12(a3), compare Figure 12a,b.

3.2.2. Flux-Controlled Memristor (FCM)

Memristor is flux-controlled if the input applied to the memristor is a voltage source (see Figure 11b). The applied voltage V ( t ) causes current i m ( t ) to flow through the memristor M. One can see that the triad variables u, x and y in (6) become V, ϕ and i, respectively. Hence, the output of a flux-controlled memristor is current and its constitutive relationship represents the charge dependence on flux. The constitutive relationship of the memristor of this type is given in (28). The state variable is controlled by the flux as the result of time-domain integral of the applied input voltage.
q = q ^ ( ϕ ) .
Similarly, substituting the variables V, ϕ and i into (4), it gives:
i = Y ( ϕ ) V , d ϕ d t = V ,
where Y ( ϕ ) is the flux-controlled memductance, measured in Siemens S, the same S.I unit as conductance. Note that Y ( ϕ ) is the inverse of M ( q ) . Thus, ϕ is the time-domain integral of V:
ϕ = t V ( τ ) d τ , = ϕ 0 + 0 t V ( τ ) d τ .
Similarly, the expression of Y ( ϕ ) can be deduced by differentiating both sides of Equation (28) with respect to time. Therefore, d q d t = d d t q ( ϕ ) , that is:
d q d t = Y ( ϕ ) d ϕ d t ,
with Y ( ϕ ) = d q ( ϕ ) d ϕ = d q d ϕ
d q = Y ( ϕ ) d ϕ .
The current through the memristor i m ( t ) can be expressed from Equation (30), and is finally given by:
i m ( t ) = Y ( ϕ ) V ( t ) .
Example 2.
Suppose a flux-controlled memristor described by:
q = ψ 1 3 ϕ 3 + ψ 2 ϕ ,
ψ 1 and ψ 2 are appropriate constants in C . W b 3 and C . W b 1 , respectively. Given a source voltage: V ( t ) = V 0 s i n ( ω t ) , the equivalent expression of the flux is obtained to be: ϕ = V 0 ω 1 c o s ( ω t ) + ϕ 0 . Using (31), then:
Y ( ϕ ) = ψ 1 ϕ 2 + ψ 2 .
Hence, knowing Y ( ϕ ) , then i ( t ) is calculated and some examples are given in Figure 13a,b, respectively, for ϕ 0 = 0 Wb and ϕ 0 = 0.08 Wb . Similar to Figure 12, here the initial conditions also affect the ϕ -q operating point and hence the IV curve.

3.3. Memory Elements (Mem-Elements)

The emergence of the memristor led to the discovery of two other memory elements [9], namely: Memcapacitor and Meminductor [37,38,39]. The memristor M R is not a loss-less device while the memcapacitor M C and meminductor M L are loss-less devices. Their names are derived accordingly from the conventional three circuit elements (resistor, capacitor and inductor, respectively) due to some common features, for example, each having the same unit of measurement as Ohm, Farad and Henry, respectively.
This poses the question of whether the memristor is indeed the fourth circuit element due to its resistance dependency and the appearance of memcapacitor and meminductor. Instead of four circuit elements, why not six altogether? However, the memristor, memcapacitor and meminductor are classified as memory circuit elements or simply mem-elements owing to the ability to remember their previous history, which is a manifestation of their memory effects [40,41,42,43,44].
Due to the relation i = C d V d t for capacitor and V = L d i d t for inductor, the memory for these elements is already present by the occurrence of the time derivative (of voltage V for capacitor and of current i for inductor). This is not the case for V = R . i through a resistor, and this is the heart of all interests for the new element: the memristor. Notwithstanding, circuit elements can be classified into linear and nonlinear elements. Hence, resistor, capacitor and inductor are rather linear elements, whereas memristor, memcapacitor and meminductor are nonlinear elements.

3.4. Not Every Nonlinear Dynamical System Is an Ideal Memristor

Memristive systems are a class of nonlinear dynamical systems whose current–voltage response resembles the fingerprint of an ideal memristor. However, it is known that not every nonlinear dynamical system is ideally a memristor, even though it exhibits a pinched hysteresis loop in its current–voltage characteristic. Hence, the above outlined criteria of memristor identification are not enough to distinguish a memristor device from some nonlinear dynamical systems that are not associated with a memristor. As recalled earlier, the pinched hysteresis loop is the major criterion used to authenticate a given system as memristor or not [25]. In fact, it states that some memory elements may not exhibit pinched hysteresis loop, and an example of a memcapacitor is even given in [45]. There are concerns in the scientific community regarding what a memristor is and is not [16,17,18,19], and further elaborations by Blaise Mouttet and Pershin et al. [46,47,48,49,50] are explained in the following.
Leon Chua generalized the concept of memristor to include all resistance switching memories [28]. However, it is shown experimentally that resistance switching memories are not memristors [46]. Blaise Mouttet reported that L. Chua contradicted himself in [28], against their axiomatic definition of a memristor in 1971 [10]. He further concluded that the HP’s memristor lacks scientific merit [17].
It is further clarified that the pinched hysteresis loop as the fingerprint of a memristor, or a memristive device, must hold for all amplitudes, for all frequencies, and for all initial conditions, of any periodic testing waveform, such as sinusoidal or triangular signals, which assume both positive and negative values over each period of the waveform [29]. However, still some dynamical systems fulfilling these conditions are yet not memristor [47,48]. Notwithstanding, a simple testing technique to identify an ideal memristor is reported in [50], which could, together with the concept of pinched hysteresis loop, help to identify a memristor from a non-memristor. However, there is no memristor reported in the literature, adhering to the axiomatic definition that relates charge and flux. Therefore, we may conclude that all the reported memristors are resistive switching devices and they are a special class of memristive systems, hence not an ideal memristor. The fact that an ideal memristor is not yet found and/or simply does not exist, does not discredit the hitherto findings regarding the memristor, as they are still valuable in resistive random access memory (ReRAM) and many other applications, and justify all efforts to better understand this new element.
An ideal memristor is described axiomatically by the constitutive relationship between the charge and the flux, but there is not yet a memristor discovery based on this principle. Contemporarily, all the memristor technologies are based on bipolar resistance-switching mechanisms. This is the main reason used by some scientists to criticize the memristor discovery. In fact, when one considers the existence of an ideal memristor, a possible conclusion is that such a device is likely to be impossible. Optimistically, we believe that one-day such a device will be discovered. However, for the moment, all the memristors are resistance-switching devices with potential applications. Moreover, because they possess the signatures of an ideal memristor, they can be categorized as a special class of memristive system.

4. Memristor Technologies and Models

All memristor technologies follow similar principles of operation—called bipolar resistance switching, which means resistance switching between two limits, namely: R o n and R o f f accomplished by the evolution of the applied signal. R o n is the lower resistance limit (higher conducting state) while R o f f is the higher resistance limit (lower conducting state). Although the principle of operation is the same, each technology differs from one another in terms of resistance-switching mechanism (see Figure 14).
The HP memristor also known as TiO 2 memristor uses the principle of a Metal-Insulator-Metal (MIM) device in which a bilayer of titanium oxide (TiO 2 ) is placed between two platinum metal electrodes, as illustrated in Figure 15b [12]. One layer of the TiO 2 bilayer is doped with positive oxygen vacancies which allow for high conduction and the other layer is pure TiO 2 . Therefore, the formation exhibits two limiting resistance states ( R o f f and R o n ) due to the contraction and the expansion of the doped region. Following the discovery of TiO 2 memristor [12], many memristor technologies are reported using different switching mechanisms. Figure 14 shows the taxonomy of memristor technologies. The memristor technologies are based on ionic or magnetic effects.
For example, the self-directed channel (SDC) device (the KNOWM memristor) uses electropositive metal (e.g., Silver, Ag) for conduction and the resistance-switching transition is due to the formation and dissolution of a high conducting channel filament [13,33]. This is the only memristor chip available yet for purchase, see Figure 16. This is the chip used in the experimental demonstrations in Appendix A.
Other memristor technologies include the following. The ferroelectric memristor is based on a ferroelectric tunnel junction where the tunneling conductance allows for bistable resistance-switching transition and can be tuned according to the duration and amplitude of the applied voltage [51,52,53]. The memristive behavior was demonstrated experimentally and is attributed to the field-induced charge redistribution at the ferroelectric/electrode interface, which causes the modulation of the interface barrier height. Other memristors named according to fabricating materials, such as, the polymeric (or organic) [54,55], spintronic memristor [56,57], amorphous silicon memristor technology [58] and amorphous oxide semiconductor zinc–tin-oxide (ZTO) memristor [59]. In the following the TiO 2 memristor is considered due to its simpler modeling equations.

4.1. HP (TiO 2 ) Memristor: Modeling, Analysis and Interpretation

The TiO 2 memristor is the first discovered two-terminal solid-state memristor observed from a nano crossbar array of wires (see Figure 15a) in which each junction formed a memristor [3,60]. It was demonstrated that the memristor in the crossbar can act as a storage element to give binary output for color images or as a switch to produce different grayscale levels, allowing the processing of images [61]. Figure 15b shows the schematic of TiO 2 memristor [12]. It is made up of a thin film bilayer of Titanium-Oxide TiO 2 of thickness D sandwiched between two platinum (Pt) contacts which serve as electrodes. One portion of TiO 2 is initially doped with oxygen vacancies, and hence becomes TiO 2 - e and the other portion remains pure TiO 2 . These oxygen vacancies allow the layer to become an N-type semiconductor with electrons as charge carriers and thus adopt conductivity, the other undoped side has resistive properties, such that the entire arrangement behaves as a semiconductor material. Notice that in reality the dopants are scattered along the device width, however, its concentration in one edge is negligible compared to that of the other edge, creating two different resistive regions.
The structural arrangement constitutes two resistances R o n and R o f f connected in series, as illustrated in Figure 17. R o n resistance corresponds to the doped region (TiO 2 - e , i.e., higher conducting region) of width ( w ) while R o f f resistance corresponds to the undoped region (TiO 2 , i.e., lower conducting region) whose width is ( D w ) . Note that when w D , R o n R o n and if w 0 , R o f f R o f f . The boundary between doped and undoped regions (shown with two headed arrows) moves back and forth depending upon the direction of the flowing current or the polarity of the applied voltage. If the boundary moves leftward, w decreases and the opposite width ( D w ) increases, leading hence to higher resistance. Conversely, if the boundary moves rightward, w increases while ( D w ) decreases, leading hence to lower resistance. This further confirms the bipolar resistance-switching characteristics. Therefore, w acts as the state variable of the device characterizing the instantaneous memristance.
Owing to oxygen vacancies, the electrons, with mass m e and charge q = e , act as the charge carriers and are accelerated with an electric field:
E = V ( t ) R o n R o n w + R o f f ( D w )
and eventually stopped as they collide together. Their limiting speed v l is given by v l = μ v E = q . E m e t , where μ v is the mobility of the charge carriers and t is the average time between two consecutive collisions. The expressions of the voltages V 1 and V 2 across the doped and undoped regions can be expressed, respectively, as:
V 1 = V ( t ) R o n w R o n w + R o f f ( D w )
and
V 2 = V ( t ) R o f f ( D w ) R o n w + R o f f ( D w ) .
Note that the electric field in the conductive region can be expressed as E = V 1 w = R o n D i ( t ) . The charge carriers expand then the doped region towards the right corresponding to an increase in the width w with a positive current i ( t ) such that:
d w d t = μ v E = μ v R o n D i ( t ) ,
V ( t ) = M ( w ) i ( t ) ,
M ( w ) = R o n w ( t ) D + R o f f 1 w ( t ) D ,
where: V ( t ) is the voltage across the two-port device, i ( t ) is the current flowing through it, M ( w ) is the memristance. Note that v l = μ v E v l μ v = 1 μ v d w d t and v l = d w d t is the drift speed of the boundary. The dopant mobility ( μ v ) determines how quickly the boundary between doped and undoped regions (or the dopants) can move back and forth across the device for any applied signal. The tunneling of the barrier width w is determined by the magnitude and polarity of the applied voltage or current. It can be seen from Equation (38a) that at any given time t, the width w ( t ) of the doped region depends on the quantity of electric charge having passed through the device.
Finally, with the normalized form x ( t ) = w ( t ) D , the modeling Equations (38) become:
d x d t = μ v R o n D 2 i ( t ) ,
V ( t ) = M ( x ) i ( t ) ,
M ( x ) = R o f f δ R x ,
where δ R = R o f f R o n . M ( x ) = R o f f if x ( t ) = 0 and R o n if x ( t ) = 1 . Equation (39c) shows that the HP memristor model remembers the coordinate of the state variable x instead of the charge, however, the coordinate of x is related to the quantity of charge having flowed through the device. Hence x and q ( t ) are directly proportional to one another. When a signal is applied to the device, the boundary between the doped and undoped regions moves, the direction of this movement depending on the polarity of the applied signal. Recall that the memristance is always positive, therefore it is always expected that: x [ 0 , 1 ] or 0 x 1 . Integrating Equation (39a) for x from 0 to 1, it can be seen that:
q d = D 2 μ v R o n ,
where q d is the charge scaling factor which is required to move completely the doped/undoped boundary from w = 0 to w = D [62]. Equation (39a) is rather rewritten as:
d x d t = 1 q d i ( t ) ,
and this model is called the linear dopant drift model.

4.2. Window Function g ( x )

There exists enriched intrinsic nonlinearity within the memristor device which also manifests in its hysteretic behavior [12], however, when the dopants move toward either of the boundaries, that is, x = 0 or x = 1 , their speed decreases to zero which significantly affects the device dynamics and hence the performance. Due to the nano-nature of memristor devices, a small voltage can result in a huge electric field to be developed across the device, which in turn yields significant nonlinearities in the ionic transport [12]. These nonlinearities become more apparent in the boundaries where the drift speed of the dopant obviously reduces to zero. Hence, this phenomenon is called nonlinear dopant drift. However, the nonlinearity can be more pronounced at the boundary by inclusion of the window function g ( x ) .
Since the state variable x is bounded between 0 and 1, for an applied voltage bias, x is proportional to the quantity of charge q already passed through the device, until it approaches 0 or 1, where it requires higher voltage to switch from OFF resistance state to ON resistance state under positive bias and from ON resistance state to OFF resistance state under negative bias. Hence, the switching transition at these extreme boundaries is described as hard switching because these transitions delay until a certain amount of voltage threshold is reached. Thus, hard switching can be specified by considering different boundary conditions, hence the need for a window function. The window function g ( x ) is basically a dimensionless function multiplied to the right-hand side of Equation (41) for modeling the nonlinear dopant drift when x approaches 0 or 1 and for avoiding x from taking values outside of the limits [ 0 , 1 ]. For example, the SPICE circuit simulation of the linear model often reports computation errors attributed to the values of x. On the other hand, there is no such error even for a hard switching case if a window function (i.e., nonlinear model) is used.
Therefore, a window function g ( x ) is added as a factor in the right-hand side of Equation (41) in order to maintain x in the interval [ 0 , 1 ] [62]. This is called nonlinear dopant drift modeling and the state Equation (41) now becomes:
d x d t = 1 q d g ( x ) i ( t ) .
The model of TiO 2 memristor is usually characterized by two models, namely: linear and nonlinear dopant drift models, with the state equation given by (41) and (42), respectively. Some authors have tried to define the function g ( x ) with a more physical description of the device, in modeling the nonlinearity of the charge carriers along the device geometry. Due to the direct dependency of x on q ( t ) , Equation (42) suggests that a higher quantity of charge is needed for w to be closer to 0 or D [12]. Five sufficient and necessary conditions for any efficient window function are outlined by Prodromakis et al. [63].
The proper choice of the window function is of significant importance for predictive modeling of memristors because the system may respond differently with respect to the window function used [64]. There are many suggested window functions essentially to resolve the boundary issues and to impose nonlinearities [65,66,67,68,69,70,71,72,73,74,75]. However, each of them has their own advantages as well as their own disadvantages. Some of the commonly used window functions are described briefly in the following.
Strukov et al. [12,65] proposed a window function, given by:
g ( x ) = x ( 1 x ) .
In the boundary limits, x will remain at 0 or 1 until the device has changed its resistance state.
Joglekar et al. [62] proposed g ( x ) to be:
g ( x ) = 1 ( 2 x 1 ) 2 p ,
where p Z + is a positive integer serving as a control parameter. For large p, this window function gives a better nonlinear ionic drift than Strukov et al. However, the model reduces to linear dopant drift if p . Notice that for p = 1 , g ( x ) in Equation (44) becomes: g ( x ) = 4 x ( 1 x ) , that is, four times Strukov’s function. Hence, the control parameter p gives Joglekar’s function more flexibility than Strukov’s function.
Prodromakis et al. [63] proposed g ( x ) to be:
g ( x ) = 1 [ ( x 0.5 ) 2 + 0.75 ] p ,
where p R + is a positive real number. This function has hence more versatility than Joglekar’s function. Moreover, here p allows upward scaling of g ( x ) such that its maximum value, i.e., g m a x , remains in the interval: 0 g m a x 1 . One can also see that for p = 1 , g ( x ) in Equation (45) becomes: g ( x ) = x ( 1 x ) , the same as Strukov’s function. Similarly, for p , the model resembles linear drift model. Moreover, Prodromakis et al. take into account the unusual situation whereby the dopant’s drift is such that g m a x 1 , by introducing a new scalar j serving as a second control parameter in expression (45), thus becoming:
g ( x ) = j 1 [ ( x 0.5 ) 2 + 0.75 ] p .
For a fixed value of parameter p with j varying suitability, g ( x ) can be scaled up and down in conformity with: g m a x 1 .
Biolek et al. [66] proposed g ( x ) to be:
g ( x ) = 1 ( x s t p ( i ) ) 2 p ,
where p Z + and i is the current flowing through the memristor, such that:
s t p ( i ) = 1 f o r i 0 , 0 f o r i < 0 .
The flowing current i is considered as positive when the device is in saturation mode, i.e., x 1 corresponding to the expansion of the doped layer, and negative if the device is in depletion mode, i.e., x 0 which corresponds to the contraction of the doped layer. Notice that there is a discontinuity in the boundaries due to the step function definition of the current i.
Proposed window function:
In accordance with the role of window function, we propose g ( x ) as derived from Hann window apodisation function as follows:
g ( x ) = 1 2 1 + c o s 2 π ( α ( x ) ) .
Moreover, to fulfill the continuity constraints for x = 0 and x = 1 , a sufficient condition stands: α ( x ) = x 1 2 , that is:
g ( x ) = 1 2 1 + c o s π ( 2 x 1 ) .
Figure 18a shows the comparison of the four aforementioned window functions. The window functions by Strukov’s team and Biolek’s team lacking flexibility, a comparison is drawn between the models by Joglekar on one hand, and Prodromakis on the other, that is, Equations (44) and (45), respectively. The control parameter p is arbitrarily chosen in ascending order in order to observe the corresponding responses of g ( x ) : p = 1 , 2 , 10 , and 20 , and the results are given in Figure 18b. One can see that for all p, Joglekar’s function has g ( 0.5 ) = 1 , unlike Prodromakis’s function where g ( 0.5 ) is scalable from 0 to 1 with increase in p, with g ( 0.5 ) g m a x ( x ) . In addition, for p , both models resemble the linear drift model. Finally, another known window function is the ThrEshold Adaptive Memristor (TEAM) model [67].
Figure 19 shows the comparison of the nonlinear models by Strukov, Joglekar and Prodromakis with respect to the flowing charge. The high- and low-resistance states are R o f f = 16 K Ω and R o n = 100 Ω , respectively. Figure 19 shows the comparison of the memristance transition from its highest resistance state to the lowest state and vice versa. The results show that each model requires a different quantity of charge to fully transition from R o f f to R o n and vice versa.
The effect of choosing a memristor model for a particular application was investigated [76]. It was shown that the amount of charge q R required for the memristance to fully transit from its high resistance state to the low resistance state and vice versa depends on the model under consideration, see Table 1. Figure 20 shows the comparison of linear and nonlinear models on the memristance transition with respect to the flowing charge. The result is obtained using the nonlinear model by Joglekar and Wolf [62]. The results show that as the parameter p increases, the nonlinear model tends to the linear one.
The analytical solution of the memristor model is given in the following according to linear and nonlinear models, that is, by observing the effect of window function g ( x ) in the two possible scenarios: without any window function Equation (41) and with a window function according to Equation (42). The analysis also takes into account the mode of excitation, that is, charge-controlled and flux-controlled memristor.

4.3. Linear Dopant Drift Model: Analysis

Here, the state Equation (41) is considered solely, and the state variable x is calculated from this equation to be used in the memristance equation, and subsequently to determine the voltage drop across the memristor and the current flowing through it. Firstly, the case of a current excitation (charge-controlled memristor: CCM) is considered and then followed by the case of a voltage excitation (flux-controlled memristor: FCM). The analytical expressions are derived for each case and the results are given accordingly.

4.3.1. CCM with Linear Dopant Drift Model

In this case, the memristance is driven by a current source. Therefore, for a memristor with memristance M ( q ) subjected to a time-varying current source i ( t ) , the voltage drop across the memristor will be: V ( t ) = M ( q ) i ( t ) . The state variable x ( t ) can be expressed from Equation (41) by integration:
x ( t ) x 0 = 1 q d q ( t ) q 0 ,
where x 0 = w ( 0 ) D is the state variable at t = 0 , given the previous history of the device with a charge q 0 having already flowed through the memristor. Actually, for a formed (used) memristor device, x 0 is likely to be non-zero because the dopants are dis-localized, hence the device has some previous information preserved. It is easy to predict x 0 if the initial memristance of M ( x ) (i.e., M 0 ) is known. From Equation (39c): M 0 = R o f f δ R x 0 . Here, x 0 is simply a notation to represent the previous state of the device. Therefore, having q ( t ) known and x ( t ) expressed in terms of q ( t ) , from (39c) and (50), thus: M ( q ) = R o f f δ R x 0 δ R 1 q d ( q ( t ) q 0 ) . With the assumption x 0 1 so that, M 0 R o f f , thus:
M ( q ) = R o f f δ R q ( t ) q d .
Now, from the expression of M ( q ) , V ( t ) = M ( q ) i ( t ) is known for any i ( t ) and the result is given by Figure 21. The results show the effect of changing frequency on the VI characteristics.

4.3.2. FCM with Linear Dopant Drift Model

Here, the memristor is driven by a voltage source V ( t ) connected across its two terminals, and the current flowing through the memristor i ( t ) is given by: i ( t ) = Y ( ϕ ) V ( t ) , where Y ( ϕ ) is the memductance. From the definition of memristor: d ϕ = M ( q ) d q . Let us substitute an expression of M ( q ) from (51) in order to obtain the relationship between charge q ( t ) and the flux ϕ ( t ) , thus d ϕ = R o f f δ R q ( t ) q d d q :
ϕ ( t ) ϕ 0 = R o f f ( q ( t ) q 0 ) δ R 2 q d ( q ( t ) 2 q 0 2 ) .
This is a quadratic equation in q ( t ) and is solved to give the feasible value of q ( t ) compatible with the boundary condition:
q = q d 1 1 q 0 q d 2 2 ( ϕ ϕ 0 ) q d R o f f .
From the Equations (50) and (52):
x ( t ) = x 0 + 1 1 q 0 q d 2 2 ( ϕ ϕ 0 ) q d R o f f q 0 q d .
With x ( t ) known, M can easily be determined and Y = 1 M . Hence, for any input voltage V ( t ) connected across the memristor, the current i ( t ) is given by: i ( t ) = Y ( ϕ ) V ( t ) . Figure 22 shows the current–voltage response and the corresponding state variables for three different input frequencies.

4.4. Nonlinear Dopant Drift Model: Analysis

Here, we consider the nonlinear dopant drift model which is characterized by Equation (42). Considering g ( x ) by Joglekar and Wolf [62], for p = 1 : g ( x ) = 4 x ( 1 x ) corresponding to the g ( x ) in [12] multiplied by four. The voltage across and current through the memristor can be calculated. This then corresponds rather to Strukov’s window function that will be considered as:
g ( x ) = x ( 1 x ) .

4.4.1. CCM with Nonlinear Dopant Drift Model

The state Equation (42) becomes: d x d t = 1 q d x ( 1 x ) i ( t )
x ( t ) = x 0 e q q 0 q d 1 x 0 + x 0 e q q 0 q d ,
where q ( t = 0 ) = q 0 and x ( t = 0 ) = x 0 are the initial conditions at time t = 0 . Therefore, the charge-controlled memristance M ( q ) becomes:
M ( q ) = R o f f δ R x 0 e q q 0 q d 1 x 0 + x 0 e q q 0 q d .
With an input current i ( t ) = I 0 s i n ( ω t ) , the voltage across the memristor is: V ( t ) = M ( q ) i ( t ) and the results are shown in Figure 23.

4.4.2. FCM with Nonlinear Dopant Drift Model

Recall that for any input voltage V ( t ) = V 0 s i n ( ω t ) applied to the memristor, the flux is given by ϕ ( t ) = V 0 ω 1 c o s ( ω t ) + ϕ 0 and the dynamic state of the memristor x ( t ) is driven by flux ϕ ( t ) . Therefore, once again by definition V ( t ) = M ( q ) d q ( t ) d t , from Equation (55), it follows that:
q ( t ) = q 0 q d ln e V 0 [ 1 c o s ( ω t ) ] q d δ R ω x 0 1 x 0 .
Similarly, x ( t ) can be obtained. From Equations (54) and (56), thus: Y = 1 M and i ( t ) = Y ( ϕ ) V ( t ) and the results are shown in Figure 24.

4.4.3. In-Memory Computing

In traditional computing (Von Neumann computing architecture), the memory and processing units are separate. Therefore, data processing involves read and write protocols. This process is delayed and energy consuming which is not efficient in high-density data applications such as neural networks and artificial intelligence. These concerns can be avoided by allowing the data to be processed within the memory block, hence referred to as in-memory computing (IMC).
Large networks, such as, neural networks for brain-inspired systems require in-memory computing in order to avoid latency for data accession and processing. This approach improves the processing speed and, hence the overall network performance. In recent years, in-memory computing has become a significant field of study owing to the sizeable data era challenges. Memristor is proved to be a reliable element for achieving efficient memristor-based in-memory computing which is an alternative architecture to Von Neumann computing [77,78]. Many challenges such as stochasticity, CMOS compatibility, memristor integration, etc., for the implementation of memristor-based computing architecture are further discussed in [78,79].
There is significant progress in the development phase of memristor-based in-memory computing, including device architectures, material engineering and challenges to practical implementation [80,81,82,83,84,85,86,87,88,89,90,91].

5. Spice and Analogue Models of Memristor

SPICE is an acronym of Simulation Program with Integrated Circuit Emphasis used for simulating and analyzing different circuit functionality. The mathematical description of a given phenomenon can be modeled in SPICE with the aid of its built-in control sources (for example, voltage-controlled voltage source, voltage-controlled current source, behavioral sources, etc.) and other components such as resistors, capacitors, OpAmps. With the discovery of TiO 2 memristor, many SPICE models of memristor were proposed mimicking its behavior. The mathematical description of HP TiO 2 memristor is used to emulate memristor characteristics, as such many models are reported and some are based on particular applications [92,93,94,95,96,97]. The most commonly used SPICE model is that developed by Biolek et al. [66], whose setup is shown in Figure 25. Figure 25a shows the block diagram representation of the port and state equations of the memristor:
V ( t ) = R o f f δ R x I ( t ) and d x d t = k I ( t ) f ( x ) with k = μ v R o n D 2 .
The ammeter (A) senses the current flowing through the memristor, meanwhile the memory effect is modeled by means of a feedback-controlled integrator. The feedback of the nonlinear window function f ( x ) models the nonlinear dopant drift and the influence of the boundary conditions. The memristance value between R o f f and R o n is determined by the coordinate of x ( 0 , 1 ) .
Figure 25b shows the equivalent SPICE schematic of the Equation (57). The capacitor C x whose initial voltage models the initial state of the normalized width x 0 , is used as the integrator of the differential state equation. The port equation is modeled with the aid of E-type voltage source (voltage-dependent voltage source) whose source is the voltage of capacitor and then multiplied by the gain δ R , and is connected in series with a resistor R o f f . V ( x ) is the voltage of the capacitor C x and it models the normalized width x of the memristor, while R s h is the shunt resistor grounding the integrator unit. The integrand, that is, the quantity on the right-hand side of the state equation is modeled with the aid of a G-type current source (voltage-dependent current source) that multiplies the memristor current I by the gain k f ( V ( x ) ) . The SPICE netlist file of Figure 25b is given in Figure 26, and is used to create memristor SPICE components for simulation purposes. The integral of the current (or charge) and voltage (or flux), respectively, flowing through and across the memristor can be modeled using the E-type voltage source, hence allowing visualization of the monotonically increasing function of q versus ϕ in the ϕ -q plane.
The initial state of the memristor is given by the initial voltage V ( x 0 ) across the capacitor. The initial memristance R i is determined as: R i = R o f f δ R x 0 .  Figure 27 shows the results of the memristor netlist file in Figure 26. The result is obtained using a sine voltage source connected across the port terminals pl and mn of the memristor. Figure 27a shows the transient results of voltage and current for an input voltage amplitude of 1.2 V and the corresponding I–V characteristic is given in Figure 27b. Furthermore, Figure 27c shows the corresponding monotonically increasing ϕ -q function, thus matching the characteristics of the memristor from its constitutive relationship. Meanwhile, Figure 27d shows the memristance with respect to the transition of the device state variable.

5.1. Analogue Models of Memristor

Analogue memristor models are developed using analog and active components such as operational amplifiers, hence modeling the behavior of memristor for simulation [98,99,100,101,102,103]. Analog models can be easily implemented in the laboratory for practical and research purposes. For example, Figure 28 shows an analog model of a flux-controlled memristor [98]. The model is analyzed by considering different input signals, for example sinusoidal, triangular input voltage sources, etc., and shows a pinched hysteresis loop, which is the primary signature of a memristor.
Figure 25b is similar to Figure 28 with differences in the integration unit, that is RC and operational amplifier, respectively. Comparing the two figures, one can see that R s h = R and C x = C . As shown in the introduction that for flux-controlled memristors, the state variable is a function of flux and the memristor dynamics depend upon the flux whose magnitude is proportional to the voltage across the memristor. In Figure 28, the operational amplifier block is used as an integrator to generate its output voltage proportional to the flux. The output flux is expressed as:
V ϕ ( t ) = 1 τ V ( t ) d t ,
where τ = R C is a time constant. The memductance G M ( t ) depends linearly on V ϕ ( t ) , with:
G M ( t ) = G 0 + K G V ϕ ( t ) ,
where G 0 and K G are constants. Finally, the current i ( t ) is given by:
i ( t ) = G M ( t ) · V ( t ) .
Equations (58)–(60) are analyzed using a sine voltage V ( t ) as:
V ( t ) = V 0 s i n ( ω t ) ,
whose flux ϕ ( t ) is represented by the voltage V ϕ ( t ) obtained by integrating (61):
V ϕ ( t ) = V 0 τ ω 1 c o s ( ω t ) + ϕ 0 τ ,
where ϕ 0 is the initial flux. Knowing the flux V ϕ ( t ) , the memductance G m ( t ) and the current i ( t ) are to be calculated using Equations (59) and (60), respectively. Figure 29 shows the results of sinusoidal input voltage, observed for different frequencies and Figure 29 shows the results obtained for sine input voltage with values parameters: R = 1 K Ω , C = 1 μ F, G 0 = 0.5 S and K G = 10 S V 1 . The results are significantly modified with the changes of G 0 , K G and frequency.

Passive Models of the Memristor Emulator

Figure 30 shows the schematic of a passive memristor emulator [102]. The model is similar to the one in Figure 28 with the exception that junction field effect (JFET) transistor is used instead of the operational amplifier and without any need for internal power to operate. The voltage across the gate (G) terminal with respect to the source (S) terminal corresponds to the voltage V C across the capacitor C provided that the gate resistance ( R G ) is infinite, that is no current flows through R G . The role of the gate resistance R G is to avoid leakage of current through the gate, therefore, it separates the gate from the output of the RC cell which acts as a passive lossy integrator having the cutoff frequency f c = 1 2 π R C .
R D is a small resistance (optional) connected to the drain terminal in order to measure the current flowing through the drain and then the source terminal. Since no current goes into the gate terminal of the JFET, the current through the resistor R is the same as that through the capacitor, that is: I R = I C . Therefore, V C = V G S , controls the current through the D-S junction. For frequencies below f c , the current I R = C d V C d t is reflectible with respect to I D . Taking into account the differential equation of the RC cell and its high impedance level (i.e., I R I D ), the mathematical relationship of Figure 30 can be expressed from Kirchhoff’s laws:
C d V C d t + V C V R = 0
d V C d t = 1 R C ( V V C ) .
The transconductance of the device is controlled by the voltage V C across the capacitor and, hence it is equivalent to the state variable x of the system: V C = x . Furthermore, this state variable V C corresponds to the integral of the port voltage V and V D S = V because R D is negligible. Therefore, the characteristics of JFET transistor as given in [98], are:
I D = g ^ ( V G S , V D S ) V D S = g ^ ( x , V ) V .
From Equations (63) and (64) we obtained the following state-dependent Ohm’s law relationship:
d x d t = 1 R C ( V x ) ,
I = g ^ ( x , V ) V .
This model is used experimentally for the study of chaos in Duffing oscillator [104,105].

6. Modeling

The pinched hysteresis loop gives the circuit response of a memristor and is considered the primary signature for identifying memristive systems. Recall that a memristor is characterized by the constitutive relationship between magnetic flux ϕ and electric charge q, hence the equivalent graphical representation is called ϕ -q curve which in essence gives the characteristics of a memristor. The ϕ -q curve is used to effectively model memristor because it also provides a better representation and analysis of a study dealing with certain initial conditions [21]. The description of the ϕ -q curve of model (39) was illustrated in detail [106]. The memristor model (39) remembers the coordinate of its state variable. However, the dynamics of the state variable x are proportional to the charge q ( t ) flowing through it. Therefore, from Equation (39a), it gives:
x ( t ) = q ( t ) q d = 1 q d q 0 + 0 t i ( τ ) d τ ,
and the expression of the memristance becomes:
M ( q ) = R o f f , if q ( t ) 0 R o f f δ R q ( t ) q d , if 0 q ( t ) q d R o n . if q ( t ) q d
Equation (67) shows the expression of the memristance M ( q ) as a function of the flowing charge q ( t ) . With d ϕ = M ( q ) d q , Equation (67) can be simplified further to observe the ϕ -q curve. Furthermore, it was shown that the model (67) has discontinuities for its first derivative versus q at q = 0 and q = q d which is disadvantageous in the study of memristor dynamics in CNN neighborhood connections between pixel cells because the system requires a continuous d M d q ( q ) function for all of the flowing charge [106,107]. To avoid such discontinuities, a new model was proposed as follows [106]:
M ( q ) = R o f f , if q ( t ) 0 R o f f 3 δ R q d 2 q 2 + 2 δ R q d 3 q 3 , if 0 q ( t ) q d R o n , if q ( t ) q d
with its first derivative with respect to charge given by:
d M ( q ) d q = 6 δ R q d 2 q + 6 δ R q d 3 q 2 , if 0 q ( t ) q d 0 . if q 0 or q q d
Furthermore, using d ϕ = M ( q ) d q and Equation (68), the corresponding expression of the relationship between flux ϕ and charge q is given by:
ϕ = R o f f q , if q ( t ) 0 R o f f q δ R q d 2 q 3 + δ R 2 q d 3 q 4 , if 0 q ( t ) q d R o n q + δ R 2 q d , if q ( t ) q d .
Note that here again, ϕ = ϕ ^ ( q ) can be shifted vertically or horizontally according to the choice of initial conditions. Figure 31 shows the comparison of the models (67) and (68). The result is obtained for R o f f = 16 K Ω , R o n = 100 Ω and q d = 100 μ C . The black curve is for model (67) and it exhibits angulation due to the discontinuities at q = 0 and q = q d . However, the red continuous curve is for the new model (68) which shows a rather better result because it solves the problem of derivative discontinuity at q ( t ) = 0 or q d . The new model (68) gives a better representation of information in a neuronal scheme. Furthermore, the response of the new model is shown in Figure 32 obtained using a periodic sine input current source.

7. Some Potential Applications of Memristor

Memristor has many interesting features useful in electrical and electronic system designs. The following are some features associated with a memristor:
It stores information, hence reliable for memory applications.
It undergoes nano-scalability, hence suitable for modern-day nanotechnology.
Conductance modulation resembling chemical synapse.
It has connection flexibility, that is, series-parallel connections, and can form a stack of memory cells for high-density storage applications.
It is compatible with CMOS technology allowing it to have a massively real-time and parallel computation in hybrid systems due to its reliable adaptability with CMOS neurons.
It is a nonlinear circuit element, by its nature.
It has low power consumption. As a nano device, it requires little power to operate.
One memristor can replace multiple transistors in a circuit, thus it will ensure better performance and more reliable systems.
Undoubtedly, the aforementioned features suggest the memristor to be a proper candidate in modern-day electronic industries and for designing very effective neuromorphic systems and memory applications [108,109,110,111]. Figure 33 shows the taxonomy of memristor applications in discrete and crossbar array configurations which display the varieties of the memristor possibilities [112]. Since the discovery of HP TiO 2 memristor, the number of published memristive-based applications has increased exponentially. Hence, utilizing memristive devices in existing applications gives numerous advantages, for example: non-volatility, scalability, no leakage current and many more due to its compatibility with CMOS technology in terms of both electrical connections and manufacturing processes.
In the last few years, there have been many proposed memristor-based applications [112,113,114]. The memristor has non-volatility properties with long retention and fast switching times [115], and is reported to be useful in high-density memory applications, e.g., non-volatile random access memory (NVRAM) and resistive random access memory (ReRAM) [116], storage and processing of big data, image recognition and processing [117,118]. The application of memristor could also be useful in field programmable gate array (FPGA) and implementation of chaotic circuits due to its adaptability to parallel and real-time computations [101,119]. Other applications areas include programmable analogue logic circuits [120,121,122], frequency and amplitude modulation [123], edge detection [124], neuromorphic system and bio-electronics [125,126,127,128] and cellular nonlinear/neural networks (CNN) [129,130,131].
Another intriguing application area of the memristor is its use as a synapse due to its conductance modulation resembling chemical synapse and very effective high-density connectivity [131,132]. Memristor-based electronic synapses are implemented, applicable to various neuromorphic computing architectures [133,134,135,136,137,138,139]. In fact, there is great progress in the phase of using memristor in neural networks and artificial intelligence [140,141,142,143,144,145,146,147,148,149].
Although the memristor is useful as a synapse in an artificial neural network, however, being a two-terminal component, it may not be adequate to effectively implement the high-density synaptic connections as each neuron has multiple synaptic connections to other neurons. Therefore, a hybrid multi-terminal memristor component such as memtransistor, with more connection terminals will be more efficient [150,151,152]. Thus, memtransistor is basically a combination of memristor and transistor and is determined to give a rather more brain-like network than a standalone memristor. Recently, a scalable multi-terminal memtransistor was implemented experimentally using a polycrystalline monolayer of molybdenum disulfide (MoS 2 ) and the results were very promising. Hence, memtransistor is reported to be useful in neuromorphic computing, for example, as artificial synapse and others such as nonvolatile memory and logic circuits [152,153,154,155,156].
A new function of the memristor as a transducer—called the memosducer—is demonstrated experimentally, and is particularly interesting in the optimization of ultrasonic excitation for Time Reversal-Nonlinear Elastic Wave Spectroscopy (TR-NEWS) dedicated to nonlinear acoustic imaging [157,158]. It was shown that the features of memristor such as hysteretic properties, nonlinearity and memory effect, etc., are promising in TR-NEWS-based ultrasonic imaging.
We are currently working on a memristor-based 2D cellular nonlinear network for signal and image processing as well as electronic prosthesis [76]. Figure 34 shows the schematic of the memristor-based 2D cellular nonlinear network using memristors in the coupling mode. The network is essential for signal and image processing with each cell corresponding to a pixel in an image application purpose. Each cell comprises one linear capacitor C in parallel with nonlinear resistance R N L , and the nonlinear current response through the cell is expressed as:
I N L ( m , n ) = f ( V m , n ) = V m , n R o ( V m , n V a ) ( V m , n V b ) V a V b ,
meanwhile the nonlinear resistance at this node R N L ( V m , n ) is given by:
R N L ( V m , n ) = V m , n I N L ( m , n ) = R o V a V b ( V m , n V a ) ( V m , n V b ) ,
and the corresponding potential energy W ( V m , n ) becomes:
W ( V m , n ) = 1 4 V m , n 4 V a + V b 3 V m , n 3 + V a V b 2 V m , n 2 + C ,
where C is a constant of integration. Meanwhile, the parameters V a and V b are the characteristic roots of the nonlinear resistance R N L , as used previously in Fitzhugh Nagumo model and R o is the linear approximation of R N L , see Figure 35a. Unlike RC cells where each cell always stabilizes at 0, here the cell can stabilize at a point of lowest potential energy corresponding to V n = 0 and V n = V b (see Figure 35b) and these are the two possible equilibrium states. Therefore: 0, V a and V b are constant voltages corresponding to the characteristic roots of the cubic function f ( V n ) at any nodal potential V m , n under consideration, such that: 0 < V a < V b .
Hence, with V a being unstable potential state, it implies 0 and V b are the only two stable states. For example, it can be seen from Figure 35b that, for: V b 2 V a > 0 the cell stabilizes at V b and for: V b 2 V a < 0 the cell stabilizes at 0. With respect to the parameters under consideration, different analysis can be performed including the history of the memristor and its effect on image succession.

8. Discussion

The paper presented briefly the three familiar passive circuit elements (R, L and C) and the general description and philosophical argumentation of the fourth passive circuit element - the memristor (M). Memristor technologies are introduced, then followed by the details of the modeling analysis of TiO 2 memristor. According to the mode of excitation, the analytical solutions and results of linear and nonlinear dopant drift models are obtained. The difference between linear and nonlinear models is highly observable as the state variable of the system approaches 0 or 1. For a very small input voltage applied to the memristor, the linear and nonlinear models respond similarly because the state variable operates within the bulk of the device, not toward the edge [76]. The effect of increasing input frequency is shown for each model and the shrinkage of the pinched hysteresis loop area is due to the inverse relationship between the flowing charge q ( t ) and the input frequency ω (i.e., q ( t ) = I o ω ). Furthermore, a new window function is presented, which is derived from the Hann window function. Its response is compared with the ones obtained from the three other functions by Strukov, Joglekar and Prodromakis. From a circuitry perspective, it was shown that the choice of window function is very important for memristor modeling, because each model responds differently due to the different level of imposed nonlinearities [76].
The model of TiO 2 memristor is used to create memristor components in SPICE for circuit simulation purposes. This approach is extended whereby analog components, such as an operational amplifier, are used to mimic the behavior of memristor in SPICE for simulation of memristor-based applications. The passive model of the memristor (Figure 30) operates under some restricted values of parameters in order to meet the conditions I R I D and the value of the cutoff frequency f c . Therefore, we are working to improve this model by avoiding these limitations.
Using the relationship between the state variable x and the charge q, the memristance function is expressed as a function of the flowing charge. Memristor is normally modeled from its constitutive relationship between flux ϕ and charge q because the pinched hysteresis loop only describes its circuit response. A new model of memristor is presented, and due to its desirable continuity for all charges q ( t ) flowing through the memristor, it is essentially vital in the study of memristor dynamics regarding the neuronal scheme especially when the memristor acts as a synapse.
In general, the advantages of the memristor outweighed its disadvantages and this can be seen in the potentiality of its outlined features in this paper. However, there are some concerns especially in its technology and modeling. For example, the TiO 2 memristor is the first reported two-terminal solid-state memristor, however, it is not yet available for purchase, though it bears a very handy mathematical description used widely to analyze some memristor-based applications. There could be some underlying issues of oxygen in the TiO 2 memristor preventing it from being readily available for purchase. Meanwhile, the SDC (KNOWM) memristor does not have a modeling equation to be used for SPICE circuit simulation of a memristor-based network prior to its implementation. It has been shown that each model responds differently from one another [76]. Therefore, one has to choose carefully the technology or model for use in a given application. Even though there are many in house metal-insulator-metal (MIM) memristors, the technological aspects need to be improved in order to meet the demand of this new and exciting component.
There is good progress in the development phase of a memristor-based networks especially in neuromorphic computing and memory applications. Memristor is able to store and process information at the same time, which in turn reduces power consumption, device circuitries and improve performance. Furthermore, this particular feature suggests the memristor to be a promising element as an alternative to Von Neumann architecture in avoiding the problems of memory-access bottleneck [159]. In fact, memristor brings an era of brain-like computing with some already in the implementation phase for practical realization.
The responses of the four basic passive circuit elements from the perspective of their circuitry are given in Appendix A. Hence, these elements are distinguishable from one another. Memristor may not be the fourth fundamental passive circuit element alongside the resistor, capacitor and inductor [18,19]. A simple test to identify an ideal memristor is presented [50]. According to this test, all the available memristors are resistive switching devices and an ideal memristor remains unlikely to be found [46]. Nevertheless, the contemporary memristor technologies are resistive switching devices, which can be categorized as a special class of memristive system owing to their pinched hysteresis loop characteristics, and they impart a massive technological impact in the twenty first century.

Funding

This research received no external funding.

Institutional Review Board Statement

Not applicable.

Informed Consent Statement

Not applicable.

Data Availability Statement

Not applicable.

Conflicts of Interest

The author declare no conflict of interest.

Appendix A. Experimental Results Showing the Typical Voltage-Current Response of the Four Basic Passive Circuit Elements

Figure A1. Experimental results of the four fundamental passive circuit elements. (a1a3) R = 1 K Ω , (b1b3) C = 10 nF, (c1c3) L = 10 mH and (d1d3) KNOWM memristor chip (see Figure 16). The current and voltage waveforms for each component are shown along with the corresponding IV characteristics. There is no phase difference in V ( t ) and I ( t ) waveforms for R and M, while there is a phase difference of π 2 for C and L. In the capacitor C, I ( t ) is leading the V ( t ) by π 2 and in an inductor L, V ( t ) is leading I ( t ) by π 2 . The IV characteristic of R is a linear graph, for C and L it is a circle (respectively with clockwise and anticlockwise) and for M it is a pinched hysteresis loop. Scales: R: time t [0.50 ms/div], current I [0.31 mA/div] and voltage V [ 0.50 V / div ] , C: time t [0.50 ms/div], current I [ 0.28 m A / div ] and voltage V [ 0.50 V / div ] , L: time t [ 20 μ s / div ] , current I [ 0.31 m A / div ] and voltage V [ 0.50 V / div ] and M: time t [ 0.50 m s / div ] , current I [ 4.45 μ A / div ] and voltage V [ 1.0 V / div ] .
Figure A1. Experimental results of the four fundamental passive circuit elements. (a1a3) R = 1 K Ω , (b1b3) C = 10 nF, (c1c3) L = 10 mH and (d1d3) KNOWM memristor chip (see Figure 16). The current and voltage waveforms for each component are shown along with the corresponding IV characteristics. There is no phase difference in V ( t ) and I ( t ) waveforms for R and M, while there is a phase difference of π 2 for C and L. In the capacitor C, I ( t ) is leading the V ( t ) by π 2 and in an inductor L, V ( t ) is leading I ( t ) by π 2 . The IV characteristic of R is a linear graph, for C and L it is a circle (respectively with clockwise and anticlockwise) and for M it is a pinched hysteresis loop. Scales: R: time t [0.50 ms/div], current I [0.31 mA/div] and voltage V [ 0.50 V / div ] , C: time t [0.50 ms/div], current I [ 0.28 m A / div ] and voltage V [ 0.50 V / div ] , L: time t [ 20 μ s / div ] , current I [ 0.31 m A / div ] and voltage V [ 0.50 V / div ] and M: time t [ 0.50 m s / div ] , current I [ 4.45 μ A / div ] and voltage V [ 1.0 V / div ] .
Jlpea 12 00044 g0a1

References

  1. Xing, R.; Wang, J.; Chen, Q. The Contemporary IT Transformations. Proc. Northeast. Bus. Econ. Assoc. 2010, 19, 3–53. [Google Scholar]
  2. Seitz, F. On the trail of the transistor. Nature 1997, 388, 339–340. [Google Scholar] [CrossRef]
  3. Stanley Williams, R. How we found the missing memristor. In Chaos, CNN, Memristors and Beyond: A Festschrift for Leon Chua with DVD-ROM, Composed by Eleonora Bilotta; World Scientific: Singapore, 2013; pp. 483–489. [Google Scholar]
  4. Swingler, J. Reliability Characterisation of Electrical and Electronic Systems; Elsevier: Amsterdam, The Netherlands, 2015. [Google Scholar]
  5. Lin, D.; Chua, L.; Hui, S.Y. The first human-made memristor: Circa 1801 [scanning our past]. Proc. IEEE 2014, 103, 131–136. [Google Scholar] [CrossRef]
  6. Prodromakis, T. Two centuries of memristors. In Chaos, CNN, Memristors and Beyond: A Festschrift for Leon Chua With DVD-ROM, Composed by Eleonora Bilotta; World Scientific: Singapore, 2013; pp. 508–517. [Google Scholar]
  7. Wuttig, M.; Yamada, N. Phase-change materials for rewriteable data storage. Nat. Mater. 2007, 6, 824. [Google Scholar] [CrossRef] [PubMed]
  8. Kato, T.; Tanaka, K. Electronic properties of amorphous and crystalline Ge2Sb2Te5 films. Jpn. J. Appl. Phys. 2005, 44, 7340. [Google Scholar] [CrossRef]
  9. Pershin, Y.V.; Di Ventra, M. Memory effects in complex materials and nanoscale systems. Adv. Phys. 2011, 60, 145–227. [Google Scholar] [CrossRef]
  10. Chua, L. Memristor-the missing circuit element. IEEE Trans. Circuit Theory 1971, 18, 507–519. [Google Scholar] [CrossRef]
  11. Chua, L.O.; Kang, S.M. Memristive devices and systems. Proc. IEEE 1976, 64, 209–223. [Google Scholar] [CrossRef]
  12. Strukov, D.B.; Snider, G.S.; Stewart, D.R.; Williams, R.S. The missing memristor found. Nature 2008, 453, 80. [Google Scholar] [CrossRef]
  13. Nugent, A. Knowm Memristor Introduction. Available online: https://knowm.org/category/memristor/ (accessed on 15 March 2022).
  14. Johnsen, G.K. An introduction to the memristor-a valuable circuit element in bioelectricity and bioimpedance. J. Electr. Bioimpedance 2012, 3, 20–28. [Google Scholar] [CrossRef]
  15. Irving, M. Smallest 3D Transistors Ever Made Measure a Minuscule 2.5 Nanometers. Available online: https://newatlas.com/smallest-transistors-microfabrication/57583/ (accessed on 15 March 2022).
  16. Mouttet, B. Memresistors and non-memristive zero-crossing hysteresis curves. arXiv 2012, arXiv:1201.2626. [Google Scholar]
  17. Mouttet, B. The Memristor and the Scientific Method. Available online: https://vixra.org/pdf/1205.0004v1.pdf (accessed on 15 March 2022).
  18. Vongehr, S.; Meng, X. The missing memristor has not been found. Sci. Rep. 2015, 5, 11657. [Google Scholar] [CrossRef] [PubMed]
  19. Abraham, I. The case for rejecting the memristor as a fundamental circuit element. Sci. Rep. 2018, 8, 10972. [Google Scholar] [CrossRef] [PubMed]
  20. Kothi Mandhana, K. Seminar Report on Memristor. Available online: https://www.researchgate.net/profile/Mangal-Das/publication/277564724_Seminar_Report_on_Memristor/links/556d526a08aeccd7773befc7/Seminar-Report-on-Memristor.pdf?origin=publication_detail (accessed on 15 March 2022).
  21. Chua, L. Everything you wish to know about memristors but are afraid to ask. Radioengineering 2015, 24, 319. [Google Scholar] [CrossRef]
  22. Di Ventra, M.; Pershin, Y.V.; Chua, L.O. Putting memory into circuit elements: Memristors, memcapacitors, and meminductors [point of view]. Proc. IEEE 2009, 97, 1371–1372. [Google Scholar] [CrossRef]
  23. Isah, A.; Tchakoutio Nguetcho, A.; Binczak, S.; Bilbault, J. Polarity Reversal Effect of a Memristor From the Circuit Point of View and Insights Into the Memristor Fuse. Front. Comms. Netw. 2021, 2, 647528. [Google Scholar] [CrossRef]
  24. Gelencser, A.; Prodromakis, T.; Toumazou, C.; Roska, T. Biomimetic model of the outer plexiform layer by incorporating memristive devices. Phys. Rev. E 2012, 85, 041918. [Google Scholar] [CrossRef]
  25. Adhikari, S.P.; Sah, M.P.; Kim, H.; Chua, L.O. Three fingerprints of memristor. IEEE Trans. Circuits Syst. Regul. Pap. 2013, 60, 3008–3021. [Google Scholar] [CrossRef]
  26. Biolek, D.; Biolek, Z.; Biolková, V.; Kolka, Z. Some fingerprints of ideal memristors. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, 19–23 May 2013; pp. 201–204. [Google Scholar]
  27. Chua, L. If it’s pinched it’sa memristor. Semicond. Sci. Technol. 2014, 29, 104001. [Google Scholar] [CrossRef]
  28. Chua, L. Resistance switching memories are memristors. Appl. Phys. A 2011, 102, 765–783. [Google Scholar] [CrossRef]
  29. Kim, H.; Sah, M.P.; Adhikari, S.P. Pinched hysteresis loops is the fingerprint of memristive devices. arXiv 2012, arXiv:1202.2437. [Google Scholar]
  30. Clauss, D.; Ralich, R.; Ramsier, R. Hysteresis in a light bulb: Connecting electricity and thermodynamics with simple experiments and simulations. Eur. J. Phys. 2001, 22, 385. [Google Scholar] [CrossRef]
  31. Markin, V.S.; Volkov, A.G.; Chua, L. An analytical model of memristors in plants. Plant Signal. Behav. 2014, 9, e972887. [Google Scholar] [CrossRef]
  32. Biolek, D.; Biolek, Z.; Biolkova, V. Pinched hysteretic loops of ideal memristors, memcapacitors and meminductors must be ‘self-crossing’. Electron. Lett. 2011, 47, 1385–1387. [Google Scholar] [CrossRef]
  33. Campbell, K.A. Self-directed channel memristor for high temperature operation. Microelectron. J. 2017, 59, 10–14. [Google Scholar] [CrossRef]
  34. Biolek, Z.; Biolek, D.; Biolková, V. Computation of the area of memristor pinched hysteresis loop. IEEE Trans. Circuits Syst. II Express Briefs 2012, 59, 607–611. [Google Scholar] [CrossRef]
  35. Biolek, Z.; Biolek, D.; Biolkova, V. Analytical computation of the area of pinched hysteresis loops of ideal mem-elements. Radioengineering 2013, 22, 132–135. [Google Scholar]
  36. Biolek, D.; Biolek, Z.; Biolkova, V. Interpreting area of pinched memristor hysteresis loop. Electron. Lett. 2014, 50, 74–75. [Google Scholar] [CrossRef]
  37. Di Ventra, M.; Pershin, Y.V.; Chua, L.O. Circuit elements with memory: Memristors, memcapacitors, and meminductors. Proc. IEEE 2009, 97, 1717–1724. [Google Scholar] [CrossRef]
  38. Yin, Z.; Tian, H.; Chen, G.; Chua, L.O. What are memristor, memcapacitor, and meminductor? IEEE Trans. Circuits Syst. II Express Briefs 2015, 62, 402–406. [Google Scholar]
  39. Chua, L. Memristor and Memristive Systems Symposium; University California: Berkeley, CA, USA, 2008. [Google Scholar]
  40. Cohen, G.Z.; Pershin, Y.V.; Di Ventra, M. Lagrange formalism of memory circuit elements: Classical and quantum formulations. Phys. Rev. B 2012, 85, 165428. [Google Scholar] [CrossRef]
  41. Di Ventra, M.; Pershin, Y.V. Memory materials: A unifying description. Mater. Today 2011, 14, 584–591. [Google Scholar] [CrossRef]
  42. Pershin, Y.V.; Martinez-Rincon, J.; Di Ventra, M. Memory circuit elements: From systems to applications. J. Comput. Theor. Nanosci. 2011, 8, 441–448. [Google Scholar] [CrossRef]
  43. Pershin, Y.V.; Di Ventra, M. Neuromorphic, digital, and quantum computation with memory circuit elements. Proc. IEEE 2011, 100, 2071–2080. [Google Scholar] [CrossRef]
  44. Di Ventra, M.; Pershin, Y.V. Biologically-inspired electronics with memory circuit elements. In Advances in Neuromorphic Memristor Science and Applications; Springer: Berlin/Heidelberg, Germany, 2012; pp. 15–36. [Google Scholar]
  45. Pershin, Y.V.; Di Ventra, M. Comment on ‘If it’s pinched it’s a memristor’. Semicond. Sci. Technol. 2019, 34, 098001. [Google Scholar] [CrossRef]
  46. Kim, J.; Pershin, Y.V.; Yin, M.; Datta, T.; Di Ventra, M. An Experimental Proof that Resistance-Switching Memory Cells are not Memristors. Adv. Electron. Mater. 2020, 6, 2000010. [Google Scholar] [CrossRef]
  47. Mouttet, B. Pinched Hysteresis Loops Are a Fingerprint of Square Law Capacitors. Available online: https://vixra.org/pdf/1205.0008v2.pdf (accessed on 15 March 2022).
  48. Mouttet, B. Response to ‘Pinched Hysteresis Loops is the Fingerprint of Memristive Devices’. Available online: https://vixra.org/pdf/1205.0009v1.pdf (accessed on 15 March 2022).
  49. Biolek, D.; Biolek, Z.; Biolkova, V.; Ascoli, A.; Tetzlaff, R. About v-i pinched hysteresis of some non-memristive systems. Math. Probl. Eng. 2018, 2018. [Google Scholar] [CrossRef]
  50. Pershin, Y.V.; Di Ventra, M. A simple test for ideal memristors. J. Phys. Appl. Phys. 2018, 52, 01LT01. [Google Scholar] [CrossRef]
  51. Chanthbouala, A.; Garcia, V.; Cherifi, R.O.; Bouzehouane, K.; Fusil, S.; Moya, X.; Xavier, S.; Yamada, H.; Deranlot, C.; Mathur, N.D.; et al. A ferroelectric memristor. Nat. Mater. 2012, 11, 860–864. [Google Scholar] [CrossRef]
  52. Kim, D.; Lu, H.; Ryu, S.; Bark, C.W.; Eom, C.B.; Tsymbal, E.; Gruverman, A. Ferroelectric tunnel memristor. Nano Lett. 2012, 12, 5697–5702. [Google Scholar] [CrossRef]
  53. Hu, Z.; Li, Q.; Li, M.; Wang, Q.; Zhu, Y.; Liu, X.; Zhao, X.; Liu, Y.; Dong, S. Ferroelectric memristor based on Pt/BiFeO3/Nb-doped SrTiO3 heterostructure. Appl. Phys. Lett. 2013, 102, 102901. [Google Scholar] [CrossRef]
  54. Erokhin, V.; Berzina, T.; Fontana, M.P. Hybrid electronic device based on polyaniline-polyethyleneoxide junction. J. Appl. Phys. 2005, 97, 064501. [Google Scholar] [CrossRef]
  55. Chen, Y.; Liu, G.; Wang, C.; Zhang, W.; Li, R.W.; Wang, L. Polymer memristor for information storage and neuromorphic applications. Mater. Horizons 2014, 1, 489–506. [Google Scholar] [CrossRef]
  56. Wang, X.; Chen, Y.; Xi, H.; Li, H.; Dimitrov, D. Spintronic memristor through spin-torque-induced magnetization motion. IEEE Electron. Device Lett. 2009, 30, 294–297. [Google Scholar] [CrossRef]
  57. Pershin, Y.V.; Di Ventra, M. Spin memristive systems: Spin memory effects in semiconductor spintronics. Phys. Rev. B 2008, 78, 113309. [Google Scholar] [CrossRef]
  58. Jo, S.H.; Chang, T.; Ebong, I.; Bhadviya, B.B.; Mazumder, P.; Lu, W. Nanoscale memristor device as synapse in neuromorphic systems. Nano Lett. 2010, 10, 1297–1301. [Google Scholar] [CrossRef] [PubMed]
  59. Murali, S.; Rajachidambaram, J.S.; Han, S.Y.; Chang, C.H.; Herman, G.S.; Conley, J.F., Jr. Resistive switching in zinc–tin-oxide. Solid-State Electron. 2013, 79, 248–252. [Google Scholar] [CrossRef]
  60. Williams, R.S. Finding the Missing Memristor. Available online: https://www.youtube.com/watch?v=bKGhvKyjgLY (accessed on 15 March 2022).
  61. Hu, X.; Duan, S.; Wang, L.; Liao, X. Memristive crossbar array with applications in image processing. Sci. China Inf. Sci. 2012, 55, 461–472. [Google Scholar] [CrossRef]
  62. Joglekar, Y.N.; Wolf, S.J. The elusive memristor: Properties of basic electrical circuits. Eur. J. Phys. 2009, 30, 661. [Google Scholar] [CrossRef]
  63. Prodromakis, T.; Peh, B.P.; Papavassiliou, C.; Toumazou, C. A versatile memristor model with nonlinear dopant kinetics. IEEE Trans. Electron Devices 2011, 58, 3099–3105. [Google Scholar] [CrossRef]
  64. Slipko, V.A.; Pershin, Y.V. Importance of the window function choice for the predictive modelling of memristors. IEEE Trans. Circuits Syst. II Express Briefs 2019, 68, 2167–2171. [Google Scholar] [CrossRef]
  65. Benderli, S.; Wey, T. On SPICE macromodelling of TiO2 memristors. Electron. Lett. 2009, 45, 377–379. [Google Scholar] [CrossRef]
  66. Biolek, Z.; Biolek, D.; Biolkova, V. SPICE Model of Memristor with Nonlinear Dopant Drift. Radioengineering 2009, 18, 210–214. [Google Scholar]
  67. Kvatinsky, S.; Friedman, E.G.; Kolodny, A.; Weiser, U.C. TEAM: Threshold adaptive memristor model. IEEE Trans. Circuits Syst. Regul. Pap. 2012, 60, 211–221. [Google Scholar] [CrossRef]
  68. Anusudha, T.; Prabaharan, S. A versatile window function for linear ion drift memristor model—A new approach. AEU-Int. J. Electron. Commun. 2018, 90, 130–139. [Google Scholar] [CrossRef]
  69. Kvatinsky, S.; Talisveyberg, K.; Fliter, D.; Kolodny, A.; Weiser, U.C.; Friedman, E.G. Models of memristors for SPICE simulations. In Proceedings of the IEEE 27th Convention of Electrical and Electronics Engineersn, Eilat, Israel, 4–17 November 2012; pp. 1–5. [Google Scholar]
  70. Yu, J.; Mu, X.; Xi, X.; Wang, S. A memristor model with piecewise window function. Radioengineering 2013, 22, 969–974. [Google Scholar]
  71. Takahashi, Y.; Sekine, T.; Yokoyama, M. SPICE model of memristive device using Tukey window function. IEICE Electron. Express 2015, 12, 20150149. [Google Scholar] [CrossRef]
  72. Abdel-Kader, R.F.; Abuelenin, S.M. Memristor model based on fuzzy window function. In Proceedings of the IEEE International Conference on Fuzzy Systems (FUZZ-IEEE), Istanbul, Turkey, 2–5 August 2015; pp. 1–5. [Google Scholar]
  73. Zha, J.; Huang, H.; Liu, Y. A novel window function for memristor model with application in programming analog circuits. IEEE Trans. Circuits Syst. II Express Briefs 2015, 63, 423–427. [Google Scholar] [CrossRef]
  74. Singh, J.; Raj, B. An accurate and generic window function for nonlinear memristor models. J. Comput. Electron. 2019, 18, 640–647. [Google Scholar] [CrossRef]
  75. Georgiou, P.S.; Yaliraki, S.N.; Drakakis, E.M.; Barahona, M. Window functions and sigmoidal behaviour of memristive systems. Int. J. Circuit Theory Appl. 2016, 44, 1685–1696. [Google Scholar] [CrossRef]
  76. Isah, A.; Nguetcho, A.S.T.; Binczak, S.; Bilbault, J.M. Comparison of the Performance of the Memristor Models in 2D Cellular Nonlinear Network. Electronics 2021, 10, 1577. [Google Scholar] [CrossRef]
  77. Sun, K.; Chen, J.; Yan, X. The future of memristors: Materials engineering and neural networks. Adv. Funct. Mater. 2021, 31, 2006773. [Google Scholar] [CrossRef]
  78. Li, Y.; Wang, Z.; Midya, R.; Xia, Q.; Yang, J.J. Review of memristor devices in neuromorphic computing: Materials sciences and device challenges. J. Phys. Appl. Phys. 2018, 51, 503002. [Google Scholar] [CrossRef]
  79. Zidan, M.A.; Strachan, J.P.; Lu, W.D. The future of electronics based on memristive systems. Nat. Electron. 2018, 1, 22–29. [Google Scholar] [CrossRef]
  80. Zhang, X.; Lu, J.; Wang, Z.; Wang, R.; Wei, J.; Shi, T.; Dou, C.; Wu, Z.; Zhu, J.; Shang, D.; et al. Hybrid memristor-CMOS neurons for in situ learning in fully hardware memristive spiking neural networks. Sci. Bull. 2021, 66, 1624–1633. [Google Scholar] [CrossRef]
  81. Lee, Y.; Lee, T.W. Organic synapses for neuromorphic electronics: From brain-inspired computing to sensorimotor nervetronics. Acc. Chem. Res. 2019, 52, 964–974. [Google Scholar] [CrossRef]
  82. Miranda, E.; Suñé, J. Memristors for neuromorphic circuits and artificial intelligence applications. Materials 2020, 13, 938. [Google Scholar] [CrossRef] [PubMed]
  83. Hu, M.; Graves, C.E.; Li, C.; Li, Y.; Ge, N.; Montgomery, E.; Davila, N.; Jiang, H.; Williams, R.S.; Yang, J.J.; et al. Memristor-based analog computation and neural network classification with a dot product engine. Adv. Mater. 2018, 30, 1705914. [Google Scholar] [CrossRef]
  84. Prezioso, M.; Merrikh-Bayat, F.; Hoskins, B.; Adam, G.C.; Likharev, K.K.; Strukov, D.B. Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature 2015, 521, 61–64. [Google Scholar] [CrossRef]
  85. Wang, Z.; Wu, H.; Burr, G.W.; Hwang, C.S.; Wang, K.L.; Xia, Q.; Yang, J.J. Resistive switching materials for information processing. Nat. Rev. Mater. 2020, 5, 173–195. [Google Scholar] [CrossRef]
  86. Ielmini, D.; Wong, H.S.P. In-memory computing with resistive switching devices. Nat. Electron. 2018, 1, 333–343. [Google Scholar] [CrossRef]
  87. Sebastian, A.; Le Gallo, M.; Khaddam-Aljameh, R.; Eleftheriou, E. Memory devices and applications for in-memory computing. Nat. Nanotechnol. 2020, 15, 529–544. [Google Scholar] [CrossRef] [PubMed]
  88. Cheng, L.; Li, J.; Zheng, H.X.; Yuan, P.; Yin, J.; Yang, L.; Luo, Q.; Li, Y.; Lv, H.; Chang, T.C.; et al. In-Memory Hamming Weight Calculation in a 1T1R Memristive Array. Adv. Electron. Mater. 2020, 6, 2000457. [Google Scholar] [CrossRef]
  89. Lin, H.; Wu, Z.; Liu, L.; Wang, D.; Zhao, X.; Cheng, L.; Lin, Y.; Wang, Z.; Xu, X.; Xu, H.; et al. Implementation of Highly Reliable and Energy Efficient in-Memory Hamming Distance Computations in 1 Kb 1-Transistor-1-Memristor Arrays. Adv. Mater. Technol. 2021, 6, 2100745. [Google Scholar] [CrossRef]
  90. Lalchhandama, F.; Datta, K.; Chakraborty, S.; Drechsler, R.; Sengupta, I. CoMIC: Complementary Memristor based in-memory computing in 3D architecture. J. Syst. Archit. 2022, 126, 102480. [Google Scholar] [CrossRef]
  91. Mehonic, A.; Sebastian, A.; Rajendran, B.; Simeone, O.; Vasilaki, E.; Kenyon, A.J. Memristors—From In-Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio-Inspired Computing. Adv. Intell. Syst. 2020, 2, 2000085. [Google Scholar] [CrossRef]
  92. Pershin, Y.V.; Di Ventra, M. SPICE model of memristive devices with threshold. arXiv 2012, arXiv:1204.2600. [Google Scholar]
  93. Kvatinsky, S.; Ramadan, M.; Friedman, E.G.; Kolodny, A. VTEAM: A general model for voltage-controlled memristors. IEEE Trans. Circuits Syst. II Express Briefs 2015, 62, 786–790. [Google Scholar] [CrossRef]
  94. Kvatinsky, S.; Talisveyberg, K.; Fliter, D.; Friedman, E.G.; Kolodny, A.; Weiser, U.C. Verilog-A for Memristor Models. Available online: https://asic2.group/wp-content/uploads/2017/06/VerilogA-models-technical-report.pdf (accessed on 15 March 2022).
  95. Biolek, D.; Biolek, Z.; Biolkova, V. SPICE modeling of memristive, memcapacitative and meminductive systems. In Proceedings of the European Conference on Circuit Theory and Design, Antalya, Turkey, 23–27 August 2009; pp. 249–252. [Google Scholar]
  96. Radwan, A.G.; Zidan, M.A.; Salama, K. HP memristor mathematical model for periodic signals and DC. In Proceedings of the 53rd IEEE International Midwest Symposium on Circuits and Systems, Washington, DC, USA, 1–4 August 2010; pp. 861–864. [Google Scholar]
  97. Rák, Á.; Cserey, G. Macromodeling of the memristor in SPICE. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010, 29, 632–636. [Google Scholar] [CrossRef]
  98. Valsa, J.; Biolek, D.; Biolek, Z. An analogue model of the memristor. Int. J. Numer. Model. Electron. Netw. Devices Fields 2011, 24, 400–408. [Google Scholar] [CrossRef]
  99. Sánchez-López, C.; Mendoza-Lopez, J.; Carrasco-Aguilar, M.; Muñiz-Montero, C. A floating analog memristor emulator circuit. IEEE Trans. Circuits Syst. II Express Briefs 2014, 61, 309–313. [Google Scholar]
  100. Xiao-Yuan, W.; Fitch, A.L.; Iu, H.H.; Sreeram, V.; Wei-Gui, Q. Implementation of an analogue model of a memristor based on a light-dependent resistor. Chin. Phys. B 2012, 21, 108501. [Google Scholar]
  101. Muthuswamy, B. Implementing memristor based chaotic circuits. Int. J. Bifurc. Chaos 2010, 20, 1335–1350. [Google Scholar] [CrossRef]
  102. Biolek, D.; Biolkova, V.; Kolka, Z.; Biolek, Z. Passive fully floating emulator of memristive device for laboratory experiments. Adv. Electr. Comput. Eng. 2015, 1, 112–116. [Google Scholar]
  103. Kim, H.; Sah, M.P.; Yang, C.; Cho, S.; Chua, L.O. Memristor emulator for memristor circuit applications. IEEE Trans. Circuits Syst. Regul. Pap. 2012, 59, 2422–2431. [Google Scholar]
  104. Bodo, B.; Fouda, J.A.E.; Mvogo, A.; Tagne, S. Experimental hysteresis in memristor based Duffing oscillator. Chaos Solitons Fractals 2018, 115, 190–195. [Google Scholar] [CrossRef]
  105. Fouda, J.A.E.; Bodo, B.; Djeufa, G.M.; Sabat, S.L. Experimental chaos detection in the Duffing oscillator. Commun. Nonlinear Sci. Numer. Simul. 2016, 33, 259–269. [Google Scholar] [CrossRef]
  106. Isah, A.; Nguetcho, A.S.T.; Binczak, S.; Bilbault, J.M. Memristor dynamics involved in cells communication for a 2D non-linear network. IET Signal Process. 2020, 14, 427–434. [Google Scholar] [CrossRef]
  107. Isah, A.; Nguetcho, A.T.; Binczak, S.; Bilbault, J. Dynamics of a charge-controlled memristor in master–slave coupling. Electron. Lett. 2020, 56, 211–213. [Google Scholar] [CrossRef]
  108. Adam, G.C.; Hoskins, B.D.; Prezioso, M.; Merrikh-Bayat, F.; Chakrabarti, B.; Strukov, D.B. 3-D memristor crossbars for analog and neuromorphic computing applications. IEEE Trans. Electron. Devices 2016, 64, 312–318. [Google Scholar] [CrossRef]
  109. Wang, Z.; Joshi, S.; Savel’ev, S.E.; Jiang, H.; Midya, R.; Lin, P.; Hu, M.; Ge, N.; Strachan, J.P.; Li, Z.; et al. Memristors with diffusive dynamics as synaptic emulators for neuromorphic computing. Nat. Mater. 2017, 16, 101–108. [Google Scholar] [CrossRef] [PubMed]
  110. Kim, K.H.; Gaba, S.; Wheeler, D.; Cruz-Albrecht, J.M.; Hussain, T.; Srinivasa, N.; Lu, W. A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications. Nano Lett. 2012, 12, 389–395. [Google Scholar] [CrossRef] [PubMed]
  111. Gaba, S.; Sheridan, P.; Zhou, J.; Choi, S.; Lu, W. Stochastic memristive devices for computing and neuromorphic applications. Nanoscale 2013, 5, 5872–5878. [Google Scholar] [CrossRef] [PubMed]
  112. Mazumder, P.; Kang, S.M.; Waser, R. Memristors: Devices, models, and applications. Proc. IEEE 2012, 100, 1911–1919. [Google Scholar] [CrossRef]
  113. Prodromakis, T.; Toumazou, C. A review on memristive devices and applications. In Proceedings of the 17th IEEE International Conference on Electronics, Circuits and Systems, Athens, Greece, 12–15 December 2010; pp. 934–937. [Google Scholar]
  114. Marani, R.; Gelao, G.; Perri, A.G. A review on memristor applications. arXiv 2015, arXiv:1506.06899. [Google Scholar]
  115. Eshraghian, K.; Cho, K.R.; Kavehei, O.; Kang, S.K.; Abbott, D.; Kang, S.M.S. Memristor MOS content addressable memory (MCAM): Hybrid architecture for future high performance search engines. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 2010, 19, 1407–1417. [Google Scholar] [CrossRef]
  116. Hu, S.; Wu, S.; Jia, W.; Yu, Q.; Deng, L.; Fu, Y.Q.; Liu, Y.; Chen, T.P. Review of nanostructured resistive switching memristor and its applications. Nanosci. Nanotechnol. Lett. 2014, 6, 729–757. [Google Scholar] [CrossRef]
  117. Hamdioui, S.; Xie, L.; Du Nguyen, H.A.; Taouil, M.; Bertels, K.; Corporaal, H.; Jiao, H.; Catthoor, F.; Wouters, D.; Eike, L.; et al. Memristor based computation-in-memory architecture for data-intensive applications. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, Grenoble, France, 9–13 March 2015; pp. 1718–1725. [Google Scholar]
  118. Duan, S.; Hu, X.; Wang, L.; Li, C.; Mazumder, P. Memristor-based RRAM with applications. Sci. China Inf. Sci. 2012, 55, 1446–1460. [Google Scholar] [CrossRef]
  119. Xu, Y.M.; Wang, L.D.; Duan, S.K. A memristor-based chaotic system and its field programmable gate array implementation. Acta Phys. Sin. 2016, 65, 120503. [Google Scholar]
  120. Pershin, Y.V.; Di Ventra, M. Practical approach to programmable analog circuits with memristors. IEEE Trans. Circuits Syst. Regul. Pap. 2010, 57, 1857–1864. [Google Scholar] [CrossRef]
  121. Shin, S.; Kim, K.; Kang, S.M. Memristor applications for programmable analog ICs. IEEE Trans. Nanotechnol. 2010, 10, 266–274. [Google Scholar] [CrossRef]
  122. Borghetti, J.; Snider, G.S.; Kuekes, P.J.; Yang, J.J.; Stewart, D.R.; Williams, R.S. ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature 2010, 464, 873–876. [Google Scholar] [CrossRef]
  123. Göknar, İ.C.; Öncül, F.; Minayi, E. New memristor applications: AM, ASK, FSK, and BPSK modulators. IEEE Antennas Propag. Mag. 2013, 55, 304–313. [Google Scholar] [CrossRef]
  124. Hutchinson, J.; Koch, C.; Luo, J.; Mead, C. Computing motion using analog and binary resistive networks. Computer 1988, 21, 52–63. [Google Scholar] [CrossRef]
  125. Linares-Barranco, B.; Serrano-Gotarredona, T. Memristance can explain spike-time-dependent-plasticity in neural synapses. Nat. Preced. 2009. [Google Scholar] [CrossRef]
  126. Chu, M.; Kim, B.; Park, S.; Hwang, H.; Jeon, M.; Lee, B.H.; Lee, B.G. Neuromorphic hardware system for visual pattern recognition with memristor array and CMOS neuron. IEEE Trans. Ind. Electron. 2014, 62, 2410–2419. [Google Scholar] [CrossRef]
  127. Snider, G.S. Spike-timing-dependent learning in memristive nanodevices. In Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, Anaheim, CA, USA, 12–13 June 2008; pp. 85–92. [Google Scholar]
  128. Yakopcic, C.; Hasan, R.; Taha, T.M. Flexible memristor based neuromorphic system for implementing multi-layer neural network algorithms. Int. J. Parallel Emergent Distrib. Syst. 2018, 33, 408–429. [Google Scholar] [CrossRef]
  129. Duan, S.; Hu, X.; Dong, Z.; Wang, L.; Mazumder, P. Memristor-based cellular nonlinear/neural network: Design, analysis, and applications. IEEE Trans. Neural Netw. Learn. Syst. 2014, 26, 1202–1213. [Google Scholar] [CrossRef]
  130. Thomas, A. Memristor-based neural networks. J. Phys. Appl. Phys. 2013, 46, 093001. [Google Scholar] [CrossRef]
  131. Adhikari, S.P.; Yang, C.; Kim, H.; Chua, L.O. Memristor bridge synapse-based neural network and its learning. IEEE Trans. Neural Netw. Learn. Syst. 2012, 23, 1426–1435. [Google Scholar] [CrossRef]
  132. Kim, H.; Sah, M.P.; Yang, C.; Roska, T.; Chua, L.O. Memristor bridge synapses. Proc. IEEE 2011, 100, 2061–2070. [Google Scholar] [CrossRef]
  133. Saïghi, S.; Mayr, C.G.; Serrano-Gotarredona, T.; Schmidt, H.; Lecerf, G.; Tomas, J.; Grollier, J.; Boyn, S.; Vincent, A.F.; Querlioz, D.; et al. Plasticity in memristive devices for spiking neural networks. Front. Neurosci. 2015, 9, 51. [Google Scholar] [CrossRef]
  134. Lecerf, G.; Tomas, J.; Boyn, S.; Girod, S.; Mangalore, A.; Grollier, J.; Saïghi, S. Silicon neuron dedicated to memristive spiking neural networks. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, 1–5 June 2014; pp. 1568–1571. [Google Scholar]
  135. Boyn, S.; Grollier, J.; Lecerf, G.; Xu, B.; Locatelli, N.; Fusil, S.; Girod, S.; Carrétéro, C.; Garcia, K.; Xavier, S.; et al. Learning through ferroelectric domain dynamics in solid-state synapses. Nat. Commun. 2017, 8, 14736. [Google Scholar] [CrossRef]
  136. Prezioso, M.; Bayat, F.M.; Hoskins, B.; Likharev, K.; Strukov, D. Self-adaptive spike-time-dependent plasticity of metal-oxide memristors. Sci. Rep. 2016, 6, 21331. [Google Scholar] [CrossRef] [PubMed]
  137. Wang, C.; He, W.; Tong, Y.; Zhao, R. Investigation and manipulation of different analog behaviors of memristor as electronic synapse for neuromorphic applications. Sci. Rep. 2016, 6, 22970. [Google Scholar] [CrossRef]
  138. Li, Y.; Zhong, Y.; Zhang, J.; Xu, L.; Wang, Q.; Sun, H.; Tong, H.; Cheng, X.; Miao, X. Activity-dependent synaptic plasticity of a chalcogenide electronic synapse for neuromorphic systems. Sci. Rep. 2014, 4, 4906. [Google Scholar] [CrossRef] [PubMed]
  139. Dongale, T.; Desai, N.; Khot, K.; Volos, C.; Bhosale, P.; Kamat, R. An electronic synapse device based on TiO2 thin film memristor. J. Nanoelectron. Optoelectron. 2018, 13, 68–75. [Google Scholar] [CrossRef]
  140. Camuñas-Mesa, L.A.; Linares-Barranco, B.; Serrano-Gotarredona, T. Neuromorphic spiking neural networks and their memristor-CMOS hardware implementations. Materials 2019, 12, 2745. [Google Scholar] [CrossRef]
  141. Milo, V.; Malavena, G.; Monzio Compagnoni, C.; Ielmini, D. Memristive and CMOS devices for neuromorphic computing. Materials 2020, 13, 166. [Google Scholar] [CrossRef]
  142. Wang, R.; Shi, T.; Zhang, X.; Wang, W.; Wei, J.; Lu, J.; Zhao, X.; Wu, Z.; Cao, R.; Long, S.; et al. Bipolar analog memristors as artificial synapses for neuromorphic computing. Materials 2018, 11, 2102. [Google Scholar] [CrossRef] [PubMed]
  143. Hajtó, D.; Rák, Á.; Cserey, G. Robust memristor networks for neuromorphic computation applications. Materials 2019, 12, 3573. [Google Scholar] [CrossRef] [PubMed]
  144. Pedró, M.; Martín-Martínez, J.; Maestro-Izquierdo, M.; Rodríguez, R.; Nafría, M. Self-organizing neural networks based on OxRAM devices under a fully unsupervised training scheme. Materials 2019, 12, 3482. [Google Scholar] [CrossRef] [PubMed]
  145. Sun, W.; Choi, S.; Kim, B.; Park, J. Three-dimensional (3D) vertical resistive random-access memory (VRRAM) synapses for neural network systems. Materials 2019, 12, 3451. [Google Scholar] [CrossRef] [PubMed]
  146. Cisternas Ferri, A.; Rapoport, A.; Fierens, P.I.; Patterson, G.A.; Miranda, E.; Suñé, J. On the application of a diffusive memristor compact model to neuromorphic circuits. Materials 2019, 12, 2260. [Google Scholar] [CrossRef]
  147. Liu, Z.; Tang, J.; Gao, B.; Li, X.; Yao, P.; Lin, Y.; Liu, D.; Hong, B.; Qian, H.; Wu, H. Multichannel parallel processing of neural signals in memristor arrays. Sci. Adv. 2020, 6, eabc4797. [Google Scholar] [CrossRef]
  148. Yao, P.; Wu, H.; Gao, B.; Tang, J.; Zhang, Q.; Zhang, W.; Yang, J.J.; Qian, H. Fully hardware-implemented memristor convolutional neural network. Nature 2020, 577, 641–646. [Google Scholar] [CrossRef]
  149. Lu, Y.; Alvarez, A.; Kao, C.H.; Bow, J.S.; Chen, S.Y.; Chen, I.W. An electronic silicon-based memristor with a high switching uniformity. Nat. Electron. 2019, 2, 66–74. [Google Scholar] [CrossRef]
  150. Sangwan, V.K.; Lee, H.S.; Bergeron, H.; Balla, I.; Beck, M.E.; Chen, K.S.; Hersam, M.C. Multi-terminal memtransistors from polycrystalline monolayer molybdenum disulfide. Nature 2018, 554, 500–504. [Google Scholar] [CrossRef]
  151. Li, D.; Liang, X. Neurons mimicked by electronics. Nature 2018, 554, 472–473. [Google Scholar] [CrossRef]
  152. Feng, X.; Li, S.; Wong, S.L.; Tong, S.; Chen, L.; Zhang, P.; Wang, L.; Fong, X.; Chi, D.; Ang, K.W. Self-selective multi-terminal memtransistor crossbar array for in-memory computing. ACS Nano 2021, 15, 1764–1774. [Google Scholar] [CrossRef]
  153. Sagar, S.; Udaya Mohanan, K.; Cho, S.; Majewski, L.A.; Das, B.C. Emulation of synaptic functions with low voltage organic memtransistor for hardware oriented neuromorphic computing. Sci. Rep. 2022, 12, 3808. [Google Scholar] [CrossRef] [PubMed]
  154. Wang, L.; Liao, W.; Wong, S.L.; Yu, Z.G.; Li, S.; Lim, Y.F.; Feng, X.; Tan, W.C.; Huang, X.; Chen, L.; et al. Artificial synapses based on multiterminal memtransistors for neuromorphic application. Adv. Funct. Mater. 2019, 29, 1901106. [Google Scholar] [CrossRef]
  155. Yang, Y.; Du, H.; Xue, Q.; Wei, X.; Yang, Z.; Xu, C.; Lin, D.; Jie, W.; Hao, J. Three-terminal memtransistors based on two-dimensional layered gallium selenide nanosheets for potential low-power electronics applications. Nano Energy 2019, 57, 566–573. [Google Scholar] [CrossRef]
  156. Dragoman, M.; Dinescu, A.; Dragoman, D.; Palade, C.; Teodorescu, V.Ş.; Ciurea, M.L. Graphene/Ferroelectric (Ge-Doped HfO2) Adaptable Transistors Acting as Reconfigurable Logic Gates. Nanomaterials 2022, 12, 279. [Google Scholar] [CrossRef] [PubMed]
  157. Dos Santos, S.; Masood, A.; Furui, S.; Nardoni, G. Self-calibration of multiscale hysteresis with memristors in nonlinear time reversal based processes. In Proceedings of the 16th Biennial Baltic Electronics Conference (BEC). IEEE, Tallin, Estonia, 8–10 October 2018; pp. 1–4. [Google Scholar]
  158. Dos Santos, S.; Furui, S. A memristor based ultrasonic transducer: The memosducer. In Proceedings of the IEEE International Ultrasonics Symposium (IUS), Tours, France, 18–21 September 2016; pp. 1–4. [Google Scholar]
  159. Min, K.S.; Corinto, F. Memristor Computing for Neuromorphic Systems. Front. Comput. Neurosci. 2021, 15, 755405. [Google Scholar] [CrossRef] [PubMed]
Figure 1. Examples of some electronic components.
Figure 1. Examples of some electronic components.
Jlpea 12 00044 g001
Figure 2. Symmetrical argument of the memristor as the fourth basic passive circuit element.
Figure 2. Symmetrical argument of the memristor as the fourth basic passive circuit element.
Jlpea 12 00044 g002
Figure 3. Memristor symbol.
Figure 3. Memristor symbol.
Jlpea 12 00044 g003
Figure 4. Memristance expression from a ϕ -q curve. Remark that, due to integration constants, this curve can be shifted horizontally and/or vertically.
Figure 4. Memristance expression from a ϕ -q curve. Remark that, due to integration constants, this curve can be shifted horizontally and/or vertically.
Jlpea 12 00044 g004
Figure 5. Testing memristor device as a black box (left) and current–voltage response of the black box (right).
Figure 5. Testing memristor device as a black box (left) and current–voltage response of the black box (right).
Jlpea 12 00044 g005
Figure 6. Demonstration of a memristor fingerprint for f o = 1 Hz , ω o = 2 π f o and V ( t ) = 1.2 s i n ( ω t ) : ω = ω o , ω = 2 ω o and ω = 10 ω o . (a) voltage V ( t ) and current i ( t ) in a memristor, (b) IV response of a memristor and effect of frequency variation.
Figure 6. Demonstration of a memristor fingerprint for f o = 1 Hz , ω o = 2 π f o and V ( t ) = 1.2 s i n ( ω t ) : ω = ω o , ω = 2 ω o and ω = 10 ω o . (a) voltage V ( t ) and current i ( t ) in a memristor, (b) IV response of a memristor and effect of frequency variation.
Jlpea 12 00044 g006
Figure 7. The two types of pinched hysteresis loop (PHL). (a) Self-crossing or transversal PHL (e.g., the ones observed in HP and KNOWM memristors) and (b) Tangential or non-transversal PHL (e.g., the ones observed in plant and light sources).
Figure 7. The two types of pinched hysteresis loop (PHL). (a) Self-crossing or transversal PHL (e.g., the ones observed in HP and KNOWM memristors) and (b) Tangential or non-transversal PHL (e.g., the ones observed in plant and light sources).
Jlpea 12 00044 g007
Figure 8. Effect of increasing frequency on the PHL lobe area. (a) Hysteresis lobe area shrinkage due to the increase in the input frequency and (b) PHL lobe area versus frequency.
Figure 8. Effect of increasing frequency on the PHL lobe area. (a) Hysteresis lobe area shrinkage due to the increase in the input frequency and (b) PHL lobe area versus frequency.
Jlpea 12 00044 g008
Figure 9. Calculating the area of PHL.
Figure 9. Calculating the area of PHL.
Jlpea 12 00044 g009
Figure 10. Memristor operating point from the constitutive relationship.
Figure 10. Memristor operating point from the constitutive relationship.
Jlpea 12 00044 g010
Figure 11. Memristor subjected to current and voltage excitation, respectively. (a) Charge-controlled memristor, (b) Flux-controlled memristor.
Figure 11. Memristor subjected to current and voltage excitation, respectively. (a) Charge-controlled memristor, (b) Flux-controlled memristor.
Jlpea 12 00044 g011
Figure 12. Results of Example 1: I o = 1 A , f = 4 Hz , α = 1 Wb . C 3 and β = 1 m W b . C 1 . (a1a3) q 0 = 0 C : (a1) ϕ -q curve, (a2) i ( t ) and v ( t ) waveform and (a3) IV characteristic. (b1b3) q 0 = 0.05 C : (b1) ϕ -q curve, (b2) i ( t ) and v ( t ) waveform and (b3) IV characteristic.
Figure 12. Results of Example 1: I o = 1 A , f = 4 Hz , α = 1 Wb . C 3 and β = 1 m W b . C 1 . (a1a3) q 0 = 0 C : (a1) ϕ -q curve, (a2) i ( t ) and v ( t ) waveform and (a3) IV characteristic. (b1b3) q 0 = 0.05 C : (b1) ϕ -q curve, (b2) i ( t ) and v ( t ) waveform and (b3) IV characteristic.
Jlpea 12 00044 g012
Figure 13. Result obtained for Example 2: V 0 = 1 V , f = 4 Hz , ψ 1 = 1 C . W b 3 and ψ 2 = 1 m C . W b 1 . (a1a3) ϕ 0 = 0 W b : (a1) ϕ -q curve, (a2) i ( t ) and v ( t ) waveform and (a3) IV characteristic. (b1b3) ϕ 0 = 0.08 W b : (b1) ϕ -q curve, (b2) i ( t ) and v ( t ) waveform and (b3) IV characteristic.
Figure 13. Result obtained for Example 2: V 0 = 1 V , f = 4 Hz , ψ 1 = 1 C . W b 3 and ψ 2 = 1 m C . W b 1 . (a1a3) ϕ 0 = 0 W b : (a1) ϕ -q curve, (a2) i ( t ) and v ( t ) waveform and (a3) IV characteristic. (b1b3) ϕ 0 = 0.08 W b : (b1) ϕ -q curve, (b2) i ( t ) and v ( t ) waveform and (b3) IV characteristic.
Jlpea 12 00044 g013
Figure 14. Some memristor fabrications technologies.
Figure 14. Some memristor fabrications technologies.
Jlpea 12 00044 g014
Figure 15. Geometry of HP (TiO 2 ) memristor. (a) Crossbar array of wires with memristor in each junction. (b) Structural view of the TiO 2 memristor, i.e., enlargement of the memristor in the junction.
Figure 15. Geometry of HP (TiO 2 ) memristor. (a) Crossbar array of wires with memristor in each junction. (b) Structural view of the TiO 2 memristor, i.e., enlargement of the memristor in the junction.
Jlpea 12 00044 g015
Figure 16. KNOWM memristor chip. The chip contains eight memristors.
Figure 16. KNOWM memristor chip. The chip contains eight memristors.
Jlpea 12 00044 g016
Figure 17. Memristor internal behavioral response. R o n = R o n w ( t ) D , R o f f = R o f f 1 w ( t ) D , V 1 = R o n i ( t ) , V 2 = R o f f i ( t ) and V = V 1 + V 2 .
Figure 17. Memristor internal behavioral response. R o n = R o n w ( t ) D , R o f f = R o f f 1 w ( t ) D , V 1 = R o n i ( t ) , V 2 = R o f f i ( t ) and V = V 1 + V 2 .
Jlpea 12 00044 g017
Figure 18. Window functions comparison. (a) Proposed window function and its comparison with the discussed functions. Joglekar ( p = 1 ) and Prodromakis ( p = 10 ), (b) Comparison of Joglekar and Prodromakis window functions, showing the effect of varying p.
Figure 18. Window functions comparison. (a) Proposed window function and its comparison with the discussed functions. Joglekar ( p = 1 ) and Prodromakis ( p = 10 ), (b) Comparison of Joglekar and Prodromakis window functions, showing the effect of varying p.
Jlpea 12 00044 g018
Figure 19. Comparison of the memristance transition with respect to the flowing charge for the models by Strukov, Joglekar and Prodromakis.
Figure 19. Comparison of the memristance transition with respect to the flowing charge for the models by Strukov, Joglekar and Prodromakis.
Jlpea 12 00044 g019
Figure 20. Memristance transition with respect to the flowing charge for linear and nonlinear dopant drift models. The nonlinear model used the window function by Joglekar and Wolf. When the parameter p increases, the nonlinear model tends to the linear one adapt with permission from ref. [76].
Figure 20. Memristance transition with respect to the flowing charge for linear and nonlinear dopant drift models. The nonlinear model used the window function by Joglekar and Wolf. When the parameter p increases, the nonlinear model tends to the linear one adapt with permission from ref. [76].
Jlpea 12 00044 g020
Figure 21. Analytical results of CCM with Linear model, R o n = 100 Ω , R o f f = 16 K Ω , q d = 100 μ C and three different input frequencies. (a) IV characteristics, (b) state variable and memristance transitions for f = 1 Hz.
Figure 21. Analytical results of CCM with Linear model, R o n = 100 Ω , R o f f = 16 K Ω , q d = 100 μ C and three different input frequencies. (a) IV characteristics, (b) state variable and memristance transitions for f = 1 Hz.
Jlpea 12 00044 g021
Figure 22. Analytical results of FCM with linear dopant drift model: R o n = 100 Ω , R o f f = 16 K Ω , q d = 100 μ C and different input frequencies. (a) IV characteristics, (b) state variable and memristance transitions for f = 1 Hz.
Figure 22. Analytical results of FCM with linear dopant drift model: R o n = 100 Ω , R o f f = 16 K Ω , q d = 100 μ C and different input frequencies. (a) IV characteristics, (b) state variable and memristance transitions for f = 1 Hz.
Jlpea 12 00044 g022
Figure 23. Analytical results of the CCM with nonlinear dopant drift model at different input frequencies. I 0 = 2 mA, x 0 = 0.05 , q d = 100 μ C, R o f f = 16 K Ω , R o n = 100 Ω and δ R = 15.9 K Ω . (a) IV characteristics, (b) state variable and memristance transitions for f = 1 Hz.
Figure 23. Analytical results of the CCM with nonlinear dopant drift model at different input frequencies. I 0 = 2 mA, x 0 = 0.05 , q d = 100 μ C, R o f f = 16 K Ω , R o n = 100 Ω and δ R = 15.9 K Ω . (a) IV characteristics, (b) state variable and memristance transitions for f = 1 Hz.
Jlpea 12 00044 g023
Figure 24. Analytical results of FCM with nonlinear dopant drift modal at different input frequencies. V ( t ) = V 0 s i n ( ω t ) , V 0 = 2 V , x 0 = 0.1 , q d = 100 μ C, R o f f = 16 K Ω , R o n = 100 Ω and δ R = 15.9 K Ω . (a) IV characteristics, (b) state variable and memristance transitions for f = 2 Hz.
Figure 24. Analytical results of FCM with nonlinear dopant drift modal at different input frequencies. V ( t ) = V 0 s i n ( ω t ) , V 0 = 2 V , x 0 = 0.1 , q d = 100 μ C, R o f f = 16 K Ω , R o n = 100 Ω and δ R = 15.9 K Ω . (a) IV characteristics, (b) state variable and memristance transitions for f = 2 Hz.
Jlpea 12 00044 g024
Figure 25. SPICE implementation of TiO 2 memristor model for simulation purposes. (a) Block diagram representation of the memristance function: V = R ( x ) i and d x d t = k f ( x ) i where k = μ v R o n D 2 , (b) Equivalent SPICE model: E is an E-type voltage source (i.e., voltage-controlled voltage source), G is a G-type current source (voltage-dependent current source) and R s h is the shunt resistance of the integrator.
Figure 25. SPICE implementation of TiO 2 memristor model for simulation purposes. (a) Block diagram representation of the memristance function: V = R ( x ) i and d x d t = k f ( x ) i where k = μ v R o n D 2 , (b) Equivalent SPICE model: E is an E-type voltage source (i.e., voltage-controlled voltage source), G is a G-type current source (voltage-dependent current source) and R s h is the shunt resistance of the integrator.
Jlpea 12 00044 g025
Figure 26. Memristor SPICE netlist file.
Figure 26. Memristor SPICE netlist file.
Jlpea 12 00044 g026
Figure 27. Simulation results of the memristor netlist file given in Figure 26. V = V 0 s i n ( ω t ) , V 0 = 1 V , f = 1 Hz, R o n = 100 Ω , R o f f = 16 K Ω , μ v = 10 f m 2 / ( V . s ) and D = 10 nm, which gives q d = 100 μ C. (a) V and i transients, (b) IV characteristic, (c) ϕ -q curve and (d) memristance and state variable transitions.
Figure 27. Simulation results of the memristor netlist file given in Figure 26. V = V 0 s i n ( ω t ) , V 0 = 1 V , f = 1 Hz, R o n = 100 Ω , R o f f = 16 K Ω , μ v = 10 f m 2 / ( V . s ) and D = 10 nm, which gives q d = 100 μ C. (a) V and i transients, (b) IV characteristic, (c) ϕ -q curve and (d) memristance and state variable transitions.
Jlpea 12 00044 g027
Figure 28. Analogue model of memristor adapt with permission from ref. [98].
Figure 28. Analogue model of memristor adapt with permission from ref. [98].
Jlpea 12 00044 g028
Figure 29. Results of the sinusoidal input voltage. Parameters set: R = 1 k Ω , C = 1 μ F, G 0 = 0.5 S and K G = 10 S V 1 (a) V o = 0.6 V and variation of input frequency, ω o = 2 π f o with f o = 1 Hz. (b) memductance for ω o and V o = 0.6 V , (c) at ω o frequency and variation of voltage amplitude V o , (d) the flux ϕ ( t ) for ω o and V o = 0.6 V .
Figure 29. Results of the sinusoidal input voltage. Parameters set: R = 1 k Ω , C = 1 μ F, G 0 = 0.5 S and K G = 10 S V 1 (a) V o = 0.6 V and variation of input frequency, ω o = 2 π f o with f o = 1 Hz. (b) memductance for ω o and V o = 0.6 V , (c) at ω o frequency and variation of voltage amplitude V o , (d) the flux ϕ ( t ) for ω o and V o = 0.6 V .
Jlpea 12 00044 g029
Figure 30. Schematic of a passive memristor emulator adapt with permission from ref. [102].
Figure 30. Schematic of a passive memristor emulator adapt with permission from ref. [102].
Jlpea 12 00044 g030
Figure 31. Comparison of the memristance M ( q ) versus the flowing charge q ( t ) for models (67) and (68), R o f f = 16 K Ω , R o n = 100 Ω and q d = 100 μ C. The first derivative of M ( q ) with respect to q i . e . , d M ( q ) d q for Equation (67) has discontinuity at q ( t ) = 0 and q ( t ) = q d while d M ( q ) d q for Equation (68) is continuous at these q values.
Figure 31. Comparison of the memristance M ( q ) versus the flowing charge q ( t ) for models (67) and (68), R o f f = 16 K Ω , R o n = 100 Ω and q d = 100 μ C. The first derivative of M ( q ) with respect to q i . e . , d M ( q ) d q for Equation (67) has discontinuity at q ( t ) = 0 and q ( t ) = q d while d M ( q ) d q for Equation (68) is continuous at these q values.
Jlpea 12 00044 g031
Figure 32. Characteristics of the memristor model given in Equation (68) by using a sine current input i ( t ) = I 0 s i n ( ω t ) . The result is obtained for R o f f = 16 K Ω , R o n = 100 Ω , I 0 = 1 mA, f = 4 Hz and q d = 100 μ C. (a) ϕ -q curve, (b) current and voltage transients and (c) IV characteristics.
Figure 32. Characteristics of the memristor model given in Equation (68) by using a sine current input i ( t ) = I 0 s i n ( ω t ) . The result is obtained for R o f f = 16 K Ω , R o n = 100 Ω , I 0 = 1 mA, f = 4 Hz and q d = 100 μ C. (a) ϕ -q curve, (b) current and voltage transients and (c) IV characteristics.
Jlpea 12 00044 g032
Figure 33. Classification of some memristor applications according to array and discrete configurations in both analog and digital domains.
Figure 33. Classification of some memristor applications according to array and discrete configurations in both analog and digital domains.
Jlpea 12 00044 g033
Figure 34. Memristor-based 2D Cellular Nonlinear Network with memristors in the coupling mode.
Figure 34. Memristor-based 2D Cellular Nonlinear Network with memristors in the coupling mode.
Jlpea 12 00044 g034
Figure 35. The response of the nonlinear current function and its corresponding potential energy.
Figure 35. The response of the nonlinear current function and its corresponding potential energy.
Jlpea 12 00044 g035
Table 1. Comparison of the three nonlinear dopant drift models.
Table 1. Comparison of the three nonlinear dopant drift models.
Window Function g ( x ) StrukovJoglekarProdromakis
Resolve boundary issues
Impose nonlinear drift
Linkage with linear drift
Control parameter
g m a x scalability
q R value1.3 mC350  μ C150  μ C
Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

Share and Cite

MDPI and ACS Style

Isah, A.; Bilbault, J.-M. Review on the Basic Circuit Elements and Memristor Interpretation: Analysis, Technology and Applications. J. Low Power Electron. Appl. 2022, 12, 44. https://doi.org/10.3390/jlpea12030044

AMA Style

Isah A, Bilbault J-M. Review on the Basic Circuit Elements and Memristor Interpretation: Analysis, Technology and Applications. Journal of Low Power Electronics and Applications. 2022; 12(3):44. https://doi.org/10.3390/jlpea12030044

Chicago/Turabian Style

Isah, Aliyu, and Jean-Marie Bilbault. 2022. "Review on the Basic Circuit Elements and Memristor Interpretation: Analysis, Technology and Applications" Journal of Low Power Electronics and Applications 12, no. 3: 44. https://doi.org/10.3390/jlpea12030044

Note that from the first issue of 2016, this journal uses article numbers instead of page numbers. See further details here.

Article Metrics

Back to TopTop