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Article

A Subthreshold Layout Strategy for Faster and Lower Energy Complex Digital Circuits

1
μ Systems Design Group, Newcastle University, Newcastle upon Tyne NE1 7RU, UK
2
Arm Ltd., Cambridge CB1 9NJ, UK
*
Author to whom correspondence should be addressed.
Academic Editor: Andrea Acquaviva
J. Low Power Electron. Appl. 2022, 12(3), 43; https://doi.org/10.3390/jlpea12030043
Received: 13 May 2022 / Revised: 8 June 2022 / Accepted: 9 July 2022 / Published: 2 August 2022
This work presents complex circuitry from subthreshold standard cell libraries created by geometric STI spacer patterning for bulk planar CMOS technology nodes. Performance/leakage granularity enhancement affords safer multi-Vt synthesis in aggressive voltage scaling schemes. Libraries are evaluated in silicon through implementation of 32-bit datapath 128-bit AES cores. Intra-die nominal temperature (20 °C) analysis reveals improvements of up to 8.65×/24% MEP-to-MEP in frequency and energy-per-cycle respectively, compared to a state-of-the-art subthreshold library. A negative temperature correlation with performance enhancement is demonstrated extending beyond the cell level and into more complex designs. MEP-to-MEP performance enhancement and energy-per-cycle reduction are demonstrated over a temperature range of 0 °C to 85 °C. View Full-Text
Keywords: INWE; RSCE; subthreshold; IoT; bulk planar INWE; RSCE; subthreshold; IoT; bulk planar
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MDPI and ACS Style

Morris, J.; Prabhat, P.; Myers, J.; Yakovlev, A. A Subthreshold Layout Strategy for Faster and Lower Energy Complex Digital Circuits. J. Low Power Electron. Appl. 2022, 12, 43. https://doi.org/10.3390/jlpea12030043

AMA Style

Morris J, Prabhat P, Myers J, Yakovlev A. A Subthreshold Layout Strategy for Faster and Lower Energy Complex Digital Circuits. Journal of Low Power Electronics and Applications. 2022; 12(3):43. https://doi.org/10.3390/jlpea12030043

Chicago/Turabian Style

Morris, Jordan, Pranay Prabhat, James Myers, and Alex Yakovlev. 2022. "A Subthreshold Layout Strategy for Faster and Lower Energy Complex Digital Circuits" Journal of Low Power Electronics and Applications 12, no. 3: 43. https://doi.org/10.3390/jlpea12030043

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