# Review on the Basic Circuit Elements and Memristor Interpretation: Analysis, Technology and Applications

^{1}

^{2}

^{*}

## Abstract

**:**

## 1. Introduction

## 2. The Basic Passive Circuit Elements and Memristor Argumentation

#### 2.1. Resistor

#### 2.2. Capacitor

#### 2.3. Inductor

#### 2.4. Memristor

**Memristor**is claimed to be the fourth basic circuit element [10] (alongside the resistor, capacitor and inductor). It is a nonlinear passive two-terminal electronic component defined by the relationship between the magnetic flux linkage $\varphi $ and the electric charge q. The definition of a memristor is given by its pioneer [21], as: “any 2-terminals device, exhibiting a pinched hysteresis loop which always passes through the origin in the voltage-current plane when driven by any periodic input current source, or voltage source, with zero DC component. If the input is a current source, it is called a current-controlled memristor. If it is a voltage source, it is called a voltage-controlled memristor ”. The name memristor is the contraction of memory resistor owing to its peculiar nature to resist the flow of electric current (as achieved by a resistor) and at the same time to remember the last amount of charge passed through it at the time when the power was disconnected, hence to memorizing the previous device resistance. Memristor keeps track of its dynamic resistance with respect to the current or electric charge flowing through it.

- It has entirely different constitutive relationship in comparison to resistor.
- Its resistance changes according to the quantity of charges having previously passed through it.
- Its resistance changes according to the direction of electric current flowing through it because it is not a bilateral device. Therefore, its connection mode matters.
- It preserves the previous history of electricity, according to the charge passed through it previously, at any given time. In other words, it has memory of the previous electricity passed through it (memory effect).
- It is nonlinear in nature.
- It has pinched hysteresis loop in the voltage–current response in a circuit, depending on its initial condition. Moreover, memristor has different circuit response according to its initial condition.
- It cannot be realized by any combination of the three known circuit elements (capacitor, resistor and inductor) and hence it can be considered as “fundamental”.
- It has a unique nature for the relationship between magnetic flux and electric charge (which is not directly available by measurement).
- It behaves differently in DC and AC conditions.

**Nevertheless**, the memristor and resistor share some similarities, for example:

- Both offer resistance to the flow of electric current.
- Their quantities (i.e., memristance and resistance) have the same unit of measurement, i.e., Ohms, symbol: $\Omega $.
- No phase shift in their voltage and current wave-forms, because $V\left(t\right)=M\left(q\right)i\left(t\right)$⇒$i\left(t\right)=0\phantom{\rule{3.33333pt}{0ex}}\mathrm{if}\phantom{\rule{3.33333pt}{0ex}}V\left(t\right)=0$ and vice versa.
- They both dissipate energy as heat (Joule effect). They are not loss-less devices, i.e., without preservation of energy. They are always associated with power (P) intake, i.e., $P\ge 0$.

## 3. The Memristor Insights and Its Philosophical Arguments

#### 3.1. Fingerprints of a Memristor

- The V-I response of a memristor (with positive memristance) is always a pinched hysteresis loop (Lissajous figure) when subjected to a bipolar periodic input signal without offset.
- The hysteresis lobe area decreases monotonically when the excitation frequency increases.
- For a fixed-input amplitude, the pinched hysteresis loop shrinks to a single-valued function as the frequency of the input supply tends to infinity.

#### 3.1.1. Pinched Hysteresis Loop (PHL)

- i.
**Self-crossing or transversal pinched hysteresis loop (SPHL):**In this type of PHL, the locus cuts across at the origin (or pinched point). Additionally, one can see that the slope of the locus moving toward the origin is different from that of the locus leaving the origin. Figure 7a shows a typical transversal PHL. An example of memristive system with transversal pinched hysteresis loop is the mathematical model of HP memristor (presented in Section 4).- ii.
**Tangential or non-transversal pinched hysteresis loop (TPHL):**As the name implies, the locus does not cut across, rather it passes tangentially as confirmed by the arrow directions, see Figure 7b. Notice that it is still pinched at the origin, i.e., $V\left(t\right)=0$ whenever $i\left(t\right)=0$ and vice versa, however, there is always a fixed slope (for both the two slopes, i.e., ${R}_{off}$ and ${R}_{on}$) when the locus moves toward the origin and immediately after leaving the origin. This observation is clear because the separate line slopes coincide together before reaching the origin and remain together even after leaving the origin until a certain amount of voltage or current is reached, then the loci separate and hence the hysteresis lobe area becomes visible, see Figure 7b.

#### 3.1.2. Pinched Hysteresis Lobe Area

#### 3.2. Memristor by Mode of Excitation

#### 3.2.1. Charge-Controlled Memristor (CCM)

**Example**

**1.**

#### 3.2.2. Flux-Controlled Memristor (FCM)

**Example**

**2.**

#### 3.3. Memory Elements (Mem-Elements)

#### 3.4. Not Every Nonlinear Dynamical System Is an Ideal Memristor

## 4. Memristor Technologies and Models

**bipolar resistance switching**, which means resistance switching between two limits, namely: ${R}_{on}$ and ${R}_{off}$ accomplished by the evolution of the applied signal. ${R}_{on}$ is the lower resistance limit (higher conducting state) while ${R}_{off}$ is the higher resistance limit (lower conducting state). Although the principle of operation is the same, each technology differs from one another in terms of resistance-switching mechanism (see Figure 14).

#### 4.1. HP (TiO${}_{2}$) Memristor: Modeling, Analysis and Interpretation

#### 4.2. Window Function $g\left(x\right)$

- •
- In the boundary limits, x will remain at 0 or 1 until the device has changed its resistance state.
- •
- Joglekar et al. [62] proposed $g\left(x\right)$ to be:$$g\left(x\right)=1-{(2x-1)}^{2p},$$
- •
- Prodromakis et al. [63] proposed $g\left(x\right)$ to be:$$g\left(x\right)=1-{[{(x-0.5)}^{2}+0.75]}^{p},$$$$g\left(x\right)=j\left(1-{[{(x-0.5)}^{2}+0.75]}^{p}\right).$$For a fixed value of parameter p with j varying suitability, $g\left(x\right)$ can be scaled up and down in conformity with: ${g}_{max}\u22db1$.
- •
- Biolek et al. [66] proposed $g\left(x\right)$ to be:$$g\left(x\right)=1-{(x-stp(-i))}^{2p},$$$$stp\left(i\right)=\left\{\begin{array}{c}1\phantom{\rule{3.33333pt}{0ex}}\phantom{\rule{3.33333pt}{0ex}}for\phantom{\rule{3.33333pt}{0ex}}i\ge 0,\hfill \\ 0\phantom{\rule{3.33333pt}{0ex}}\phantom{\rule{3.33333pt}{0ex}}for\phantom{\rule{3.33333pt}{0ex}}i<0.\hfill \end{array}\right.$$The flowing current i is considered as positive when the device is in saturation mode, i.e., $x\to 1$ corresponding to the expansion of the doped layer, and negative if the device is in depletion mode, i.e., $x\to 0$ which corresponds to the contraction of the doped layer. Notice that there is a discontinuity in the boundaries due to the step function definition of the current i.
- •
- Proposed window function:In accordance with the role of window function, we propose $g\left(x\right)$ as derived from Hann window apodisation function as follows:$$g\left(x\right)=\frac{1}{2}\left[1+cos\phantom{\rule{3.33333pt}{0ex}}2\pi \left(\alpha \right(x\left)\right)\right].$$Moreover, to fulfill the continuity constraints for $x=0$ and $x=1$, a sufficient condition stands: $\alpha \left(x\right)=x-\frac{1}{2}$, that is:$$g\left(x\right)=\frac{1}{2}\left[1+cos\phantom{\rule{3.33333pt}{0ex}}\pi (2x-1)\right].$$

#### 4.3. Linear Dopant Drift Model: Analysis

#### 4.3.1. CCM with Linear Dopant Drift Model

#### 4.3.2. FCM with Linear Dopant Drift Model

#### 4.4. Nonlinear Dopant Drift Model: Analysis

#### 4.4.1. CCM with Nonlinear Dopant Drift Model

#### 4.4.2. FCM with Nonlinear Dopant Drift Model

#### 4.4.3. In-Memory Computing

## 5. Spice and Analogue Models of Memristor

**SPICE**is an acronym of

**S**imulation

**P**rogram with

**I**ntegrated

**C**ircuit

**E**mphasis used for simulating and analyzing different circuit functionality. The mathematical description of a given phenomenon can be modeled in SPICE with the aid of its built-in control sources (for example, voltage-controlled voltage source, voltage-controlled current source, behavioral sources, etc.) and other components such as resistors, capacitors, OpAmps. With the discovery of TiO${}_{2}$ memristor, many SPICE models of memristor were proposed mimicking its behavior. The mathematical description of HP TiO${}_{2}$ memristor is used to emulate memristor characteristics, as such many models are reported and some are based on particular applications [92,93,94,95,96,97]. The most commonly used SPICE model is that developed by Biolek et al. [66], whose setup is shown in Figure 25. Figure 25a shows the block diagram representation of the port and state equations of the memristor:

#### 5.1. Analogue Models of Memristor

#### Passive Models of the Memristor Emulator

## 6. Modeling

## 7. Some Potential Applications of Memristor

- •
- It stores information, hence reliable for memory applications.
- •
- It undergoes nano-scalability, hence suitable for modern-day nanotechnology.
- •
- Conductance modulation resembling chemical synapse.
- •
- It has connection flexibility, that is, series-parallel connections, and can form a stack of memory cells for high-density storage applications.
- •
- It is compatible with CMOS technology allowing it to have a massively real-time and parallel computation in hybrid systems due to its reliable adaptability with CMOS neurons.
- •
- It is a nonlinear circuit element, by its nature.
- •
- It has low power consumption. As a nano device, it requires little power to operate.
- •
- One memristor can replace multiple transistors in a circuit, thus it will ensure better performance and more reliable systems.

## 8. Discussion

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## Appendix A. Experimental Results Showing the Typical Voltage-Current Response of the Four Basic Passive Circuit Elements

**Figure A1.**Experimental results of the four fundamental passive circuit elements. (

**a1**–

**a3**) $R=1\mathrm{K}\Omega $, (

**b1**–

**b3**) C = 10 nF, (

**c1**–

**c3**) L = 10 mH and (

**d1**–

**d3**) KNOWM memristor chip (see Figure 16). The current and voltage waveforms for each component are shown along with the corresponding I–V characteristics. There is no phase difference in $V\left(t\right)$ and $I\left(t\right)$ waveforms for R and M, while there is a phase difference of $\frac{\pi}{2}$ for C and L. In the capacitor C, $I\left(t\right)$ is leading the $V\left(t\right)$ by $\frac{\pi}{2}$ and in an inductor L, $V\left(t\right)$ is leading $I\left(t\right)$ by $\frac{\pi}{2}$. The I–V characteristic of R is a linear graph, for C and L it is a circle (respectively with clockwise and anticlockwise) and for M it is a pinched hysteresis loop.

**Scales:**R: time t [0.50 ms/div], current I [0.31 mA/div] and voltage V$[0.50\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}/\mathrm{div}]$, C: time t [0.50 ms/div], current I$[0.28\phantom{\rule{3.33333pt}{0ex}}\mathrm{m}\mathrm{A}/\mathrm{div}]$ and voltage V$[0.50\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}/\mathrm{div}]$, L: time t$[20\phantom{\rule{3.33333pt}{0ex}}\mathrm{\mu}\mathrm{s}/\mathrm{div}]$, current I$[0.31\phantom{\rule{3.33333pt}{0ex}}\mathrm{m}\mathrm{A}/\mathrm{div}]$ and voltage V$[0.50\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}/\mathrm{div}]$ and M: time t$[0.50\phantom{\rule{3.33333pt}{0ex}}\mathrm{m}\mathrm{s}/\mathrm{div}]$, current I$[4.45\phantom{\rule{3.33333pt}{0ex}}\mu \mathrm{A}/\mathrm{div}]$ and voltage V$[1.0\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}/\mathrm{div}]$.

## References

- Xing, R.; Wang, J.; Chen, Q. The Contemporary IT Transformations. Proc. Northeast. Bus. Econ. Assoc.
**2010**, 19, 3–53. [Google Scholar] - Seitz, F. On the trail of the transistor. Nature
**1997**, 388, 339–340. [Google Scholar] [CrossRef] - Stanley Williams, R. How we found the missing memristor. In Chaos, CNN, Memristors and Beyond: A Festschrift for Leon Chua with DVD-ROM, Composed by Eleonora Bilotta; World Scientific: Singapore, 2013; pp. 483–489. [Google Scholar]
- Swingler, J. Reliability Characterisation of Electrical and Electronic Systems; Elsevier: Amsterdam, The Netherlands, 2015. [Google Scholar]
- Lin, D.; Chua, L.; Hui, S.Y. The first human-made memristor: Circa 1801 [scanning our past]. Proc. IEEE
**2014**, 103, 131–136. [Google Scholar] [CrossRef] - Prodromakis, T. Two centuries of memristors. In Chaos, CNN, Memristors and Beyond: A Festschrift for Leon Chua With DVD-ROM, Composed by Eleonora Bilotta; World Scientific: Singapore, 2013; pp. 508–517. [Google Scholar]
- Wuttig, M.; Yamada, N. Phase-change materials for rewriteable data storage. Nat. Mater.
**2007**, 6, 824. [Google Scholar] [CrossRef] [PubMed] - Kato, T.; Tanaka, K. Electronic properties of amorphous and crystalline Ge2Sb2Te5 films. Jpn. J. Appl. Phys.
**2005**, 44, 7340. [Google Scholar] [CrossRef] - Pershin, Y.V.; Di Ventra, M. Memory effects in complex materials and nanoscale systems. Adv. Phys.
**2011**, 60, 145–227. [Google Scholar] [CrossRef] - Chua, L. Memristor-the missing circuit element. IEEE Trans. Circuit Theory
**1971**, 18, 507–519. [Google Scholar] [CrossRef] - Chua, L.O.; Kang, S.M. Memristive devices and systems. Proc. IEEE
**1976**, 64, 209–223. [Google Scholar] [CrossRef] - Strukov, D.B.; Snider, G.S.; Stewart, D.R.; Williams, R.S. The missing memristor found. Nature
**2008**, 453, 80. [Google Scholar] [CrossRef] - Nugent, A. Knowm Memristor Introduction. Available online: https://knowm.org/category/memristor/ (accessed on 15 March 2022).
- Johnsen, G.K. An introduction to the memristor-a valuable circuit element in bioelectricity and bioimpedance. J. Electr. Bioimpedance
**2012**, 3, 20–28. [Google Scholar] [CrossRef] - Irving, M. Smallest 3D Transistors Ever Made Measure a Minuscule 2.5 Nanometers. Available online: https://newatlas.com/smallest-transistors-microfabrication/57583/ (accessed on 15 March 2022).
- Mouttet, B. Memresistors and non-memristive zero-crossing hysteresis curves. arXiv
**2012**, arXiv:1201.2626. [Google Scholar] - Mouttet, B. The Memristor and the Scientific Method. Available online: https://vixra.org/pdf/1205.0004v1.pdf (accessed on 15 March 2022).
- Vongehr, S.; Meng, X. The missing memristor has not been found. Sci. Rep.
**2015**, 5, 11657. [Google Scholar] [CrossRef] [PubMed] - Abraham, I. The case for rejecting the memristor as a fundamental circuit element. Sci. Rep.
**2018**, 8, 10972. [Google Scholar] [CrossRef] [PubMed] - Kothi Mandhana, K. Seminar Report on Memristor. Available online: https://www.researchgate.net/profile/Mangal-Das/publication/277564724_Seminar_Report_on_Memristor/links/556d526a08aeccd7773befc7/Seminar-Report-on-Memristor.pdf?origin=publication_detail (accessed on 15 March 2022).
- Chua, L. Everything you wish to know about memristors but are afraid to ask. Radioengineering
**2015**, 24, 319. [Google Scholar] [CrossRef] - Di Ventra, M.; Pershin, Y.V.; Chua, L.O. Putting memory into circuit elements: Memristors, memcapacitors, and meminductors [point of view]. Proc. IEEE
**2009**, 97, 1371–1372. [Google Scholar] [CrossRef] - Isah, A.; Tchakoutio Nguetcho, A.; Binczak, S.; Bilbault, J. Polarity Reversal Effect of a Memristor From the Circuit Point of View and Insights Into the Memristor Fuse. Front. Comms. Netw.
**2021**, 2, 647528. [Google Scholar] [CrossRef] - Gelencser, A.; Prodromakis, T.; Toumazou, C.; Roska, T. Biomimetic model of the outer plexiform layer by incorporating memristive devices. Phys. Rev. E
**2012**, 85, 041918. [Google Scholar] [CrossRef] - Adhikari, S.P.; Sah, M.P.; Kim, H.; Chua, L.O. Three fingerprints of memristor. IEEE Trans. Circuits Syst. Regul. Pap.
**2013**, 60, 3008–3021. [Google Scholar] [CrossRef] - Biolek, D.; Biolek, Z.; Biolková, V.; Kolka, Z. Some fingerprints of ideal memristors. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS2013), Beijing, China, 19–23 May 2013; pp. 201–204. [Google Scholar]
- Chua, L. If it’s pinched it’sa memristor. Semicond. Sci. Technol.
**2014**, 29, 104001. [Google Scholar] [CrossRef] - Chua, L. Resistance switching memories are memristors. Appl. Phys. A
**2011**, 102, 765–783. [Google Scholar] [CrossRef] - Kim, H.; Sah, M.P.; Adhikari, S.P. Pinched hysteresis loops is the fingerprint of memristive devices. arXiv
**2012**, arXiv:1202.2437. [Google Scholar] - Clauss, D.; Ralich, R.; Ramsier, R. Hysteresis in a light bulb: Connecting electricity and thermodynamics with simple experiments and simulations. Eur. J. Phys.
**2001**, 22, 385. [Google Scholar] [CrossRef] - Markin, V.S.; Volkov, A.G.; Chua, L. An analytical model of memristors in plants. Plant Signal. Behav.
**2014**, 9, e972887. [Google Scholar] [CrossRef] - Biolek, D.; Biolek, Z.; Biolkova, V. Pinched hysteretic loops of ideal memristors, memcapacitors and meminductors must be ‘self-crossing’. Electron. Lett.
**2011**, 47, 1385–1387. [Google Scholar] [CrossRef] - Campbell, K.A. Self-directed channel memristor for high temperature operation. Microelectron. J.
**2017**, 59, 10–14. [Google Scholar] [CrossRef] - Biolek, Z.; Biolek, D.; Biolková, V. Computation of the area of memristor pinched hysteresis loop. IEEE Trans. Circuits Syst. II Express Briefs
**2012**, 59, 607–611. [Google Scholar] [CrossRef] - Biolek, Z.; Biolek, D.; Biolkova, V. Analytical computation of the area of pinched hysteresis loops of ideal mem-elements. Radioengineering
**2013**, 22, 132–135. [Google Scholar] - Biolek, D.; Biolek, Z.; Biolkova, V. Interpreting area of pinched memristor hysteresis loop. Electron. Lett.
**2014**, 50, 74–75. [Google Scholar] [CrossRef] - Di Ventra, M.; Pershin, Y.V.; Chua, L.O. Circuit elements with memory: Memristors, memcapacitors, and meminductors. Proc. IEEE
**2009**, 97, 1717–1724. [Google Scholar] [CrossRef] - Yin, Z.; Tian, H.; Chen, G.; Chua, L.O. What are memristor, memcapacitor, and meminductor? IEEE Trans. Circuits Syst. II Express Briefs
**2015**, 62, 402–406. [Google Scholar] - Chua, L. Memristor and Memristive Systems Symposium; University California: Berkeley, CA, USA, 2008. [Google Scholar]
- Cohen, G.Z.; Pershin, Y.V.; Di Ventra, M. Lagrange formalism of memory circuit elements: Classical and quantum formulations. Phys. Rev. B
**2012**, 85, 165428. [Google Scholar] [CrossRef] - Di Ventra, M.; Pershin, Y.V. Memory materials: A unifying description. Mater. Today
**2011**, 14, 584–591. [Google Scholar] [CrossRef] - Pershin, Y.V.; Martinez-Rincon, J.; Di Ventra, M. Memory circuit elements: From systems to applications. J. Comput. Theor. Nanosci.
**2011**, 8, 441–448. [Google Scholar] [CrossRef] - Pershin, Y.V.; Di Ventra, M. Neuromorphic, digital, and quantum computation with memory circuit elements. Proc. IEEE
**2011**, 100, 2071–2080. [Google Scholar] [CrossRef] - Di Ventra, M.; Pershin, Y.V. Biologically-inspired electronics with memory circuit elements. In Advances in Neuromorphic Memristor Science and Applications; Springer: Berlin/Heidelberg, Germany, 2012; pp. 15–36. [Google Scholar]
- Pershin, Y.V.; Di Ventra, M. Comment on ‘If it’s pinched it’s a memristor’. Semicond. Sci. Technol.
**2019**, 34, 098001. [Google Scholar] [CrossRef] - Kim, J.; Pershin, Y.V.; Yin, M.; Datta, T.; Di Ventra, M. An Experimental Proof that Resistance-Switching Memory Cells are not Memristors. Adv. Electron. Mater.
**2020**, 6, 2000010. [Google Scholar] [CrossRef] - Mouttet, B. Pinched Hysteresis Loops Are a Fingerprint of Square Law Capacitors. Available online: https://vixra.org/pdf/1205.0008v2.pdf (accessed on 15 March 2022).
- Mouttet, B. Response to ‘Pinched Hysteresis Loops is the Fingerprint of Memristive Devices’. Available online: https://vixra.org/pdf/1205.0009v1.pdf (accessed on 15 March 2022).
- Biolek, D.; Biolek, Z.; Biolkova, V.; Ascoli, A.; Tetzlaff, R. About v-i pinched hysteresis of some non-memristive systems. Math. Probl. Eng.
**2018**, 2018. [Google Scholar] [CrossRef] - Pershin, Y.V.; Di Ventra, M. A simple test for ideal memristors. J. Phys. Appl. Phys.
**2018**, 52, 01LT01. [Google Scholar] [CrossRef] - Chanthbouala, A.; Garcia, V.; Cherifi, R.O.; Bouzehouane, K.; Fusil, S.; Moya, X.; Xavier, S.; Yamada, H.; Deranlot, C.; Mathur, N.D.; et al. A ferroelectric memristor. Nat. Mater.
**2012**, 11, 860–864. [Google Scholar] [CrossRef] - Kim, D.; Lu, H.; Ryu, S.; Bark, C.W.; Eom, C.B.; Tsymbal, E.; Gruverman, A. Ferroelectric tunnel memristor. Nano Lett.
**2012**, 12, 5697–5702. [Google Scholar] [CrossRef] - Hu, Z.; Li, Q.; Li, M.; Wang, Q.; Zhu, Y.; Liu, X.; Zhao, X.; Liu, Y.; Dong, S. Ferroelectric memristor based on Pt/BiFeO
_{3}/Nb-doped SrTiO_{3}heterostructure. Appl. Phys. Lett.**2013**, 102, 102901. [Google Scholar] [CrossRef] - Erokhin, V.; Berzina, T.; Fontana, M.P. Hybrid electronic device based on polyaniline-polyethyleneoxide junction. J. Appl. Phys.
**2005**, 97, 064501. [Google Scholar] [CrossRef] - Chen, Y.; Liu, G.; Wang, C.; Zhang, W.; Li, R.W.; Wang, L. Polymer memristor for information storage and neuromorphic applications. Mater. Horizons
**2014**, 1, 489–506. [Google Scholar] [CrossRef] - Wang, X.; Chen, Y.; Xi, H.; Li, H.; Dimitrov, D. Spintronic memristor through spin-torque-induced magnetization motion. IEEE Electron. Device Lett.
**2009**, 30, 294–297. [Google Scholar] [CrossRef] - Pershin, Y.V.; Di Ventra, M. Spin memristive systems: Spin memory effects in semiconductor spintronics. Phys. Rev. B
**2008**, 78, 113309. [Google Scholar] [CrossRef] - Jo, S.H.; Chang, T.; Ebong, I.; Bhadviya, B.B.; Mazumder, P.; Lu, W. Nanoscale memristor device as synapse in neuromorphic systems. Nano Lett.
**2010**, 10, 1297–1301. [Google Scholar] [CrossRef] [PubMed] - Murali, S.; Rajachidambaram, J.S.; Han, S.Y.; Chang, C.H.; Herman, G.S.; Conley, J.F., Jr. Resistive switching in zinc–tin-oxide. Solid-State Electron.
**2013**, 79, 248–252. [Google Scholar] [CrossRef] - Williams, R.S. Finding the Missing Memristor. Available online: https://www.youtube.com/watch?v=bKGhvKyjgLY (accessed on 15 March 2022).
- Hu, X.; Duan, S.; Wang, L.; Liao, X. Memristive crossbar array with applications in image processing. Sci. China Inf. Sci.
**2012**, 55, 461–472. [Google Scholar] [CrossRef] - Joglekar, Y.N.; Wolf, S.J. The elusive memristor: Properties of basic electrical circuits. Eur. J. Phys.
**2009**, 30, 661. [Google Scholar] [CrossRef] - Prodromakis, T.; Peh, B.P.; Papavassiliou, C.; Toumazou, C. A versatile memristor model with nonlinear dopant kinetics. IEEE Trans. Electron Devices
**2011**, 58, 3099–3105. [Google Scholar] [CrossRef] - Slipko, V.A.; Pershin, Y.V. Importance of the window function choice for the predictive modelling of memristors. IEEE Trans. Circuits Syst. II Express Briefs
**2019**, 68, 2167–2171. [Google Scholar] [CrossRef] - Benderli, S.; Wey, T. On SPICE macromodelling of TiO
_{2}memristors. Electron. Lett.**2009**, 45, 377–379. [Google Scholar] [CrossRef] - Biolek, Z.; Biolek, D.; Biolkova, V. SPICE Model of Memristor with Nonlinear Dopant Drift. Radioengineering
**2009**, 18, 210–214. [Google Scholar] - Kvatinsky, S.; Friedman, E.G.; Kolodny, A.; Weiser, U.C. TEAM: Threshold adaptive memristor model. IEEE Trans. Circuits Syst. Regul. Pap.
**2012**, 60, 211–221. [Google Scholar] [CrossRef] - Anusudha, T.; Prabaharan, S. A versatile window function for linear ion drift memristor model—A new approach. AEU-Int. J. Electron. Commun.
**2018**, 90, 130–139. [Google Scholar] [CrossRef] - Kvatinsky, S.; Talisveyberg, K.; Fliter, D.; Kolodny, A.; Weiser, U.C.; Friedman, E.G. Models of memristors for SPICE simulations. In Proceedings of the IEEE 27th Convention of Electrical and Electronics Engineersn, Eilat, Israel, 4–17 November 2012; pp. 1–5. [Google Scholar]
- Yu, J.; Mu, X.; Xi, X.; Wang, S. A memristor model with piecewise window function. Radioengineering
**2013**, 22, 969–974. [Google Scholar] - Takahashi, Y.; Sekine, T.; Yokoyama, M. SPICE model of memristive device using Tukey window function. IEICE Electron. Express
**2015**, 12, 20150149. [Google Scholar] [CrossRef] - Abdel-Kader, R.F.; Abuelenin, S.M. Memristor model based on fuzzy window function. In Proceedings of the IEEE International Conference on Fuzzy Systems (FUZZ-IEEE), Istanbul, Turkey, 2–5 August 2015; pp. 1–5. [Google Scholar]
- Zha, J.; Huang, H.; Liu, Y. A novel window function for memristor model with application in programming analog circuits. IEEE Trans. Circuits Syst. II Express Briefs
**2015**, 63, 423–427. [Google Scholar] [CrossRef] - Singh, J.; Raj, B. An accurate and generic window function for nonlinear memristor models. J. Comput. Electron.
**2019**, 18, 640–647. [Google Scholar] [CrossRef] - Georgiou, P.S.; Yaliraki, S.N.; Drakakis, E.M.; Barahona, M. Window functions and sigmoidal behaviour of memristive systems. Int. J. Circuit Theory Appl.
**2016**, 44, 1685–1696. [Google Scholar] [CrossRef] - Isah, A.; Nguetcho, A.S.T.; Binczak, S.; Bilbault, J.M. Comparison of the Performance of the Memristor Models in 2D Cellular Nonlinear Network. Electronics
**2021**, 10, 1577. [Google Scholar] [CrossRef] - Sun, K.; Chen, J.; Yan, X. The future of memristors: Materials engineering and neural networks. Adv. Funct. Mater.
**2021**, 31, 2006773. [Google Scholar] [CrossRef] - Li, Y.; Wang, Z.; Midya, R.; Xia, Q.; Yang, J.J. Review of memristor devices in neuromorphic computing: Materials sciences and device challenges. J. Phys. Appl. Phys.
**2018**, 51, 503002. [Google Scholar] [CrossRef] - Zidan, M.A.; Strachan, J.P.; Lu, W.D. The future of electronics based on memristive systems. Nat. Electron.
**2018**, 1, 22–29. [Google Scholar] [CrossRef] - Zhang, X.; Lu, J.; Wang, Z.; Wang, R.; Wei, J.; Shi, T.; Dou, C.; Wu, Z.; Zhu, J.; Shang, D.; et al. Hybrid memristor-CMOS neurons for in situ learning in fully hardware memristive spiking neural networks. Sci. Bull.
**2021**, 66, 1624–1633. [Google Scholar] [CrossRef] - Lee, Y.; Lee, T.W. Organic synapses for neuromorphic electronics: From brain-inspired computing to sensorimotor nervetronics. Acc. Chem. Res.
**2019**, 52, 964–974. [Google Scholar] [CrossRef] - Miranda, E.; Suñé, J. Memristors for neuromorphic circuits and artificial intelligence applications. Materials
**2020**, 13, 938. [Google Scholar] [CrossRef] [PubMed] - Hu, M.; Graves, C.E.; Li, C.; Li, Y.; Ge, N.; Montgomery, E.; Davila, N.; Jiang, H.; Williams, R.S.; Yang, J.J.; et al. Memristor-based analog computation and neural network classification with a dot product engine. Adv. Mater.
**2018**, 30, 1705914. [Google Scholar] [CrossRef] - Prezioso, M.; Merrikh-Bayat, F.; Hoskins, B.; Adam, G.C.; Likharev, K.K.; Strukov, D.B. Training and operation of an integrated neuromorphic network based on metal-oxide memristors. Nature
**2015**, 521, 61–64. [Google Scholar] [CrossRef] - Wang, Z.; Wu, H.; Burr, G.W.; Hwang, C.S.; Wang, K.L.; Xia, Q.; Yang, J.J. Resistive switching materials for information processing. Nat. Rev. Mater.
**2020**, 5, 173–195. [Google Scholar] [CrossRef] - Ielmini, D.; Wong, H.S.P. In-memory computing with resistive switching devices. Nat. Electron.
**2018**, 1, 333–343. [Google Scholar] [CrossRef] - Sebastian, A.; Le Gallo, M.; Khaddam-Aljameh, R.; Eleftheriou, E. Memory devices and applications for in-memory computing. Nat. Nanotechnol.
**2020**, 15, 529–544. [Google Scholar] [CrossRef] [PubMed] - Cheng, L.; Li, J.; Zheng, H.X.; Yuan, P.; Yin, J.; Yang, L.; Luo, Q.; Li, Y.; Lv, H.; Chang, T.C.; et al. In-Memory Hamming Weight Calculation in a 1T1R Memristive Array. Adv. Electron. Mater.
**2020**, 6, 2000457. [Google Scholar] [CrossRef] - Lin, H.; Wu, Z.; Liu, L.; Wang, D.; Zhao, X.; Cheng, L.; Lin, Y.; Wang, Z.; Xu, X.; Xu, H.; et al. Implementation of Highly Reliable and Energy Efficient in-Memory Hamming Distance Computations in 1 Kb 1-Transistor-1-Memristor Arrays. Adv. Mater. Technol.
**2021**, 6, 2100745. [Google Scholar] [CrossRef] - Lalchhandama, F.; Datta, K.; Chakraborty, S.; Drechsler, R.; Sengupta, I. CoMIC: Complementary Memristor based in-memory computing in 3D architecture. J. Syst. Archit.
**2022**, 126, 102480. [Google Scholar] [CrossRef] - Mehonic, A.; Sebastian, A.; Rajendran, B.; Simeone, O.; Vasilaki, E.; Kenyon, A.J. Memristors—From In-Memory Computing, Deep Learning Acceleration, and Spiking Neural Networks to the Future of Neuromorphic and Bio-Inspired Computing. Adv. Intell. Syst.
**2020**, 2, 2000085. [Google Scholar] [CrossRef] - Pershin, Y.V.; Di Ventra, M. SPICE model of memristive devices with threshold. arXiv
**2012**, arXiv:1204.2600. [Google Scholar] - Kvatinsky, S.; Ramadan, M.; Friedman, E.G.; Kolodny, A. VTEAM: A general model for voltage-controlled memristors. IEEE Trans. Circuits Syst. II Express Briefs
**2015**, 62, 786–790. [Google Scholar] [CrossRef] - Kvatinsky, S.; Talisveyberg, K.; Fliter, D.; Friedman, E.G.; Kolodny, A.; Weiser, U.C. Verilog-A for Memristor Models. Available online: https://asic2.group/wp-content/uploads/2017/06/VerilogA-models-technical-report.pdf (accessed on 15 March 2022).
- Biolek, D.; Biolek, Z.; Biolkova, V. SPICE modeling of memristive, memcapacitative and meminductive systems. In Proceedings of the European Conference on Circuit Theory and Design, Antalya, Turkey, 23–27 August 2009; pp. 249–252. [Google Scholar]
- Radwan, A.G.; Zidan, M.A.; Salama, K. HP memristor mathematical model for periodic signals and DC. In Proceedings of the 53rd IEEE International Midwest Symposium on Circuits and Systems, Washington, DC, USA, 1–4 August 2010; pp. 861–864. [Google Scholar]
- Rák, Á.; Cserey, G. Macromodeling of the memristor in SPICE. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
**2010**, 29, 632–636. [Google Scholar] [CrossRef] - Valsa, J.; Biolek, D.; Biolek, Z. An analogue model of the memristor. Int. J. Numer. Model. Electron. Netw. Devices Fields
**2011**, 24, 400–408. [Google Scholar] [CrossRef] - Sánchez-López, C.; Mendoza-Lopez, J.; Carrasco-Aguilar, M.; Muñiz-Montero, C. A floating analog memristor emulator circuit. IEEE Trans. Circuits Syst. II Express Briefs
**2014**, 61, 309–313. [Google Scholar] - Xiao-Yuan, W.; Fitch, A.L.; Iu, H.H.; Sreeram, V.; Wei-Gui, Q. Implementation of an analogue model of a memristor based on a light-dependent resistor. Chin. Phys. B
**2012**, 21, 108501. [Google Scholar] - Muthuswamy, B. Implementing memristor based chaotic circuits. Int. J. Bifurc. Chaos
**2010**, 20, 1335–1350. [Google Scholar] [CrossRef] - Biolek, D.; Biolkova, V.; Kolka, Z.; Biolek, Z. Passive fully floating emulator of memristive device for laboratory experiments. Adv. Electr. Comput. Eng.
**2015**, 1, 112–116. [Google Scholar] - Kim, H.; Sah, M.P.; Yang, C.; Cho, S.; Chua, L.O. Memristor emulator for memristor circuit applications. IEEE Trans. Circuits Syst. Regul. Pap.
**2012**, 59, 2422–2431. [Google Scholar] - Bodo, B.; Fouda, J.A.E.; Mvogo, A.; Tagne, S. Experimental hysteresis in memristor based Duffing oscillator. Chaos Solitons Fractals
**2018**, 115, 190–195. [Google Scholar] [CrossRef] - Fouda, J.A.E.; Bodo, B.; Djeufa, G.M.; Sabat, S.L. Experimental chaos detection in the Duffing oscillator. Commun. Nonlinear Sci. Numer. Simul.
**2016**, 33, 259–269. [Google Scholar] [CrossRef] - Isah, A.; Nguetcho, A.S.T.; Binczak, S.; Bilbault, J.M. Memristor dynamics involved in cells communication for a 2D non-linear network. IET Signal Process.
**2020**, 14, 427–434. [Google Scholar] [CrossRef] - Isah, A.; Nguetcho, A.T.; Binczak, S.; Bilbault, J. Dynamics of a charge-controlled memristor in master–slave coupling. Electron. Lett.
**2020**, 56, 211–213. [Google Scholar] [CrossRef] - Adam, G.C.; Hoskins, B.D.; Prezioso, M.; Merrikh-Bayat, F.; Chakrabarti, B.; Strukov, D.B. 3-D memristor crossbars for analog and neuromorphic computing applications. IEEE Trans. Electron. Devices
**2016**, 64, 312–318. [Google Scholar] [CrossRef] - Wang, Z.; Joshi, S.; Savel’ev, S.E.; Jiang, H.; Midya, R.; Lin, P.; Hu, M.; Ge, N.; Strachan, J.P.; Li, Z.; et al. Memristors with diffusive dynamics as synaptic emulators for neuromorphic computing. Nat. Mater.
**2017**, 16, 101–108. [Google Scholar] [CrossRef] [PubMed] - Kim, K.H.; Gaba, S.; Wheeler, D.; Cruz-Albrecht, J.M.; Hussain, T.; Srinivasa, N.; Lu, W. A functional hybrid memristor crossbar-array/CMOS system for data storage and neuromorphic applications. Nano Lett.
**2012**, 12, 389–395. [Google Scholar] [CrossRef] [PubMed] - Gaba, S.; Sheridan, P.; Zhou, J.; Choi, S.; Lu, W. Stochastic memristive devices for computing and neuromorphic applications. Nanoscale
**2013**, 5, 5872–5878. [Google Scholar] [CrossRef] [PubMed] - Mazumder, P.; Kang, S.M.; Waser, R. Memristors: Devices, models, and applications. Proc. IEEE
**2012**, 100, 1911–1919. [Google Scholar] [CrossRef] - Prodromakis, T.; Toumazou, C. A review on memristive devices and applications. In Proceedings of the 17th IEEE International Conference on Electronics, Circuits and Systems, Athens, Greece, 12–15 December 2010; pp. 934–937. [Google Scholar]
- Marani, R.; Gelao, G.; Perri, A.G. A review on memristor applications. arXiv
**2015**, arXiv:1506.06899. [Google Scholar] - Eshraghian, K.; Cho, K.R.; Kavehei, O.; Kang, S.K.; Abbott, D.; Kang, S.M.S. Memristor MOS content addressable memory (MCAM): Hybrid architecture for future high performance search engines. IEEE Trans. Very Large Scale Integr. (VLSI) Syst.
**2010**, 19, 1407–1417. [Google Scholar] [CrossRef] - Hu, S.; Wu, S.; Jia, W.; Yu, Q.; Deng, L.; Fu, Y.Q.; Liu, Y.; Chen, T.P. Review of nanostructured resistive switching memristor and its applications. Nanosci. Nanotechnol. Lett.
**2014**, 6, 729–757. [Google Scholar] [CrossRef] - Hamdioui, S.; Xie, L.; Du Nguyen, H.A.; Taouil, M.; Bertels, K.; Corporaal, H.; Jiao, H.; Catthoor, F.; Wouters, D.; Eike, L.; et al. Memristor based computation-in-memory architecture for data-intensive applications. In Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, Grenoble, France, 9–13 March 2015; pp. 1718–1725. [Google Scholar]
- Duan, S.; Hu, X.; Wang, L.; Li, C.; Mazumder, P. Memristor-based RRAM with applications. Sci. China Inf. Sci.
**2012**, 55, 1446–1460. [Google Scholar] [CrossRef] - Xu, Y.M.; Wang, L.D.; Duan, S.K. A memristor-based chaotic system and its field programmable gate array implementation. Acta Phys. Sin.
**2016**, 65, 120503. [Google Scholar] - Pershin, Y.V.; Di Ventra, M. Practical approach to programmable analog circuits with memristors. IEEE Trans. Circuits Syst. Regul. Pap.
**2010**, 57, 1857–1864. [Google Scholar] [CrossRef] - Shin, S.; Kim, K.; Kang, S.M. Memristor applications for programmable analog ICs. IEEE Trans. Nanotechnol.
**2010**, 10, 266–274. [Google Scholar] [CrossRef] - Borghetti, J.; Snider, G.S.; Kuekes, P.J.; Yang, J.J.; Stewart, D.R.; Williams, R.S. ‘Memristive’ switches enable ‘stateful’ logic operations via material implication. Nature
**2010**, 464, 873–876. [Google Scholar] [CrossRef] - Göknar, İ.C.; Öncül, F.; Minayi, E. New memristor applications: AM, ASK, FSK, and BPSK modulators. IEEE Antennas Propag. Mag.
**2013**, 55, 304–313. [Google Scholar] [CrossRef] - Hutchinson, J.; Koch, C.; Luo, J.; Mead, C. Computing motion using analog and binary resistive networks. Computer
**1988**, 21, 52–63. [Google Scholar] [CrossRef] - Linares-Barranco, B.; Serrano-Gotarredona, T. Memristance can explain spike-time-dependent-plasticity in neural synapses. Nat. Preced.
**2009**. [Google Scholar] [CrossRef] - Chu, M.; Kim, B.; Park, S.; Hwang, H.; Jeon, M.; Lee, B.H.; Lee, B.G. Neuromorphic hardware system for visual pattern recognition with memristor array and CMOS neuron. IEEE Trans. Ind. Electron.
**2014**, 62, 2410–2419. [Google Scholar] [CrossRef] - Snider, G.S. Spike-timing-dependent learning in memristive nanodevices. In Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, Anaheim, CA, USA, 12–13 June 2008; pp. 85–92. [Google Scholar]
- Yakopcic, C.; Hasan, R.; Taha, T.M. Flexible memristor based neuromorphic system for implementing multi-layer neural network algorithms. Int. J. Parallel Emergent Distrib. Syst.
**2018**, 33, 408–429. [Google Scholar] [CrossRef] - Duan, S.; Hu, X.; Dong, Z.; Wang, L.; Mazumder, P. Memristor-based cellular nonlinear/neural network: Design, analysis, and applications. IEEE Trans. Neural Netw. Learn. Syst.
**2014**, 26, 1202–1213. [Google Scholar] [CrossRef] - Thomas, A. Memristor-based neural networks. J. Phys. Appl. Phys.
**2013**, 46, 093001. [Google Scholar] [CrossRef] - Adhikari, S.P.; Yang, C.; Kim, H.; Chua, L.O. Memristor bridge synapse-based neural network and its learning. IEEE Trans. Neural Netw. Learn. Syst.
**2012**, 23, 1426–1435. [Google Scholar] [CrossRef] - Kim, H.; Sah, M.P.; Yang, C.; Roska, T.; Chua, L.O. Memristor bridge synapses. Proc. IEEE
**2011**, 100, 2061–2070. [Google Scholar] [CrossRef] - Saïghi, S.; Mayr, C.G.; Serrano-Gotarredona, T.; Schmidt, H.; Lecerf, G.; Tomas, J.; Grollier, J.; Boyn, S.; Vincent, A.F.; Querlioz, D.; et al. Plasticity in memristive devices for spiking neural networks. Front. Neurosci.
**2015**, 9, 51. [Google Scholar] [CrossRef] - Lecerf, G.; Tomas, J.; Boyn, S.; Girod, S.; Mangalore, A.; Grollier, J.; Saïghi, S. Silicon neuron dedicated to memristive spiking neural networks. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), Melbourne, Australia, 1–5 June 2014; pp. 1568–1571. [Google Scholar]
- Boyn, S.; Grollier, J.; Lecerf, G.; Xu, B.; Locatelli, N.; Fusil, S.; Girod, S.; Carrétéro, C.; Garcia, K.; Xavier, S.; et al. Learning through ferroelectric domain dynamics in solid-state synapses. Nat. Commun.
**2017**, 8, 14736. [Google Scholar] [CrossRef] - Prezioso, M.; Bayat, F.M.; Hoskins, B.; Likharev, K.; Strukov, D. Self-adaptive spike-time-dependent plasticity of metal-oxide memristors. Sci. Rep.
**2016**, 6, 21331. [Google Scholar] [CrossRef] [PubMed] - Wang, C.; He, W.; Tong, Y.; Zhao, R. Investigation and manipulation of different analog behaviors of memristor as electronic synapse for neuromorphic applications. Sci. Rep.
**2016**, 6, 22970. [Google Scholar] [CrossRef] - Li, Y.; Zhong, Y.; Zhang, J.; Xu, L.; Wang, Q.; Sun, H.; Tong, H.; Cheng, X.; Miao, X. Activity-dependent synaptic plasticity of a chalcogenide electronic synapse for neuromorphic systems. Sci. Rep.
**2014**, 4, 4906. [Google Scholar] [CrossRef] [PubMed] - Dongale, T.; Desai, N.; Khot, K.; Volos, C.; Bhosale, P.; Kamat, R. An electronic synapse device based on TiO2 thin film memristor. J. Nanoelectron. Optoelectron.
**2018**, 13, 68–75. [Google Scholar] [CrossRef] - Camuñas-Mesa, L.A.; Linares-Barranco, B.; Serrano-Gotarredona, T. Neuromorphic spiking neural networks and their memristor-CMOS hardware implementations. Materials
**2019**, 12, 2745. [Google Scholar] [CrossRef] - Milo, V.; Malavena, G.; Monzio Compagnoni, C.; Ielmini, D. Memristive and CMOS devices for neuromorphic computing. Materials
**2020**, 13, 166. [Google Scholar] [CrossRef] - Wang, R.; Shi, T.; Zhang, X.; Wang, W.; Wei, J.; Lu, J.; Zhao, X.; Wu, Z.; Cao, R.; Long, S.; et al. Bipolar analog memristors as artificial synapses for neuromorphic computing. Materials
**2018**, 11, 2102. [Google Scholar] [CrossRef] [PubMed] - Hajtó, D.; Rák, Á.; Cserey, G. Robust memristor networks for neuromorphic computation applications. Materials
**2019**, 12, 3573. [Google Scholar] [CrossRef] [PubMed] - Pedró, M.; Martín-Martínez, J.; Maestro-Izquierdo, M.; Rodríguez, R.; Nafría, M. Self-organizing neural networks based on OxRAM devices under a fully unsupervised training scheme. Materials
**2019**, 12, 3482. [Google Scholar] [CrossRef] [PubMed] - Sun, W.; Choi, S.; Kim, B.; Park, J. Three-dimensional (3D) vertical resistive random-access memory (VRRAM) synapses for neural network systems. Materials
**2019**, 12, 3451. [Google Scholar] [CrossRef] [PubMed] - Cisternas Ferri, A.; Rapoport, A.; Fierens, P.I.; Patterson, G.A.; Miranda, E.; Suñé, J. On the application of a diffusive memristor compact model to neuromorphic circuits. Materials
**2019**, 12, 2260. [Google Scholar] [CrossRef] - Liu, Z.; Tang, J.; Gao, B.; Li, X.; Yao, P.; Lin, Y.; Liu, D.; Hong, B.; Qian, H.; Wu, H. Multichannel parallel processing of neural signals in memristor arrays. Sci. Adv.
**2020**, 6, eabc4797. [Google Scholar] [CrossRef] - Yao, P.; Wu, H.; Gao, B.; Tang, J.; Zhang, Q.; Zhang, W.; Yang, J.J.; Qian, H. Fully hardware-implemented memristor convolutional neural network. Nature
**2020**, 577, 641–646. [Google Scholar] [CrossRef] - Lu, Y.; Alvarez, A.; Kao, C.H.; Bow, J.S.; Chen, S.Y.; Chen, I.W. An electronic silicon-based memristor with a high switching uniformity. Nat. Electron.
**2019**, 2, 66–74. [Google Scholar] [CrossRef] - Sangwan, V.K.; Lee, H.S.; Bergeron, H.; Balla, I.; Beck, M.E.; Chen, K.S.; Hersam, M.C. Multi-terminal memtransistors from polycrystalline monolayer molybdenum disulfide. Nature
**2018**, 554, 500–504. [Google Scholar] [CrossRef] - Li, D.; Liang, X. Neurons mimicked by electronics. Nature
**2018**, 554, 472–473. [Google Scholar] [CrossRef] - Feng, X.; Li, S.; Wong, S.L.; Tong, S.; Chen, L.; Zhang, P.; Wang, L.; Fong, X.; Chi, D.; Ang, K.W. Self-selective multi-terminal memtransistor crossbar array for in-memory computing. ACS Nano
**2021**, 15, 1764–1774. [Google Scholar] [CrossRef] - Sagar, S.; Udaya Mohanan, K.; Cho, S.; Majewski, L.A.; Das, B.C. Emulation of synaptic functions with low voltage organic memtransistor for hardware oriented neuromorphic computing. Sci. Rep.
**2022**, 12, 3808. [Google Scholar] [CrossRef] [PubMed] - Wang, L.; Liao, W.; Wong, S.L.; Yu, Z.G.; Li, S.; Lim, Y.F.; Feng, X.; Tan, W.C.; Huang, X.; Chen, L.; et al. Artificial synapses based on multiterminal memtransistors for neuromorphic application. Adv. Funct. Mater.
**2019**, 29, 1901106. [Google Scholar] [CrossRef] - Yang, Y.; Du, H.; Xue, Q.; Wei, X.; Yang, Z.; Xu, C.; Lin, D.; Jie, W.; Hao, J. Three-terminal memtransistors based on two-dimensional layered gallium selenide nanosheets for potential low-power electronics applications. Nano Energy
**2019**, 57, 566–573. [Google Scholar] [CrossRef] - Dragoman, M.; Dinescu, A.; Dragoman, D.; Palade, C.; Teodorescu, V.Ş.; Ciurea, M.L. Graphene/Ferroelectric (Ge-Doped HfO2) Adaptable Transistors Acting as Reconfigurable Logic Gates. Nanomaterials
**2022**, 12, 279. [Google Scholar] [CrossRef] [PubMed] - Dos Santos, S.; Masood, A.; Furui, S.; Nardoni, G. Self-calibration of multiscale hysteresis with memristors in nonlinear time reversal based processes. In Proceedings of the 16th Biennial Baltic Electronics Conference (BEC). IEEE, Tallin, Estonia, 8–10 October 2018; pp. 1–4. [Google Scholar]
- Dos Santos, S.; Furui, S. A memristor based ultrasonic transducer: The memosducer. In Proceedings of the IEEE International Ultrasonics Symposium (IUS), Tours, France, 18–21 September 2016; pp. 1–4. [Google Scholar]
- Min, K.S.; Corinto, F. Memristor Computing for Neuromorphic Systems. Front. Comput. Neurosci.
**2021**, 15, 755405. [Google Scholar] [CrossRef] [PubMed]

**Figure 4.**Memristance expression from a $\varphi $-q curve. Remark that, due to integration constants, this curve can be shifted horizontally and/or vertically.

**Figure 5.**Testing memristor device as a black box (

**left**) and current–voltage response of the black box (

**right**).

**Figure 6.**Demonstration of a memristor fingerprint for ${f}_{o}=1\phantom{\rule{3.33333pt}{0ex}}\mathrm{Hz}$, ${\omega}_{o}=2\phantom{\rule{3.33333pt}{0ex}}\pi {f}_{o}$ and $V\left(t\right)=1.2\phantom{\rule{3.33333pt}{0ex}}sin\left(\omega t\right)$: $\omega ={\omega}_{o}$, $\omega =2\phantom{\rule{3.33333pt}{0ex}}{\omega}_{o}$ and $\omega =10\phantom{\rule{3.33333pt}{0ex}}{\omega}_{o}$. (

**a**) voltage $V\left(t\right)$ and current $i\left(t\right)$ in a memristor, (

**b**) I–V response of a memristor and effect of frequency variation.

**Figure 7.**The two types of pinched hysteresis loop (PHL). (

**a**) Self-crossing or transversal PHL (e.g., the ones observed in HP and KNOWM memristors) and (

**b**) Tangential or non-transversal PHL (e.g., the ones observed in plant and light sources).

**Figure 8.**Effect of increasing frequency on the PHL lobe area. (

**a**) Hysteresis lobe area shrinkage due to the increase in the input frequency and (

**b**) PHL lobe area versus frequency.

**Figure 11.**Memristor subjected to current and voltage excitation, respectively. (

**a**) Charge-controlled memristor, (

**b**) Flux-controlled memristor.

**Figure 12.**Results of Example 1: ${I}_{o}=1\mathrm{A}$, $f=4\phantom{\rule{3.33333pt}{0ex}}\mathrm{Hz}$, $\alpha =1\phantom{\rule{3.33333pt}{0ex}}\mathrm{Wb}.{\mathrm{C}}^{-3}$ and $\phantom{\rule{3.33333pt}{0ex}}\beta =1\phantom{\rule{3.33333pt}{0ex}}\mathrm{m}\mathrm{W}\mathrm{b}.{\mathrm{C}}^{-1}$. (

**a1**–

**a3**) ${q}_{0}=0\phantom{\rule{3.33333pt}{0ex}}\mathrm{C}$: (

**a1**) $\varphi $-q curve, (

**a2**) $i\left(t\right)$ and $v\left(t\right)$ waveform and (

**a3**) I–V characteristic. (

**b1**–

**b3**) ${q}_{0}=0.05\phantom{\rule{3.33333pt}{0ex}}\mathrm{C}$: (

**b1**) $\varphi $-q curve, (

**b2**) $i\left(t\right)$ and $v\left(t\right)$ waveform and (

**b3**) I–V characteristic.

**Figure 13.**Result obtained for Example 2: ${V}_{0}=1\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}$,$f=4\phantom{\rule{3.33333pt}{0ex}}\mathrm{Hz}$, $\phantom{\rule{3.33333pt}{0ex}}{\psi}_{1}=1\phantom{\rule{3.33333pt}{0ex}}\mathrm{C}.\mathrm{W}{\mathrm{b}}^{-3}$ and ${\psi}_{2}=1\phantom{\rule{3.33333pt}{0ex}}\mathrm{m}\mathrm{C}.\mathrm{W}{\mathrm{b}}^{-1}$. (

**a1**–

**a3**) ${\varphi}_{0}=0\phantom{\rule{3.33333pt}{0ex}}\mathrm{W}\mathrm{b}$: (

**a1**) $\varphi $-q curve, (

**a2**) $i\left(t\right)$ and $v\left(t\right)$ waveform and (

**a3**) I–V characteristic. (

**b1**–

**b3**) ${\varphi}_{0}=0.08\phantom{\rule{3.33333pt}{0ex}}\mathrm{W}\mathrm{b}$: (

**b1**) $\varphi $-q curve, (

**b2**) $i\left(t\right)$ and $v\left(t\right)$ waveform and (

**b3**) I–V characteristic.

**Figure 15.**Geometry of HP (TiO${}_{2}$) memristor. (

**a**) Crossbar array of wires with memristor in each junction. (

**b**) Structural view of the TiO${}_{2}$ memristor, i.e., enlargement of the memristor in the junction.

**Figure 17.**Memristor internal behavioral response. $R}_{on}^{\prime}={R}_{on}\frac{w\left(t\right)}{D$, ${R}_{off}^{\prime}={R}_{off}\left(1-\frac{w\left(t\right)}{D}\right)$, ${V}_{1}={R}_{on}^{\prime}i\left(t\right)$, ${V}_{2}={R}_{off}^{\prime}i\left(t\right)$ and $V={V}_{1}+{V}_{2}$.

**Figure 18.**Window functions comparison. (

**a**) Proposed window function and its comparison with the discussed functions. Joglekar ($p=1$) and Prodromakis ($p=10$), (

**b**) Comparison of Joglekar and Prodromakis window functions, showing the effect of varying p.

**Figure 19.**Comparison of the memristance transition with respect to the flowing charge for the models by Strukov, Joglekar and Prodromakis.

**Figure 20.**Memristance transition with respect to the flowing charge for linear and nonlinear dopant drift models. The nonlinear model used the window function by Joglekar and Wolf. When the parameter p increases, the nonlinear model tends to the linear one adapt with permission from ref. [76].

**Figure 21.**Analytical results of CCM with Linear model, ${R}_{on}=100\phantom{\rule{3.33333pt}{0ex}}\Omega $, ${R}_{off}=16$ K$\Omega $, ${q}_{d}=100\phantom{\rule{3.33333pt}{0ex}}\mathsf{\mu}$C and three different input frequencies. (

**a**) I–V characteristics, (

**b**) state variable and memristance transitions for f = 1 Hz.

**Figure 22.**Analytical results of FCM with linear dopant drift model: ${R}_{on}=100\phantom{\rule{3.33333pt}{0ex}}\Omega $, ${R}_{off}=16$ K$\Omega $, ${q}_{d}=100\phantom{\rule{3.33333pt}{0ex}}\mathsf{\mu}$C and different input frequencies. (

**a**) I–V characteristics, (

**b**) state variable and memristance transitions for f = 1 Hz.

**Figure 23.**Analytical results of the CCM with nonlinear dopant drift model at different input frequencies. ${I}_{0}=2$ mA, ${x}_{0}=0.05$, ${q}_{d}=100\phantom{\rule{3.33333pt}{0ex}}\mathsf{\mu}$C, ${R}_{off}=16$ K$\Omega $, ${R}_{on}=100\phantom{\rule{3.33333pt}{0ex}}\Omega $ and $\delta R=15.9$ K$\Omega $. (

**a**) I–V characteristics, (

**b**) state variable and memristance transitions for f = 1 Hz.

**Figure 24.**Analytical results of FCM with nonlinear dopant drift modal at different input frequencies. $V\left(t\right)={V}_{0}sin\left(\omega t\right)$, ${V}_{0}=2\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}$, ${x}_{0}=0.1$, ${q}_{d}=100\phantom{\rule{3.33333pt}{0ex}}\mathsf{\mu}$C, ${R}_{off}=16$ K$\Omega $, ${R}_{on}=100$$\Omega $ and $\delta R=15.9$ K$\Omega $. (

**a**) I–V characteristics, (

**b**) state variable and memristance transitions for f = 2 Hz.

**Figure 25.**SPICE implementation of TiO${}_{2}$ memristor model for simulation purposes. (

**a**) Block diagram representation of the memristance function: $V=R\left(x\right)i$ and $\frac{dx}{dt}=kf\left(x\right)i$ where $k=\frac{{\mu}_{v}{R}_{on}}{{D}^{2}}$, (

**b**) Equivalent SPICE model: E is an E-type voltage source (i.e., voltage-controlled voltage source), G is a G-type current source (voltage-dependent current source) and ${R}_{sh}$ is the shunt resistance of the integrator.

**Figure 27.**Simulation results of the memristor netlist file given in Figure 26. $V={V}_{0}sin\left(\omega t\right)$, ${V}_{0}=1\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}$, f = 1 Hz, ${R}_{on}=100\phantom{\rule{3.33333pt}{0ex}}\Omega $, ${R}_{off}=16\phantom{\rule{3.33333pt}{0ex}}\mathrm{K}\Omega $, ${\mu}_{v}=10\phantom{\rule{3.33333pt}{0ex}}\mathrm{f}{\mathrm{m}}^{2}/(\mathrm{V}.\mathrm{s})$ and D = 10 nm, which gives ${q}_{d}=100\phantom{\rule{3.33333pt}{0ex}}\mathsf{\mu}$C. (

**a**) V and i transients, (

**b**) I–V characteristic, (

**c**) $\varphi $-q curve and (

**d**) memristance and state variable transitions.

**Figure 28.**Analogue model of memristor adapt with permission from ref. [98].

**Figure 29.**Results of the sinusoidal input voltage. Parameters set: $R=1$ k$\Omega $, $C=1\phantom{\rule{3.33333pt}{0ex}}\mathsf{\mu}$F, ${G}_{0}=0.5\phantom{\rule{3.33333pt}{0ex}}\mathrm{S}$ and ${K}_{G}=10\mathrm{S}{\mathrm{V}}^{-1}$ (

**a**) ${V}_{o}=0.6\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}$ and variation of input frequency, ${\omega}_{o}=2\phantom{\rule{3.33333pt}{0ex}}\pi {f}_{o}$ with ${f}_{o}$ = 1 Hz. (

**b**) memductance for ${\omega}_{o}$ and ${V}_{o}=0.6\phantom{\rule{3.33333pt}{0ex}}\mathrm{V}$, (

**c**) at ${\omega}_{o}$ frequency and variation of voltage amplitude ${V}_{o}$, (

**d**) the flux $\varphi \left(t\right)$ for ${\omega}_{o}$ and ${V}_{o}=0.6\mathrm{V}$.

**Figure 30.**Schematic of a passive memristor emulator adapt with permission from ref. [102].

**Figure 31.**Comparison of the memristance $M\left(q\right)$ versus the flowing charge $q\left(t\right)$ for models (67) and (68), ${R}_{off}=16$ K$\Omega $, ${R}_{on}=100\phantom{\rule{3.33333pt}{0ex}}\Omega $ and ${q}_{d}=100\phantom{\rule{3.33333pt}{0ex}}\mathsf{\mu}$C. The first derivative of $M\left(q\right)$ with respect to q$\left(i.e.,\frac{dM\left(q\right)}{dq}\right)$ for Equation (67) has discontinuity at $q\left(t\right)=0$ and $q\left(t\right)={q}_{d}$ while $\frac{dM\left(q\right)}{dq}$ for Equation (68) is continuous at these q values.

**Figure 32.**Characteristics of the memristor model given in Equation (68) by using a sine current input $i\left(t\right)={I}_{0}\phantom{\rule{3.33333pt}{0ex}}sin\left(\omega t\right)$. The result is obtained for ${R}_{off}=16$ K$\Omega $, ${R}_{on}=100\phantom{\rule{3.33333pt}{0ex}}\Omega $, ${I}_{0}$ = 1 mA, f = 4 Hz and ${q}_{d}=100\phantom{\rule{3.33333pt}{0ex}}\mathsf{\mu}$C. (

**a**) $\varphi $-q curve, (

**b**) current and voltage transients and (

**c**) I–V characteristics.

**Figure 33.**Classification of some memristor applications according to array and discrete configurations in both analog and digital domains.

Window Function $\mathit{g}\left(\mathit{x}\right)$ | Strukov | Joglekar | Prodromakis |
---|---|---|---|

Resolve boundary issues | ✓ | ✓ | ✓ |

Impose nonlinear drift | ✓ | ✓ | ✓ |

Linkage with linear drift | ✗ | ✓ | ✓ |

Control parameter | ✗ | ✓ | ✓ |

${g}_{max}$ scalability | ✗ | ✗ | ✓ |

${q}_{R}$ value | 1.3 mC | 350 $\mathsf{\mu}$C | 150 $\mathsf{\mu}$C |

Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations. |

© 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Isah, A.; Bilbault, J.-M.
Review on the Basic Circuit Elements and Memristor Interpretation: Analysis, Technology and Applications. *J. Low Power Electron. Appl.* **2022**, *12*, 44.
https://doi.org/10.3390/jlpea12030044

**AMA Style**

Isah A, Bilbault J-M.
Review on the Basic Circuit Elements and Memristor Interpretation: Analysis, Technology and Applications. *Journal of Low Power Electronics and Applications*. 2022; 12(3):44.
https://doi.org/10.3390/jlpea12030044

**Chicago/Turabian Style**

Isah, Aliyu, and Jean-Marie Bilbault.
2022. "Review on the Basic Circuit Elements and Memristor Interpretation: Analysis, Technology and Applications" *Journal of Low Power Electronics and Applications* 12, no. 3: 44.
https://doi.org/10.3390/jlpea12030044