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Article

Efficiency of Priority Queue Architectures in FPGA †

Institute of Informatics, Information Systems and Software Engineering, Slovak University of Technology in Bratislava, 812 43 Bratislava, Slovakia
This paper is an extended version of our paper published in DSD, Kohutka, L.; Nagy, L.; Stopjaková, V. A Novel Hardware-Accelerated Priority Queue for Real-Time Systems, 2018. In Proceedings of the 21st Euromicro Conference on Digital System Design (DSD), Prague, Slovakia, 2018; pp. 46–53. https://doi.org/10.1109/DSD.2018.00023.
Academic Editors: Stefania Perri and Andrea Acquaviva
J. Low Power Electron. Appl. 2022, 12(3), 39; https://doi.org/10.3390/jlpea12030039
Received: 16 December 2021 / Revised: 18 April 2022 / Accepted: 13 July 2022 / Published: 14 July 2022
(This article belongs to the Special Issue Advanced Researches in Embedded Systems)
This paper presents a novel SRAM-based architecture of a data structure that represents a set of multiple priority queues that can be implemented in FPGA or ASIC. The proposed architecture is based on shift registers, systolic arrays and SRAM memories. Such architecture, called MultiQueue, is optimized for minimum chip area costs, which leads to lower energy consumption too. The MultiQueue architecture has constant time complexity, constant critical path length and constant latency. Therefore, it is highly predictable and very suitable for real-time systems too. The proposed architecture was verified using a simplified version of UVM and applying millions of instructions with randomly generated input values. Achieved FPGA synthesis results are presented and discussed. These results show significant savings in FPGA Look-Up Tables consumption in comparison to existing solutions. More than 63% of Look-Up Tables can be saved using the MultiQueue architecture instead of the existing priority queues. View Full-Text
Keywords: priority queue; architecture; efficiency; FPGA; SRAM; data sorting; MultiQueue priority queue; architecture; efficiency; FPGA; SRAM; data sorting; MultiQueue
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MDPI and ACS Style

Kohútka, L. Efficiency of Priority Queue Architectures in FPGA. J. Low Power Electron. Appl. 2022, 12, 39. https://doi.org/10.3390/jlpea12030039

AMA Style

Kohútka L. Efficiency of Priority Queue Architectures in FPGA. Journal of Low Power Electronics and Applications. 2022; 12(3):39. https://doi.org/10.3390/jlpea12030039

Chicago/Turabian Style

Kohútka, Lukáš. 2022. "Efficiency of Priority Queue Architectures in FPGA" Journal of Low Power Electronics and Applications 12, no. 3: 39. https://doi.org/10.3390/jlpea12030039

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