Next Article in Journal
Efficiency of Priority Queue Architectures in FPGA
Previous Article in Journal
Deep Learning Approaches to Source Code Analysis for Optimization of Heterogeneous Systems: Recent Results, Challenges and Opportunities
 
 
Article

Analysis and Comparison of Different Approaches to Implementing a Network-Based Parallel Data Processing Algorithm

Institute of Electronics and Informatics Engineering of Aveiro (IEETA), Department of Electronics, Telecommunications and Informatics, University of Aveiro, Campus Universitário de Santiago, 3810-193 Aveiro, Portugal
Academic Editors: Xinfei Guo and Andrea Acquaviva
J. Low Power Electron. Appl. 2022, 12(3), 38; https://doi.org/10.3390/jlpea12030038
Received: 22 May 2022 / Revised: 24 June 2022 / Accepted: 6 July 2022 / Published: 9 July 2022
It is well known that network-based parallel data processing algorithms are well suited to implementation in reconfigurable hardware recurring to either Field-Programmable Gate Arrays (FPGA) or Programmable Systems-on-Chip (PSoC). The intrinsic parallelism of these devices makes it possible to execute several data-independent network operations in parallel. However, the approaches to designing the respective systems vary significantly with the experience and background of the engineer in charge. In this paper, we analyze and compare the pros and cons of using an embedded processor, high-level synthesis methods, and register-transfer low-level design in terms of design effort, performance, and power consumption for implementing a parallel algorithm to find the two smallest values in a dataset. This problem is easy to formulate, has a number of practical applications (for instance, in low-density parity check decoders), and is very well suited to parallel implementation based on comparator networks. View Full-Text
Keywords: data processing; parallel algorithm; hardware accelerator; high-level synthesis; embedded processor; two smallest values in a dataset data processing; parallel algorithm; hardware accelerator; high-level synthesis; embedded processor; two smallest values in a dataset
Show Figures

Figure 1

MDPI and ACS Style

Skliarova, I. Analysis and Comparison of Different Approaches to Implementing a Network-Based Parallel Data Processing Algorithm. J. Low Power Electron. Appl. 2022, 12, 38. https://doi.org/10.3390/jlpea12030038

AMA Style

Skliarova I. Analysis and Comparison of Different Approaches to Implementing a Network-Based Parallel Data Processing Algorithm. Journal of Low Power Electronics and Applications. 2022; 12(3):38. https://doi.org/10.3390/jlpea12030038

Chicago/Turabian Style

Skliarova, Iouliia. 2022. "Analysis and Comparison of Different Approaches to Implementing a Network-Based Parallel Data Processing Algorithm" Journal of Low Power Electronics and Applications 12, no. 3: 38. https://doi.org/10.3390/jlpea12030038

Find Other Styles
Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Article Access Map by Country/Region

1
Back to TopTop