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Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution †

EPFL SCI-STI-MM, École Polytechnique Fédérale de Lausanne, CH-1015 Lausanne, Switzerland
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Author to whom correspondence should be addressed.
This paper is an extended version of our paper published in 14th IEEE MCSoC 2021.
Academic Editor: Andrea Acquaviva
J. Low Power Electron. Appl. 2022, 12(3), 36; https://doi.org/10.3390/jlpea12030036
Received: 10 March 2022 / Revised: 17 May 2022 / Accepted: 18 June 2022 / Published: 23 June 2022
The performance of programs executed on heterogeneous parallel platforms largely depends on the design choices regarding how to partition the processing on the various different processing units. In other words, it depends on the assumptions and parameters that define the partitioning, mapping, scheduling, and allocation of data exchanges among the various processing elements of the platform executing the program. The advantage of programs written in languages using the dataflow model of computation (MoC) is that executing the program with different configurations and parameter settings does not require rewriting the application software for each configuration setting, but only requires generating a new synthesis of the execution code corresponding to different parameters. The synthesis stage of dataflow programs is usually supported by automatic code generation tools. Another competitive advantage of dataflow software methodologies is that they are well-suited to support designs on heterogeneous parallel systems as they are inherently free of memory access contention issues and naturally expose the available intrinsic parallelism. So as to fully exploit these advantages and to be able to efficiently search the configuration space to find the design points that better satisfy the desired design constraints, it is necessary to develop tools and associated methodologies capable of evaluating the performance of different configurations and to drive the search for good design configurations, according to the desired performance criteria. The number of possible design assumptions and associated parameter settings is usually so large (i.e., the dimensions and size of the design space) that intuition as well as trial and error are clearly unfeasible, inefficient approaches. This paper describes a method for the clock-accurate profiling of software applications developed using the dataflow programming paradigm such as the formal RVL-CAL language. The profiling can be applied when the application program has been compiled and executed on GPU/CPU heterogeneous hardware platforms utilizing two main methodologies, denoted as static and dynamic. This paper also describes how a method for the qualitative evaluation of the performance of such programs as a function of the supplied configuration parameters can be successfully applied to heterogeneous platforms. The technique was illustrated using two different application software examples and several design points. View Full-Text
Keywords: dynamic dataflow programs; RVC-CAL; profiling; performance estimation parallel computing; source-to-source compiler; GPU programming heterogeneous systems dynamic dataflow programs; RVC-CAL; profiling; performance estimation parallel computing; source-to-source compiler; GPU programming heterogeneous systems
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MDPI and ACS Style

Bloch, A.; Casale-Brunet, S.; Mattavelli, M. Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution. J. Low Power Electron. Appl. 2022, 12, 36. https://doi.org/10.3390/jlpea12030036

AMA Style

Bloch A, Casale-Brunet S, Mattavelli M. Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution. Journal of Low Power Electronics and Applications. 2022; 12(3):36. https://doi.org/10.3390/jlpea12030036

Chicago/Turabian Style

Bloch, Aurelien, Simone Casale-Brunet, and Marco Mattavelli. 2022. "Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms by Dynamic Network Execution" Journal of Low Power Electronics and Applications 12, no. 3: 36. https://doi.org/10.3390/jlpea12030036

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