# ±0.3V Bulk-Driven Fully Differential Buffer with High Figures of Merit

^{1}

^{2}

^{3}

^{4}

^{5}

^{6}

^{*}

## Abstract

**:**

_{SS}= 12.69 MHzpFμW

^{−1}, a large signal figure of merit FOM

_{LS}= 34.89 (V/μs) pFμW

^{−1}, CMRR = 102 dB, PSRR+ = 109 dB, PSRR− = 100 dB, 1.1 μV/√Hz input noise spectral density, 0.3 mVrms input noise and 3.5 mV input DC offset voltage.

## 1. Introduction

_{Q}< 1 uW and very low supply voltages V

_{supply}< 1 V [2]. In order to preserve battery life and/or to be able to operate with energy harvested sources in biological systems, these systems operate transistors in subthreshold and use bulk-driven circuits, where the input signals are injected through the bulk terminals rather than through the gate terminals [3]. To suppress large noise from digital and other analog sections of the chip and to increase dynamic range, analog signals on chips are usually processed using fully differential circuits.

_{out}≪ R

_{L}, very high input impedance R

_{in}≫ R

_{so}and close to unity gain G = V

_{out}/V

_{in}= 1 (R

_{so}is the signal source impedance). The buffer is commonly used as an interface between subsystems on a chip or to bring signals out of a chip. The op-amp is commonly used to implement buffers. Figure 1a shows the conventional implementation of a single-ended voltage buffer based on the non-inverting op-amp configuration. A drawback of fully differential op-amp circuits is that they can only be used to implement inverting configurations with finite input impedance R

_{in}. Figure 1b shows a possible implementation of a fully differential buffer using four equal valued resistors R. This requires the value of R to be in the order of tens of MΩs to avoid loading the signals sources that have typically impedances R

_{so}in the order of MΩs for micropower circuits operating in subthreshold. These resistor values are impractical due to the large silicon area required for their implementation and to the large time constants associated with them that degrade the circuit’s bandwidth. Another drawback is that the BW of a unity gain inverting buffer corresponds to one half of the gain bandwidth of the op-amp (BW = GB/2) as opposed to the voltage buffer based on the non-inverting configuration that has a factor two higher bandwidth BW = GB. Figure 1c shows the implementation of a true fully differential buffer using a fully differential op-amp with a differential–difference input stage [4,5,6] that has two pairs of input terminals.

_{i1+}, V

_{i1−}, V

_{i2+}and V

_{i2−}, a common load for the input stage, two output stages and a common-mode feedback network. Upon application of negative feedback, the virtual short-circuit input rule of a conventional op-amp (V

_{i+}− V

_{i−}) = 0 is simply replaced by the composite virtual short circuit input rule: (V

_{i1+}− V

_{i1−}) + (V

_{i2+}− V

_{i2−}) = 0 in the differential–difference input stage [4]. In this paper the output stage operates in class AB based on the Free Class AB Technique reported in [7] as explained in detail in Section 3.

_{S+}, V

_{S−}are not loaded by the buffer. Since it is based on a non-inverting configuration, the bandwidth of the buffer corresponds to the gain bandwidth of the op-amp, as opposed to the circuit of Figure 1b that has half the bandwidth. Negative feedback results in the input terminals having voltages V1 = Vs+ = V

_{i1+}= V

_{i1−}(V2 = Vs− = V

_{i2+}= V

_{i2−}). These voltages follow the swing of the input signals V

_{S+}(V

_{S−}) similar to the case of the conventional single-ended buffer of Figure 1a. A drawback of gate-driven non-inverting op-amp circuits operating from low supply voltages (V

_{supply}< 1 V) is that the peak-to-peak input signal swing V

_{PPswing}is severely limited by the differential pair headroom HR

_{DP}= |V

_{GS}| + |V

_{DSsat}|. The input swing is given by V

_{PPswing}= V

_{supply}− HR

_{DP}(V

_{GS}and V

_{DSsat}are the gate-source and drain-source saturation voltage of the transistors in the input differential pairs). Bulk-driven differential amplifiers can operate with rail-to-rail input signals in low-voltage circuits [8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23]. The condition V

_{supply}< 1 V is usually imposed in bulk-driven circuits to avoid forward biasing the bulk–substrate PN junctions of the bulk-driven differential pair input transistors. These circuits are usually operated in subthreshold.

## 2. High CMRR Bulk-Driven No-Tail Pseudo-Differential Pair

_{Gcntl}that provides it with high common mode rejection as explained below. All transistors in the circuit of Figure 3 operate in subthreshold in high gain mode with g

_{m}r

_{o}>> 1.

#### 2.1. Differential Gain

_{i+}, V

_{i−}. In this case, for positive values of the input differential voltage V

_{d,}the voltage V

_{i+}= V

_{d}/2 increases and V

_{i−}= −V

_{d}/2 decreases by the same amount. Drain currents in M

_{1}, M

_{1p}decrease by–ΔI

_{D}= −g

_{mb}V

_{d}/2, and drain currents in M

_{2}, M

_{2P}increase by the same amount ΔI

_{D}= g

_{mb}V

_{d}/2. Since the sum of currents in M

_{1p}, M

_{2p}remains constant and equal to 2Ib the voltage V

_{Gcntl}at the gate of M

_{1}, M

_{1p}, M

_{2}, M

_{2p}has only relatively small variations that compensate for channel-length modulation effects. The effective differential transconductance g

_{md}has an approximate value g

_{md}= g

_{mb}= (I

_{1}− I

_{2})/V

_{d}.

#### 2.2. Common-Mode Gain

_{icm}= V

_{i+}= V

_{i−}. Given that M

_{1p}, M

_{2p}satisfy the condition 2I

_{b}= I

_{1p}+ I

_{2p}, negative feedback adjusts the voltage V

_{Gcntl}so that the condition I

_{b}= I

_{1p}= I

_{2p}= I

_{1}= I

_{2}is satisfied. Transistors M

_{1}, M

_{c1p}and M

_{2}, M

_{c2p}constitute high gain cascode amplifiers that provide a gain A = (g

_{m}r

_{o})

^{2}to the local negative feedback loop (g

_{m}and r

_{o}are the small signal transconductance gain and output resistance of the MOS transistor assumed, for simplicity, equal for all transistors). In this case, all currents (I

_{1p}, I

_{2p}, I

_{1}, I

_{2}) remain constant, and the output differential current should be I

_{out}= I

_{1}− I

_{2}= 0 which corresponds ideally to a zero common mode transconductance gain. In practice, however, the finite gain A

_{fb}= (g

_{m}r

_{o})

^{2}of the loop formed by M

_{1p}, M

_{c1p}and M

_{2p}, M

_{c2p}leads to a non-zero common mode transconductance gain g

_{mCM}given by g

_{mCM}= g

_{mb}/(g

_{m}r

_{o})

^{2,}The systematic common mode rejection ratio is given by CMRR

_{syst}= g

_{md}/g

_{mCM}= 1/(g

_{m1}r

_{o})

^{2}. Other authors (i.e., [8,9,10]) have used non-cascoded no-tail bulk-driven pseudo-differential pairs which are characterized by much lower CMRR.

_{1}and M

_{2}, denoted I

_{RL1}and I

_{RL2}, for complementary differential input voltages and denoted I

_{RL1CM}, I

_{RL2CM}for common mode input voltages. Figure 4b shows the value of V

_{Gcntl}for differential input voltages and V

_{gcntCM}for common mode input voltages. Notice that the bulk-driven pseudo-DP cell has high CMRR. It shows no noticeable changes in I

_{RL1CM}, I

_{RL2CM}for common mode input voltages, while V

_{gcntCM}has relatively large changes that keep the current in M

_{1}, M

_{2}approximately constant. On the other hand, currents I

_{RL1}and I

_{RL2}are subject to relatively large complementary changes, while V

_{Gcntl}is subject to small changes that compensate for channel length modulation effects.

## 3. Transistor Level Implementation of FD-DDA

_{1p}and M

_{2}are connected to the output reference common-mode voltage V

_{refCM,}and the bulk terminals of M

_{1}and M

_{2p}are connected to the FD-DDA output voltages V

_{o+}and V

_{o−}. In this case, the cascoded load transistor M

_{LCM}is diode connected. The voltage V

_{gntCM}shows changes proportional to the difference between the common-mode output voltage V

_{oCM}= (V

_{o+}+ V

_{o−})/2 and the output reference common-mode voltage V

_{refCM}. It generates variations given by ΔV

_{gcntCM}= −K(V

_{Ocm}− V

_{refCM}) with K~1. The common mode feedback loop has approximately a gain A

_{CM}= (g

_{m}r

_{o})

^{2}. It operates with rail-to-rail output voltage variations. This differs from the conventional gate-driven two-differential pair-based CMFN that has a very limited common-mode operating range limited by the headroom of the gate-driven differential pairs HD

_{DP}used in its implementation. Conventional R

_{c}− C

_{c}Miller compensation elements are used. The output stages use the free class AB technique reported in [7] to achieve current efficient push–pull operation with output quiescent current I

_{outQ}= I

_{b}and dynamic peak output currents much larger than I

_{outQ}. This is performed by transferring directly dynamic changes in nodes X and Y to the gates of the PMOS output transistors through capacitors C

_{bat}that act as floating batteries. In practice, R

_{large}and C

_{bat}form a high-pass circuit with a very low 3 dB frequency (in the order of Hz). The large resistive elements R

_{large}required in this technique are implemented using pseudo-resistors [7]. The input cascoded stage has a gain.

_{inp}= g

_{mb}g

_{m}r

_{o}

^{2}

_{out}= (g

_{moutP}+ g

_{moutN}) r

_{oP}||r

_{oN}

_{ol}= A

_{inp}A

_{out,}the gain bandwidth product by

_{mb}/C

_{c})

_{pout}HF = (1/2π)(g

_{moutP}+ g

_{moutN})/C

_{L}

_{zHF}= (1/2π)(1/((1/(g

_{moutP}+ g

_{moutN}) − R

_{c}) C

_{c}))

_{s}is used for phase lead compensation to improve the phase margin of the FD-DDA. It generates a zero f

_{zlead}in the transfer function with a value.

_{zlead}= (1/2π)(1/R

_{s}C

_{L})

## 4. Results

_{L}= 50 pF, R

_{s}= 10 kΩ, C

_{c}= 0.5 pF and R

_{c}= 10 MΩ were used. Rlarge resistors were implemented with two PMOS transistors in series with dimensions 2 µm/0.2 µm. Compensation resistors R

_{c}were implemented as shown in Figure 5 with the parallel combination of a PMOS and an NMOS transistor with dimensions W = 0.5 µm/1 µm.

^{2}. Figure 7 shows the open-loop response of the FD-DDA It has a DC open-loop gain A

_{olDC}= 86.77 dB, a unity gain frequency f

_{u}= 88.1 kHz and a phase margin PM = 65.47°. Figure 8 shows the AC response of the buffer. It has a bandwidth BW = 172.91 kHz, with 0.556 dB peaking.

_{out}, V

_{outp}and of the load capacitor currents I

_{CL}, I

_{CLP}to a 10 kHz, 0.4 V

_{PP}input pulse. It can be seen that the peak positive and negative currents have values I

_{pkpos}= 6 µA and I

_{pkneg}= −4.6 μA, and the buffer has a symmetrical slew rate SR+ = SR− = 0.238 V/µs. These currents are essentially larger than the output quiescent current I

_{outQ}= 60 nA and than the total FD-DDA quiescent current I

_{totQ}= 1.12 μA. A conventional class A DDA would have a peak negative output current of I

_{pk}= IoutQ = 60 nA and would be characterized by an essentially lower slew rate of only SR− = 0.0012 V/µs.

_{totQ}= 0.666 μW, input noise spectral density at 1 kHz and RMS noise values 1.1 uV/√Hz and 0.34 mV

_{RMS,}respectively. RMS noise was obtained by integrating noise spectral density over the noise bandwidth. CMRR = 102 dB, PSRR+ = 109 dB, PSRR− = 100 dB, input DC offset voltage V

_{os}= 3.5 mV. V

_{os}was obtained including typical 2% transistor W/L mismatches. The small signal and large signal figures of merit of the proposed FD-DDA are FOMss = GBC

_{Ltot}/P

_{Q}= 12.69 MHzpF/µW. FOM

_{LS}= SRC

_{Ltot}/P

_{Q}= 34.79 (V/μs)pF/µW. The current efficiency is CE = I

_{outtotpk}/I

_{totQ}= 8.9. Total harmonic distortion is THD = 0.09% for a 10 kHz 0.2 V

_{PP}and 10 kHz sinusoidal input signal. Table 1, Table 2 and Table 3 show corner simulations of parameters at three temperatures spanning a 100 °C range.

## 5. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## References

- Casson, A.J.; Logesparan, L.; Rodriguez-Villegas, E. An introduction to future truly wearable medical devices—ASIC. In Proceedings of the 2010 Annual International Conference of the IEEE Engineering in Medicine and Biology, Buenos Aires, Argentina, 31 August–4 September 2010; Volume 30, pp. 3430–3431. [Google Scholar]
- Chatterjee, S.; Tsividis, Y.; Kinget, P. 0.5-V analog circuit techniques and their application in OTA and filter design. IEEE J. Solid-State Circuits
**2005**, 40, 2373–2387. [Google Scholar] [CrossRef] - Stopjakova, V.; Rakus, M.; Kovac, M.; Arbet, D.; Nagy, L.; Sovcik, M.; Potocny, M. Ultra-Low Voltage Analog IC Design: Challenges, Methods and Examples. Radioengineering
**2018**, 27, 171–185. [Google Scholar] [CrossRef] - Ramirez-Angulo, J.; Ledesma, F. The universal op-amp and applications in continuous-time resistorless and capacitorless linear weighted voltage addition. IEEE Trans. Circuits Syst. II Express Briefs
**2006**, 53, 404–408. [Google Scholar] [CrossRef] - Sackinger, E.; Guggenbuhl, W. A versatile building block: The CMOS differential difference amplifier. IEEE J. Solid-State Circuits
**1987**, 22, 287–294. [Google Scholar] [CrossRef] - Huang, S.-C.; Ismail, M. A wide range differential difference amplifier: A basic block for analog signal processing in MOS technology. IEEE Trans. Circuits Syst. II
**1993**, 40, 289–301. [Google Scholar] [CrossRef] - Ramirez-Angulo, J.; Carvajal, R.G.; Galan, J.A.; Lopez-Martin, A. A free but efficient low-voltage class-AB two-stage operational amplifier. IEEE Trans. Circuits Syst. II Express Briefs
**2006**, 53, 568–571. [Google Scholar] [CrossRef] - Grech, I.; Micallef, J.; Azzopardi, G.; Debono, C.J. A low voltage wide-input range bulk-input CMOS OTA. Analog. Integr. Circuits Signal Process.
**2005**, 43, 127–136. [Google Scholar] [CrossRef] - Trakimas, M.; Sonkusale, S. A 0.5 V bulk-input OTA with improved common-mode feedback for low-frequency filtering applications. Analog. Integr. Circuits Signal Process.
**2009**, 59, 83–89. [Google Scholar] [CrossRef] - Abdelfattah, O.; Roberts, G.W.; Shih, I.; Shih, Y.S. An Ultra-Low-Voltage CMOS Process-Insensitive Self-Biased OTA With Rail-to-Rail Input Range. IEEE Trans. Circuits Syst. I Regul. Pap.
**2015**, 63, 2380–2390. [Google Scholar] [CrossRef] - Cabrera-Bernal, E.; Pennisi, S.; Grasso, A.D.; Torralba, A.; Carvajal, R.G. 0.7-V Three-Stage Class-AB CMOS Operational Transconductance Amplifier. IEEE Trans. Circuits Syst. I Regular Papers
**2016**, 63, 1807–1815. [Google Scholar] [CrossRef] - Zuo, L.; Islam, S.K. Low-Voltage Bulk-Driven Operational Amplifier with Improved Transconductance. IEEE Trans. Circuits Syst. I
**2013**, 60, 2084–2091. [Google Scholar] [CrossRef] - Kulej, T.; Khateb, F. 0.4-V bulk-driven differential-difference amplifier. Microelectron. J.
**2015**, 46, 362–369. [Google Scholar] [CrossRef] - Qin, Z.; Tanaka, A.; Takaya, N.; Yoshizawa, H. 0.5-V 70-nW Rail-to-Rail Operational Amplifier Using a Cross-Coupled Output Stage. IEEE Trans. Circuits Syst. II
**2016**, 63, 1009–1013. [Google Scholar] [CrossRef] - Khateb, F.; Kulej, T. Design and Implementation of a 0.3-V Differential Difference Amplifier. IEEE Trans. Circuits Syst. I
**2019**, 66, 513–523. [Google Scholar] - Kulej, T.; Khateb, F.A. Compact 0.3-V Class AB Bulk-Driven OTA. IEEE Trans. VLSI Syst.
**2020**, 28, 224–232. [Google Scholar] [CrossRef] - Woo, K.C.; Yang, B.D. A 0.25-V Rail-to-Rail Three-Stage OTA With an Enhanced DC Gain. IEEE Trans. Circuits Syst. II
**2020**, 67, 1179–1183. [Google Scholar] [CrossRef] - Khateb, F.; Kulej, T.; Kumngern, M.; Arbet, D.; Jaikla, W. A 0.5-V 95-dB rail-to-rail DDA for biosignal processing. AEU—Int. J. Electron. Commun.
**2022**, 145, 154098. [Google Scholar] [CrossRef] - Kulej, T.; Khateb, F.; Arbet, D.; Stopjakova, V. A 0.3-V High Linear Rail-to-Rail Bulk-Driven OTA in 0.13 μm CMOS. IEEE Trans. Circuits Syst. II Express Briefs
**2022**, 69, 2046–2050. [Google Scholar] [CrossRef] - Tang, N.; Hong, W.; Kim, J.H.; Yang, D.; Heo, D. A Sub-1-V Bulk-Driven Opamp With an Effective Transconductance-Stabilizing Technique. IEEE Trans. Circuits Syst. II Express Briefs
**2015**, 62, 1018–1022. [Google Scholar] [CrossRef] - Akbari, M.; Hussein, S.; Hashim, Y.; Tang, K.T. An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers. IEEE Trans. VLSI Syst.
**2021**, 29, 1601–1611. [Google Scholar] [CrossRef] - Baghtash, H.F. A 0.4 V, body-driven, fully differential, tail-less OTA based on current push-pull. Microelectron. J.
**2020**, 99, 104768. [Google Scholar] [CrossRef] - Veldandi, H.; Shaik, R.A. A 0.3-v pseudo-differential bulk-input ota for low-frequency applications. Circuits Syst. Signal Process.
**2018**, 37, 5199–5221. [Google Scholar] [CrossRef]

**Figure 1.**(

**a**) Single-ended buffer based on non-inverting configuration; (

**b**) fully differential unity gain amplifier with finite input impedance 2R based on conventional fully differential op-amp; (

**c**) true fully differential analog buffer based on FD-DDA with infinite input impedance.

**Figure 2.**(

**a**) Architecture of fully differential Miller op-amp with DDA input stage; (

**b**) FD−DDA symbol.

**Figure 3.**Low supply voltage bulk-driven class AB no-tail cascaded pseudo-differential pair with rail-to-rail input range and high common mode rejection ratio. The biasing current source 2I

_{b}is also implemented as a cascoded current source.

**Figure 4.**(

**a**) Currents I

_{RL1}, I

_{RL2}in M

_{1}, M

_{2}for complementary input signals Vi+ = V

_{INP}/2, Vi− = −V

_{INP}/2 and currents I

_{RL1CM}, I

_{RL2CM}in M

_{1}, M

_{2}for common mode input signals Vi+ = Vi− = V

_{INP}; (

**b**) control voltage V

_{Gcntl}for differential complementary input signals and V

_{GcntlCM}for common mode input signals.

**Figure 9.**Top: transient voltage response of Vout, Voutp to 10 kHz, 0.4 V

_{PP}input pulse Vinp; Bottom: transient load currents I

_{CL}, I

_{CLP}in load capacitors C

_{L}, C

_{LP}.

tt | ss | ff | fs | sf | |
---|---|---|---|---|---|

fu (kHz) | 76.2 | 75.7 | 73.4 | 73.9 | 76.2 |

A_{OLDC} (dB) | 72.8 | 77.5 | 56.2 | 59.3 | 75.8 |

PM | 65.1° | 64.7° | 66.2° | 65.2° | 65.4° |

CMRR (dB) | 141 | 138 | 116 | 123 | 147 |

PSRR (dB) | 81 | 101 | 70.4 | 71.4 | 76.6 |

Slew Rate (v/μs) positive | 0.25 | 0.22 | 0.24 | 0.24 | 0.23 |

Slew Rate (v/μs) negative | 0.248 | 0.22 | 0.24 | 0.24 | 0.23 |

tt | ss | ff | fs | sf | |
---|---|---|---|---|---|

fu (kHz) | 119.6 | 120.4 | 120.2 | 120.9 | 112.7 |

A_{OLDC} (dB) | 85.3 | 81.6 | 84.1 | 84 | 83.6 |

PM | 62.6° | 63.5° | 62.5° | 62.9° | 62.7° |

CMRR (dB) | 171.5 | 130 | 148 | 139.2 | 148 |

PSRR (dB) | 97 | 75 | 112.4 | 84.6 | 75 |

Slew Rate (v/μs) positive | 0.25 | 0.22 | 0.24 | 0.24 | 0.23 |

Slew Rate (v/μs) negative | 0.248 | 0.22 | 0.24 | 0.24 | 0.23 |

tt | ss | ff | fs | sf | |
---|---|---|---|---|---|

fu (kHz) | 135.36 | 95.5 | 143.9 | 105 | 139.2 |

A_{OLDC} (dB) | 71.3 | 52 | 88 | 62 | 79.6 |

PM | 65° | 75° | 62.6° | 73.4° | 63.4° |

CMRR (dB) | 126 | 105 | 157 | 121.7 | 141 |

PSRR (dB) | 70 | 40 | 91 | 52 | 96 |

Slew Rate (v/μs) positive | 0.20 | 0.14 | 0.29 | 0.23 | 0.13 |

Slew Rate (v/μs) negative | 0.20 | 0.14 | 0.29 | 0.23 | 0.13 |

Parameter Year Sim/Exp | This Work Sim | [19] 2022 Sim | [18] 2021 Exp | [17] 2020 Exp | [16] 2020 Exp | [15] 2019 Exp | [14] 2016 Exp | [13] 2015 Exp | [12] 2013 Sim | [11] 2016 Exp |
---|---|---|---|---|---|---|---|---|---|---|

Vsupply (V) | 0.6 | 0.5 | 0.5 | 0.25 | 0.3 | 0.3 | 0.5 | 0.4 | 1 | 0.7 |

Technology (μm) | 0.18 | 0.18 | 0.18 | 0.065 | 0.18 | 0.18 | 0.18 | 0.05 | 0.35 | 0.18 |

Power Dissipation (μW) | 0.684 | 0.312 | 0.0455 | 0.026 | 0.0126 | 0.022 | 0.07 | 31.84 | 197 | 22.4 |

C_{L} (pF) total | 50 × 2 | 15 | 15 | 15 | 30 | 20 | 40 | 20 × 2 | 15 | 20 |

GB (MHz) | 0.0868 | 0.0128 | 0.0075 | 0.0095 | 0.00296 | 0.00185 | 0.004 | 2.31 | 11.67 | 3 |

SR+/SR− (V/μs) | 0.238 | 0.0158/0.0135 | - | 0.002/0.002 | 0.0019/0.0064 | 0.00165/0.00135 | 0.002/0.002 | 1.2 | 2.53/1.37 | 1.8/3.8 |

CMRR (dB) | 102 | 60 | 85.7 | 62.5 | 110 | 82 | 55 | 92 | 40 | 19 |

PSRR+/PSRR− (dB) | 109/ 100 | 66 | 68.1 | 38 | 56 | 57 | 52 | 64 | 40/46.8 | 52.1 |

Input noise spectral density ($\mathsf{\mu}\mathrm{V}/\sqrt{\mathrm{Hz}}$) | 1.1 @ 1 kHz | 0.88 | 0.65 @ 1 kHz | - | 1.6 | 2.58 | - | 0.164 @ 10 kHz | 0.06 @ 1 MHz | 0.1@ 1 MHz |

FOM_{SS} (MHz.pF/μW) | 12.69 | 0.614 | 2.5 | 5.48 | 7.047 | 1.68 | 2.28 | 2.88 | 0.88 | 2.67 |

FOM_{LS} ((V/µs).pF/μW) | 34.79 | 0.647 | 2.76 | 1.15 | 4.52 | 1.22 | 1.14 | 1.5 | 0.10 | 1.60 |

Total Harmonic Distortion (%) | 0.09 @ 1 kHz, 0.2 V _{PP} | 0.28 | 1% @ 0.46 V_{PP} | - | - | - | - | - | - | 0.2 @ 100 kHz 400 mV _{PP} |

Input offset (mV) | 3.2 | 6.14 | 2.3 | - | 3.2 | 4.73 | 4 (average) | - | 8.4,10 | 11 |

Single-Ended/Fully differential | FD | SE | SE | SE | SE | SE | SE | FD | SE | SE |

_{LS}was performed using the minimum of the two slew rates values min{SR

^{+}, SR

^{−}}. (b) For fully differential (FD) amplifiers, the total load capacitance CLtot = 2xCLwas used to calculate FOM

_{SS}and FOM

_{LS}.

Publisher’s Note: MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations. |

© 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https://creativecommons.org/licenses/by/4.0/).

## Share and Cite

**MDPI and ACS Style**

Gangineni, M.; Ramirez-Angulo, J.; Vázquez-Leal, H.; Huerta-Chua, J.; Lopez-Martin, A.J.; Carvajal, R.G.
±0.3V Bulk-Driven Fully Differential Buffer with High Figures of Merit. *J. Low Power Electron. Appl.* **2022**, *12*, 35.
https://doi.org/10.3390/jlpea12030035

**AMA Style**

Gangineni M, Ramirez-Angulo J, Vázquez-Leal H, Huerta-Chua J, Lopez-Martin AJ, Carvajal RG.
±0.3V Bulk-Driven Fully Differential Buffer with High Figures of Merit. *Journal of Low Power Electronics and Applications*. 2022; 12(3):35.
https://doi.org/10.3390/jlpea12030035

**Chicago/Turabian Style**

Gangineni, Manaswini, Jaime Ramirez-Angulo, Héctor Vázquez-Leal, Jesús Huerta-Chua, Antonio J. Lopez-Martin, and Ramon Gonzalez Carvajal.
2022. "±0.3V Bulk-Driven Fully Differential Buffer with High Figures of Merit" *Journal of Low Power Electronics and Applications* 12, no. 3: 35.
https://doi.org/10.3390/jlpea12030035