±0.3V Bulk-Driven Fully Differential Buffer with High Figures of Merit

Abstract

A high performance bulk-driven rail-to-rail fully differential buffer operating from ±0.3V supplies in 180 nm CMOS technology is reported. It has a differential–difference input stage and common mode feedback circuits implemented with no-tail, high CMRR bulk-driven pseudo-differential cells. It operates in subthreshold, has infinite input impedance, low output impedance (1.4 kΩ), 86.77 dB DC open-loop gain, 172.91 kHz bandwidth and 0.684 μW static power dissipation with a 50-pF load capacitance. The buffer has power efficient class AB operation, a small signal figure of merit FOM_SS = 12.69 MHzpFμW⁻¹, a large signal figure of merit FOM_LS = 34.89 (V/μs) pFμW⁻¹, CMRR = 102 dB, PSRR+ = 109 dB, PSRR− = 100 dB, 1.1 μV/√Hz input noise spectral density, 0.3 mVrms input noise and 3.5 mV input DC offset voltage.

1. Introduction

Biomedical wearable and implantable systems are becoming widely used to sense and monitor biological signals such as EEG, ECG, respiratory signals, etc., in real time [1]. The electronic circuitry used in these systems requires very low power dissipation P_Q < 1 uW and very low supply voltages V_supply < 1 V [2]. In order to preserve battery life and/or to be able to operate with energy harvested sources in biological systems, these systems operate transistors in subthreshold and use bulk-driven circuits, where the input signals are injected through the bulk terminals rather than through the gate terminals [3]. To suppress large noise from digital and other analog sections of the chip and to increase dynamic range, analog signals on chips are usually processed using fully differential circuits.

An important building block of analog systems is the analog buffer that is required to have very low output impedance R_out ≪ R_L, very high input impedance R_in ≫ R_so and close to unity gain G = V_out/V_in = 1 (R_so is the signal source impedance). The buffer is commonly used as an interface between subsystems on a chip or to bring signals out of a chip. The op-amp is commonly used to implement buffers. Figure 1a shows the conventional implementation of a single-ended voltage buffer based on the non-inverting op-amp configuration. A drawback of fully differential op-amp circuits is that they can only be used to implement inverting configurations with finite input impedance R_in. Figure 1b shows a possible implementation of a fully differential buffer using four equal valued resistors R. This requires the value of R to be in the order of tens of MΩs to avoid loading the signals sources that have typically impedances R_so in the order of MΩs for micropower circuits operating in subthreshold. These resistor values are impractical due to the large silicon area required for their implementation and to the large time constants associated with them that degrade the circuit’s bandwidth. Another drawback is that the BW of a unity gain inverting buffer corresponds to one half of the gain bandwidth of the op-amp (BW = GB/2) as opposed to the voltage buffer based on the non-inverting configuration that has a factor two higher bandwidth BW = GB. Figure 1c shows the implementation of a true fully differential buffer using a fully differential op-amp with a differential–difference input stage [4,5,6] that has two pairs of input terminals.

Figure 2 shows the architecture of a fully differential Miller op-amp using a differential–difference input stage (denoted here FD-DDA). The input stage has two differential pairs with two pairs of input terminals V_i1+, V_i1−, V_i2+ and V_i2−, a common load for the input stage, two output stages and a common-mode feedback network. Upon application of negative feedback, the virtual short-circuit input rule of a conventional op-amp (V_i+ − V_i−) = 0 is simply replaced by the composite virtual short circuit input rule: (V_i1+ − V_i1−) + (V_i2+ − V_i2−) = 0 in the differential–difference input stage [4]. In this paper the output stage operates in class AB based on the Free Class AB Technique reported in [7] as explained in detail in Section 3.

The buffer of Figure 1c is a true fully differential buffer with infinite input impedance. It does not require external resistors; therefore, signal sources V_S+, V_S− are not loaded by the buffer. Since it is based on a non-inverting configuration, the bandwidth of the buffer corresponds to the gain bandwidth of the op-amp, as opposed to the circuit of Figure 1b that has half the bandwidth. Negative feedback results in the input terminals having voltages V1 = Vs+ = V_i1+ = V_i1− (V2 = Vs− = V_i2+ = V_i2−). These voltages follow the swing of the input signals V_S+ (V_S−) similar to the case of the conventional single-ended buffer of Figure 1a. A drawback of gate-driven non-inverting op-amp circuits operating from low supply voltages (V_supply < 1 V) is that the peak-to-peak input signal swing V_PPswing is severely limited by the differential pair headroom HR_DP = |V_GS| + |V_DSsat|. The input swing is given by V_PPswing = V_supply − HR_DP (V_GS and V_DSsat are the gate-source and drain-source saturation voltage of the transistors in the input differential pairs). Bulk-driven differential amplifiers can operate with rail-to-rail input signals in low-voltage circuits [8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23]. The condition V_supply < 1 V is usually imposed in bulk-driven circuits to avoid forward biasing the bulk–substrate PN junctions of the bulk-driven differential pair input transistors. These circuits are usually operated in subthreshold.

In this paper, we show the implementation of a high performance fully differential buffer with rail-to-rail input and output swing based on a bulk-driven FD-DDA implemented using a high CMRR no-tail bulk-driven pseudo-differential cell.

2. High CMRR Bulk-Driven No-Tail Pseudo-Differential Pair

Figure 3 shows the schematic of a bulk-driven no-tail pseudo-differential pair cell. The input terminals Vi+, Vi− can have rail-to-rail swing. This cell is used to implement the two input pseudo-differential pairs of the differential–difference input stage and the common-mode feedback network of the proposed fully differential DDA with low supply voltage requirements, rail-to-rail input and output range, high CMRR and class AB operation. The cells include a high gain negative feedback loop through V_Gcntl that provides it with high common mode rejection as explained below. All transistors in the circuit of Figure 3 operate in subthreshold in high gain mode with g_mr_o >> 1.

2.1. Differential Gain

Assume complementary input voltages V_i+, V_i−. In this case, for positive values of the input differential voltage V_d, the voltage V_i+ = V_d/2 increases and V_i− = −V_d/2 decreases by the same amount. Drain currents in M₁, M_1p decrease by–ΔI_D = −g_mbV_d/2, and drain currents in M₂, M_2P increase by the same amount ΔI_D = g_mbV_d/2. Since the sum of currents in M_1p, M_2p remains constant and equal to 2Ib the voltage V_Gcntl at the gate of M₁, M_1p, M₂, M_2p has only relatively small variations that compensate for channel-length modulation effects. The effective differential transconductance g_md has an approximate value g_md = g_mb = (I₁ − I₂)/V_d.

2.2. Common-Mode Gain

Assume now common-mode input voltages V_icm = V_i+ = V_i−. Given that M_1p, M_2p satisfy the condition 2I_b = I_1p + I_2p, negative feedback adjusts the voltage V_Gcntl so that the condition I_b = I_1p = I_2p = I₁ = I₂ is satisfied. Transistors M₁, M_c1p and M₂, M_c2p constitute high gain cascode amplifiers that provide a gain A = (g_mr_o)² to the local negative feedback loop (g_m and r_o are the small signal transconductance gain and output resistance of the MOS transistor assumed, for simplicity, equal for all transistors). In this case, all currents (I_1p, I_2p, I₁, I₂) remain constant, and the output differential current should be I_out = I₁ − I₂ = 0 which corresponds ideally to a zero common mode transconductance gain. In practice, however, the finite gain A_fb = (g_mr_o)² of the loop formed by M_1p, M_c1p and M_2p, M_c2p leads to a non-zero common mode transconductance gain g_mCM given by g_mCM = g_mb/(g_mr_o)^2, The systematic common mode rejection ratio is given by CMRR_syst = g_md/g_mCM = 1/(g_m1r_o)². Other authors (i.e., [8,9,10]) have used non-cascoded no-tail bulk-driven pseudo-differential pairs which are characterized by much lower CMRR.

Figure 4a shows the currents in M₁ and M₂, denoted I_RL1 and I_RL2, for complementary differential input voltages and denoted I_RL1CM, I_RL2CM for common mode input voltages. Figure 4b shows the value of V_Gcntl for differential input voltages and V_gcntCM for common mode input voltages. Notice that the bulk-driven pseudo-DP cell has high CMRR. It shows no noticeable changes in I_RL1CM, I_RL2CM for common mode input voltages, while V_gcntCM has relatively large changes that keep the current in M₁, M₂ approximately constant. On the other hand, currents I_RL1 and I_RL2 are subject to relatively large complementary changes, while V_Gcntl is subject to small changes that compensate for channel length modulation effects.

3. Transistor Level Implementation of FD-DDA

Figure 5 shows the full transistor level schematic of the FD-DDA with the architecture of Figure 2a. It is a two-stage Miller op-amp with a differential–difference input stage that uses two of the bulk-driven no-tail pseudo-DPs described in Section 2. The common-mode feedback network also uses a bulk-driven no-tail pseudo-DP cell. In the CMFB cell, the bulk terminals of transistors M_1p and M₂ are connected to the output reference common-mode voltage V_refCM, and the bulk terminals of M₁ and M_2p are connected to the FD-DDA output voltages V_o+ and V_o−. In this case, the cascoded load transistor M_LCM is diode connected. The voltage V_gntCM shows changes proportional to the difference between the common-mode output voltage V_oCM = (V_o+ + V_o−)/2 and the output reference common-mode voltage V_refCM. It generates variations given by ΔV_gcntCM = −K(V_Ocm − V_refCM) with K~1. The common mode feedback loop has approximately a gain A_CM = (g_mr_o)². It operates with rail-to-rail output voltage variations. This differs from the conventional gate-driven two-differential pair-based CMFN that has a very limited common-mode operating range limited by the headroom of the gate-driven differential pairs HD_DP used in its implementation. Conventional R_c − C_c Miller compensation elements are used. The output stages use the free class AB technique reported in [7] to achieve current efficient push–pull operation with output quiescent current I_outQ = I_b and dynamic peak output currents much larger than I_outQ. This is performed by transferring directly dynamic changes in nodes X and Y to the gates of the PMOS output transistors through capacitors C_bat that act as floating batteries. In practice, R_large and C_bat form a high-pass circuit with a very low 3 dB frequency (in the order of Hz). The large resistive elements R_large required in this technique are implemented using pseudo-resistors [7]. The input cascoded stage has a gain.

A_inp = g_mbg_mr_o²

(1)

The output stage has a gain.

A_out = (g_moutP + g_moutN) r_oP||r_oN

(2)

The open-loop DC gain is given by A_ol = A_inpA_out, the gain bandwidth product by

GB = (1/2π)(g_mb/C_c)

(3)

The high frequency output pole is given by

f_poutHF = (1/2π)(g_moutP + g_moutN)/C_L

(4)

The high frequency zero is given by

f_zHF = (1/2π)(1/((1/(g_moutP + g_moutN) − R_c) C_c))

(5)

Resistor R_s is used for phase lead compensation to improve the phase margin of the FD-DDA. It generates a zero f_zlead in the transfer function with a value.

f_zlead = (1/2π)(1/R_sC_L)

(6)

4. Results

The buffer of Figure 1c using the FD-DDA circuit of Figure 5 was laid out and simulated in a commercial 180 nm CMOS technology using unit PMOS and NMOS transistor sizes W/L = 15 µm/0.4 μm. Ib = 60 nA. Some transistors are scaled by a factor two as shown by the “x2” in the schematic of Figure 5. Dual supply voltages VDD = 0.3 V, VSS = −0.3 V, C_L = 50 pF, R_s = 10 kΩ, C_c = 0.5 pF and R_c = 10 MΩ were used. Rlarge resistors were implemented with two PMOS transistors in series with dimensions 2 µm/0.2 µm. Compensation resistors R_c were implemented as shown in Figure 5 with the parallel combination of a PMOS and an NMOS transistor with dimensions W = 0.5 µm/1 µm.

Figure 6 shows the layout of the FD-DDA with dimensions 45.5 × 135.2 µm². Figure 7 shows the open-loop response of the FD-DDA It has a DC open-loop gain A_olDC = 86.77 dB, a unity gain frequency f_u = 88.1 kHz and a phase margin PM = 65.47°. Figure 8 shows the AC response of the buffer. It has a bandwidth BW = 172.91 kHz, with 0.556 dB peaking.

Figure 9 shows the transient response of the output waveforms V_out, V_outp and of the load capacitor currents I_CL, I_CLP to a 10 kHz, 0.4 V_PP input pulse. It can be seen that the peak positive and negative currents have values I_pkpos = 6 µA and I_pkneg = −4.6 μA, and the buffer has a symmetrical slew rate SR+ = SR− = 0.238 V/µs. These currents are essentially larger than the output quiescent current I_outQ = 60 nA and than the total FD-DDA quiescent current I_totQ = 1.12 μA. A conventional class A DDA would have a peak negative output current of I_pk = IoutQ = 60 nA and would be characterized by an essentially lower slew rate of only SR− = 0.0012 V/µs.

Other performance parameters obtained from simulations include: total quiescent power dissipation P_totQ = 0.666 μW, input noise spectral density at 1 kHz and RMS noise values 1.1 uV/√Hz and 0.34 mV_RMS, respectively. RMS noise was obtained by integrating noise spectral density over the noise bandwidth. CMRR = 102 dB, PSRR+ = 109 dB, PSRR− = 100 dB, input DC offset voltage V_os = 3.5 mV. V_os was obtained including typical 2% transistor W/L mismatches. The small signal and large signal figures of merit of the proposed FD-DDA are FOMss = GBC_Ltot/P_Q = 12.69 MHzpF/µW. FOM_LS = SRC_Ltot/P_Q = 34.79 (V/μs)pF/µW. The current efficiency is CE = I_outtotpk/I_totQ = 8.9. Total harmonic distortion is THD = 0.09% for a 10 kHz 0.2 V_PP and 10 kHz sinusoidal input signal.

Table 1. Corner simulations at T = 90 °C.

	tt	ss	ff	fs	sf
fu (kHz)	76.2	75.7	73.4	73.9	76.2
AOLDC (dB)	72.8	77.5	56.2	59.3	75.8
PM	65.1°	64.7°	66.2°	65.2°	65.4°
CMRR (dB)	141	138	116	123	147
PSRR (dB)	81	101	70.4	71.4	76.6
Slew Rate (v/μs) positive	0.25	0.22	0.24	0.24	0.23
Slew Rate (v/μs) negative	0.248	0.22	0.24	0.24	0.23

,

Table 2. Corner simulations at T = 27 °C.

	tt	ss	ff	fs	sf
fu (kHz)	119.6	120.4	120.2	120.9	112.7
AOLDC (dB)	85.3	81.6	84.1	84	83.6
PM	62.6°	63.5°	62.5°	62.9°	62.7°
CMRR (dB)	171.5	130	148	139.2	148
PSRR (dB)	97	75	112.4	84.6	75
Slew Rate (v/μs) positive	0.25	0.22	0.24	0.24	0.23
Slew Rate (v/μs) negative	0.248	0.22	0.24	0.24	0.23

and

Table 3. Corner simulations at T = −10 °C.

	tt	ss	ff	fs	sf
fu (kHz)	135.36	95.5	143.9	105	139.2
AOLDC (dB)	71.3	52	88	62	79.6
PM	65°	75°	62.6°	73.4°	63.4°
CMRR (dB)	126	105	157	121.7	141
PSRR (dB)	70	40	91	52	96
Slew Rate (v/μs) positive	0.20	0.14	0.29	0.23	0.13
Slew Rate (v/μs) negative	0.20	0.14	0.29	0.23	0.13

show corner simulations of parameters at three temperatures spanning a 100 °C range.

Table 4. Comparison table of proposed circuit to recently published bulk-driven op-amps.

Parameter Year Sim/Exp	This Work Sim	[19] 2022 Sim	[18] 2021 Exp	[17] 2020 Exp	[16] 2020 Exp	[15] 2019 Exp	[14] 2016 Exp	[13] 2015 Exp	[12] 2013 Sim	[11] 2016 Exp
Vsupply (V)	0.6	0.5	0.5	0.25	0.3	0.3	0.5	0.4	1	0.7
Technology (μm)	0.18	0.18	0.18	0.065	0.18	0.18	0.18	0.05	0.35	0.18
Power Dissipation (μW)	0.684	0.312	0.0455	0.026	0.0126	0.022	0.07	31.84	197	22.4
CL (pF) total	50 × 2	15	15	15	30	20	40	20 × 2	15	20
GB (MHz)	0.0868	0.0128	0.0075	0.0095	0.00296	0.00185	0.004	2.31	11.67	3
SR+/SR− (V/μs)	0.238	0.0158/0.0135	-	0.002/0.002	0.0019/0.0064	0.00165/0.00135	0.002/0.002	1.2	2.53/1.37	1.8/3.8
CMRR (dB)	102	60	85.7	62.5	110	82	55	92	40	19
PSRR+/PSRR− (dB)	109/ 100	66	68.1	38	56	57	52	64	40/46.8	52.1
Input noise spectral density ($\mathsf{\mu }\mathrm{V}/\sqrt{\mathrm{Hz}}$)	1.1 @ 1 kHz	0.88	0.65 @ 1 kHz	-	1.6	2.58	-	0.164 @ 10 kHz	0.06 @ 1 MHz	0.1@ 1 MHz
FOMSS (MHz.pF/μW)	12.69	0.614	2.5	5.48	7.047	1.68	2.28	2.88	0.88	2.67
FOMLS ((V/µs).pF/μW)	34.79	0.647	2.76	1.15	4.52	1.22	1.14	1.5	0.10	1.60
Total Harmonic Distortion (%)	0.09 @ 1 kHz, 0.2 VPP	0.28	1% @ 0.46 VPP	-	-	-	-	-	-	0.2 @ 100 kHz 400 mVPP
Input offset (mV)	3.2	6.14	2.3	-	3.2	4.73	4 (average)	-	8.4,10	11
Single-Ended/Fully differential	FD	SE	SE	SE	SE	SE	SE	FD	SE	SE

Remarks: (a) Given that the minimum of the rising and falling slew rates (SR+ and SR−) limits the large signal speed of an amplifier, calculation of FOM_LS was performed using the minimum of the two slew rates values min{SR⁺, SR⁻}. (b) For fully differential (FD) amplifiers, the total load capacitance CLtot = 2xCLwas used to calculate FOM_SS and FOM_LS.

summarizes and compares the performance characteristics of the proposed op-amp and buffer to recently reported bulk-driven low-voltage circuits [11,12,13,14,15,16,17,18,19]. It can be seen that the proposed circuit has the highest small and large signal figures of merit.

5. Conclusions

A high performance true fully differential bulk-driven buffer operating from ±0.3V dual supply voltages is presented. A fully differential class AB Miller op-amp with differential–difference input stage is used to implement the buffer. A high CMRR no-tail bulk-driven cascoded pseudo-differential cell is used in the input stage and in the common mode feedback network of the op-amp. The circuit was verified with simulations in a commercial 180 nm CMOS technology.