An Approach for a Wide Dynamic Range Low-Noise Current Readout Circuit

Round 1

Reviewer 1 Report

The paper is well written, the proposed architecture suits the low-current application. I have a few questions.

(1) The current amplification stage has a trans-impedance gain and thus an input referred current noise. Please explain how this noise is reduced to 10fA level. Why the main integration stage have a large gain and reduce its noise to 10fA level, avoiding using the previous current amplification stage(s)? 

(2) In high frequency band current amplification, the KT/C noise from resetting capacitor will play any role in the total noise? How this noise is minimized?

(3) Fig. 14, the input referred noise density has a positive relationship with frequency, it is due to the integrator 1/sC gain? Why this curve looks not very linear when the frequency and gain are both logarithmic?

(4) The references in benchmarking table is not very up to date, please consider to add more recent papers from important conferences, for example ISSCC/VLSI/CICC/ASSCC/ESSCIRC/BioCAS. 

Author Response

We want to first thank all the reviewers for their time to review our manuscript even under the current pandemic. We have addressed their concerns individually in an itemized form below. We have also made changes in the main manuscript based on reviewers’ comments. The changes are highlighted in the manuscript.

Thank you,

Authors

 

 

 

The paper is well written, the proposed architecture suits the low-current application. I have a few questions.

(1) The current amplification stage has a trans-impedance gain and thus an input referred current noise. Please explain how this noise is reduced to 10fA level. Why the main integration stage have a large gain and reduce its noise to 10fA level, avoiding using the previous current amplification stage(s)?

Thank you for the question.

The input-referred current noise mainly comes from the pre-amplification stage and the noise from the integration stage has been attenuated due to the high current gain of the pre-amplification stage.  For example, with a current gain of 1000 from the pre-amplification stage, the current noise contribution from the integrator is attenuated by 1000 times.

The input-referred current noise of the front stage amplifier as in Fig. 10 is very small in the low-frequency range as in Equation (5) on page 7.

The low input current flowing through the feedback transistors bring a large feedback resistance, and the input noise current is inversely proportional to the feedback resistor. Therefore, the current noise floor can be as low as 10fA/sq(Hz).

 

 

(2) In high frequency band current amplification, the KT/C noise from resetting capacitor will play any role in the total noise? How this noise is minimized?

 

Thank you for the question.

The input referred noise from the integration stage has been attenuated by 1000 times due to the front current gain stage. Therefore, the noise contribution from the integration is minimal.

The information is added on page 8.

 

(3) Fig. 14, the input referred noise density has a positive relationship with frequency, it is due to the integrator 1/sC gain? Why this curve looks not very linear when the frequency and gain are both logarithmic?

 

Thank you for the question.

The integrator 1/sC has minimal contribution on the input referred noise. In Fig. 14, in the range of 10Hz to 1MHz, the input referred noise is mainly from flicker noise, thermal noise from the pre-amplification stage, and the shot noise from the feedback transistor, all of these factors contribute the noise shape in that frequency range.

 

• The references in benchmarking table is not very up to date, please consider to add more recent papers from important conferences, for example ISSCC/VLSI/CICC/ASSCC/ESSCIRC/BioCAS.

Thank you for the suggestion. Reference 16(ESSCIR 2017) and reference 17 (ISSCC 2018) have been added in the table on page 9.

Reviewer 2 Report

This paper presents an interesting low-noise current readout circuit with a large dynamic range. It uses an already published quite interesting structure, not widely known by the community, based on a double-MOS architecture around an amplifier. The authors feature this system with a large dynamic range by a programmable current gain. In order to deal with the parasitic capacitances of the switches in the programmable gain system, the authors propose a novative T-network switch architecure that is also quite interesting.

The whole system is terminated by a clock-less sigma-delta modulator to provide a numerical output of the sensed current. The priciple is validated through simulation and compared to other published works.

The paper is easy to read, and deserves to be published. However, it needs some improvements in order to be fully valuable for the scientific community.

1) The programmable refence current stage used in the sigma-delta modulator, and presented in section 2.6, is described every shortly and difficult to understand. The authors need to improve the description or to give the appropriate references for the reader to find the right information allowing him to understand the way this sub-circuit works.

2) Idem, in section 2.8, although the comparator structure with hysteresis is a well known architecture, please provide a reference for "young" readers...

3) In section 2.9, please indicate the different sub-circuits location on the layout of figure 12.

4) The main improvement to bring to this paper is on simulation results. The authors never consider the effect on fabrication dispersion on the performance of their current readout circuit. It is mandatory to discuss the effect of any mismatch in the double-MOS / capacitor feedback structure sued to set the current gain, and the effect of any offset in the amplifier. At least Monte-Carlo simulations have to be provided. Note that the authors use a dummy transistor for matching... So matching has to be discussed.

5) In addition, the authors have to point out that in Table 3, they compare their work to experimental results published in the litterature while the performances they announce for their circuit is based on simulations.

Author Response

We want to first thank all the reviewers for their time to review our manuscript even under the current pandemic. We have addressed their concerns individually in an itemized form below. We have also made changes in the main manuscript based on reviewers’ comments. The changes are highlighted in the manuscript.

Thank you,

Authors

 

Review 2:

 

This paper presents an interesting low-noise current readout circuit with a large dynamic range. It uses an already published quite interesting structure, not widely known by the community, based on a double-MOS architecture around an amplifier. The authors feature this system with a large dynamic range by a programmable current gain. In order to deal with the parasitic capacitances of the switches in the programmable gain system, the authors propose a novative T-network switch architecure that is also quite interesting.

The whole system is terminated by a clock-less sigma-delta modulator to provide a numerical output of the sensed current. The priciple is validated through simulation and compared to other published works.

The paper is easy to read, and deserves to be published. However, it needs some improvements in order to be fully valuable for the scientific community.

1) The programmable refence current stage used in the sigma-delta modulator, and presented in section 2.6, is described every shortly and difficult to understand. The authors need to improve the description or to give the appropriate references for the reader to find the right information allowing him to understand the way this sub-circuit works.

Thank you for the suggestion.

We have added the following text and Fig. 10 on page 6 and 7. The cited paper of this design is from No. 16 in reference.

“We use a simple divide by 2 circuit to explain the operation of this circuit. For a long-channel transistor, the drain current is proportional to the channel size W/L. Based on this statement, in Figure 10(a), the transistor M_0 with size W/L is equivalent to the four identical transistors M01, M02, M03, and M04, with same size W/L in series-parallel configuration. The current I splits equally through each of the four transistors. Transistor M01 and M02 can be simplified as an equivalent transistor M012 with a size of 2W/L. In Figure 10(b), the transistor based current split architecture by a factor of 2 is shown. Different scaled current can be obtained from different transistor size ratio as shown in Table 2.”

 

2) Idem, in section 2.8, although the comparator structure with hysteresis is a well known architecture, please provide a reference for "young" readers...

 

Thank you for the suggestion.

Reference source No. 17 is added.

 

3) In section 2.9, please indicate the different sub-circuits location on the layout of figure 12.

 

Thank you for the suggestion.

It is updated in Fig. 13.

 

4) The main improvement to bring to this paper is on simulation results. The authors never consider the effect on fabrication dispersion on the performance of their current readout circuit. It is mandatory to discuss the effect of any mismatch in the double-MOS / capacitor feedback structure sued to set the current gain, and the effect of any offset in the amplifier. At least Monte-Carlo simulations have to be provided. Note that the authors use a dummy transistor for matching... So matching has to be discussed.

 

Thank you for the suggestion.

For the current gain of 1000, a 10-bit resolution is required for the matching. For the standard process, it is easy to achieve with the transistor and capacitor with large size.

The offset of the amplifier is minimized by using a pre-amplification stage with large input transistor size (200/0.5) as in Figure 10.

Monte Carlo simulations would be a good idea. There is already a good reference with actual silicon measurement in reference paper No. 14 which proves that the accurate current gain can be obtained by using large transistor and capacitor size.  Due to university closing, and main author Wei having graduated from Tufts, performing Monte Carlo simulations would be quite challenging. Given there is well known reference, we believe providing a reference would be adequate.

 

We have added offset issue page 7.

“The pre-amplification stage provides a gain of 4 with 13 MHz 3-dB bandwidth to reduce the noise and offset from the subsequent stage.”

 

5) In addition, the authors have to point out that in Table 3, they compare their work to experimental results published in the litterature while the performances they announce for their circuit is based on simulations.

Thank you for the suggestion.

We noted the simulation result besides the table.

 

Reviewer 3 Report

The paper deals with an approach for the design of a low noise current readout circuit for low noise current.

I believe that is should be made clear (or clearer)  starting with the title and the abstract, that the device being discussed has not been fabricated and that results, so fare, are only those obtained from post layout simulations. I would therefore suggest to modify the title into something like “An approach for wide dynamic range etc…”. 

This fact should also be emphasized in table 3, where simulation results from the paper are compared to measured results on actual devices. A row should be added specifying “Measured” for all referenced works (4,5,16,17,18) and “Simulated” in the case of “This work”.

While a reference ([14]) is provided, the operation of the circuit in Fig. 1 could be more clearly explained. In particular, please revise the statement at line 43 “The node Vout could connect….”: as far as I can understand,  vout MUST be connected to a node with potential exactly equal to Vcm for the circuit to work.

It is not clear how the authors define the dynamic range for their circuit. If I understand correctly, the claim is that by changing the gain of the first two stages, one can change the maximum input current for saturation. At the same time, by setting a high gain, one can reduce input noise and increase sensitivity. However, since changing the gain also changes the equivalent noise level at the input, it is not obvious what should be taken as the dynamic range of the system.  Usually one defines the dynamic range for an amplifier (at given gain and bandwidth ) as the ratio between the maximum input and the integrated (over the bandwidth)  equivalent input noise.  In principle there is, therefore, a different dynamic range for any different gain setting, which makes sense in those cases, some of which have been referenced by the authors themselves, in which one wants to quantify the ability to maintain high sensitivity coupled to a large DC linear range ( i.e. the ability to detect small changes of the input superimposed to a large value).  Figure 16 does not help in understanding how the estimation of the Dynamic range was made. Moreover, Fig. 16, Fig. 15 and the data reported in table 3 do not appear to be consistent among themselves. With a bandwidth of 1.1 MHz (Table 3), the minimum integrated noise (at the highest gain) is about 1 nArms (figure 15). However, Fig. 16 is used to state that the minimum detectable current is 100 pA. This is quite confusing and need to be clarified. More precisely, since the claim of high dynamic range is the most important claim of the paper and since we are dealing with simulations, all aspects related to the definition and to the estimation of the dynamic range must be discussed in full and in detail before one can begin to discuss the actual merits and the relevance of approach proposed by the authors.

Author Response

We want to first thank all the reviewers for their time to review our manuscript even under the current pandemic. We have addressed their concerns individually in an itemized form below. We have also made changes in the main manuscript based on reviewers’ comments. The changes are highlighted in the manuscript.

Thank you,

Authors

 

Reviewer 3:

The paper deals with an approach for the design of a low noise current readout circuit for low noise current.

 

I believe that is should be made clear (or clearer)  starting with the title and the abstract, that the device being discussed has not been fabricated and that results, so fare, are only those obtained from post layout simulations. I would therefore suggest tomodify the title into something like “An approach for wide dynamic range etc…”.

Thank you for the question.

We have modified the title to “An approach for wide dynamic range low-noise current readout circuit”.

The text “The circuit has been verified using post-layout simulations.” has been added in abstract on page 1.

 

This fact should also be emphasized in table 3, where simulation results from the paper are compared to measured results on actual devices. A row should be added specifying “Measured” for all referenced works (4,5,16,17,18) and “Simulated” in the case of “This work”.

Thank you for the question.

The simulation information is added below the table on page 9.

 

While a reference ([14]) is provided, the operation of the circuit in Fig. 1 could be more clearly explained.

Thank you for the suggestion.  The text is modified on page 2.

 

 

In particular, please revise the statement at line 43 “The node Vout could connect….”: as far as I can understand,  vout MUST be connected to a node with potential exactly equal to Vcm for the circuit to work.

Thank you for the suggestion.  The text is modified as following on page 2:

“The  node Vout  connects to the negative input node of a following TIA or integrator stage which keeps Vout at the exactly same voltage potential as node Vin or Vcm. ”

 

It is not clear how the authors define the dynamic range for their circuit. If I understand correctly, the claim is that by changing the gain of the first two stages, one can change the maximum input current for saturation. At the same time, by setting a high gain, one can reduce input noise and increase sensitivity. However, since changing the gain also changes the equivalent noise level at the input, it is not obvious what should be taken as the dynamic range of the system.  Usually one defines the dynamic range for an amplifier (at given gain and bandwidth ) as the ratio between the maximum input and the integrated (over the bandwidth)  equivalent input noise.  In principle there is, therefore, a different dynamic range for any different gain setting, which makes sense in those cases, some of which have been referenced by the authors themselves, in which one wants to quantify the ability to maintain high sensitivity coupled to a large DC linear range ( i.e. the ability to detect small changes of the input superimposed to a large value). 

 

Thank you for the comment. We understand the confusion from our claims. For us the dynamic range is defined as the range of input signals that can be processed by the circuit with noise limiting at the lower end and saturation limiting at the higher end.

We use a pre-amplification stage to amplify the low current signal, while for large current signal, we reduce the gain from pre-amplification stage. This programmable gain allows us to scale the current levels on the higher end. The low levels of current that can be detected is still limited by the noise level.

Other papers can either detect a wide dynamic range but a long operation time is required or detect a small dynamic range with a fast operation time. Our solution is for a wide dynamic range detection with fast operation using a programmable gain setting.

We have added the following text on page 2.

“The high current amplification gain allows for a fast operation for smaller values of current. On the other hand, lower amplification will avoid the integration stage from saturation for large input current levels.  The variable current gain allows a wide range input current dynamic range.”

 

Figure 16 does not help in understanding how the estimation of the Dynamic range was made. Moreover, Fig. 16, Fig. 15 and the data reported in table 3 do not appear to be consistent among themselves. With a bandwidth of 1.1 MHz (Table 3), the minimum integrated noise (at the highest gain) is about 1 nArms (figure 15). However, Fig. 16 is used to state that the minimum detectable current is 100 pA. This is quite confusing and need to be clarified. More precisely, since the claim of high dynamic range is the most important claim of the paper and since we are dealing with simulations, all aspects related to the definition and to the estimation of the dynamic range must be discussed in full and in detail before one can begin to discuss the actual merits and the relevance of approach proposed by the authors.

Thank you for the question.

The minimal detectable current signal is inversely proportional to the signal bandwidth. In Fig. 15, for example, with 1000× current gain, the integrated noise is about 1nArms at 1MHz. Therefore, the minimal detectable 1MHz current signal is slightly larger than 1nA. If the current signal frequency is 10Hz, the integrated noise is around 100fA, so the minimal current detection level approximately 100fA range. All the other reference papers have similar results.

 

We added the frequency information on page 8.

“In Figure 16, sinusoidal signals of amplitude of 100fA(10Hz), 1 nA(1KHz), and 1uA (1MHz) are used as the input signal, respectively, and results show that recovered signal matches well with the input signal.”

 

Author Response File: Author Response.docx

Round 2

Reviewer 2 Report

The paper can now be published as is.

Author Response

Thank you. 

Reviewer 3 Report

While in the response to my comments on the previous version of the manuscript the authors essentially accept all my observations, the content of the modified paper still remains problematic in my view. Some of the statements added in order to address the issues I had risen do not really help.
For instance:
"The programmable current gains setting enables one to achieve a wide input dynamic range while achieving low-noise performance. The high current amplification gain allows for a fast operation for smaller values of current. On the other hand, lower amplification will avoid the integration stage from saturation for large input current levels. The variable current gain allows a wide range of input current dynamic range."
The first statement was also present in the previous version and I believe that it is not an accurate description of the work that has been done. The claim still appears to be that high dynamic range and low noise are obtained at the same time, while, as the authors themselves agree in their response to my objection, their configuration allows, depending on the gain, to obtain either low noise (with reduced dynamic range), or high dynamic range (with increased noise) which is a quite different thing and, I may add, nothing new in itself since in almost any conceivable current measuring circuit it is possible to add programmability in order to trade dynamic range for low noise. The statements in the new version, that should be a clarification in the intentions of the authors, appear to be quite obscure to me.
It is my strong position that the fact that what is being done is trading low noise for dynamic range must be absolutely clear. This aspect is not yet sufficiently clear in the new version of the manuscript.
The authors, moreover, clearly state (in their response to my review) that they indeed define the dynamic range as the maximum input signal at the lowest gain divided by the input noise at the highest gain. At the very least, the authors should clearly state, somewhere in the paper, their own definition of dynamic range, otherwise they are suggesting something different from what is being really done. Indeed, the sentence they added to supposedly clarify this aspect reads:
“The high current amplification gain allows for a fast operation for smaller values of current. On the other hand, lower amplification will avoid the integration stage from saturation for large input current levels. The variable current gain allows a wide range of input current dynamic range.”
This statement does not clarify the definition of dynamic range as used in the paper and it merely states the obvious, that is the fact that with a programmable gain, the overall range of input signals is large, with the dynamic range (in the most commonly accepted definition) remaining the same for any given value.
Table 3 in the new version includes a new parameter “Maximum data processing operation improvement” that, unless I am mistaken, is not defined anywhere in the paper. Since the authors list a factor “1000” with respect to the other referenced design, they should at least clarify what this parameter represents.
As a final major remark, there appears to be quite a lot of confusion in the use of the terms “signal frequency” and “signal bandwidth”. In the response to my observations, the author state:
“The minimal detectable current signal is inversely proportional to the signal bandwidth. In Fig. 15, for example, with 1000× current gain, the integrated noise is about 1nArms at 1MHz. Therefore, the minimal detectable 1MHz current signal is slightly larger than 1nA. If the current signal frequency is 10Hz, the integrated noise is around 100fA, so the minimal current detection level approximately 100fA range. All the other reference papers have similar results.”
I really do not understand what is being stated in the previous sentence. In any case, it is still not clear how Fig. 16 is obtained (for instance what was the gain setting?).

Author Response

The rely is in the doc file. 

Author Response File: Author Response.pdf

Round 3

Reviewer 3 Report

While I sill maintain a few doubts on some of the choices made by the authors in defining some relevant figures of merit, I must recognize that in this version of the paper they have made an effort to clarify how some crucial parameters (such as dynamic range) are defined and used in their work. 

I have no longer strong objections to the publication of the paper: any informed reader can now evaulate for himself the relevance of the work that has been done.  

I would however advice the authors to revise Fig. 16. If my understanding is correct, the x axis is the measurement bandwidth and therefore it should be marked "bandwidth" rather than "frequency" as it is done at present.