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Open AccessArticle

An Approach for a Wide Dynamic Range Low-Noise Current Readout Circuit

Department of Electrical and Computer Engineering, Tufts University, 161 College Ave, Medford, MA 02155, USA
*
Author to whom correspondence should be addressed.
J. Low Power Electron. Appl. 2020, 10(3), 23; https://doi.org/10.3390/jlpea10030023
Received: 14 May 2020 / Revised: 19 July 2020 / Accepted: 27 July 2020 / Published: 29 July 2020

Abstract

Designing low-noise current readout circuits at high speed is challenging. There is a need for preamplification stages to amplify weak input currents before being processed by conventional integrator based readout. However, the high current gain preamplification stage usually limits the dynamic range. This article presents a 140 dB input dynamic range low-noise current readout circuit with a noise floor of 10 fArms/sq(Hz). The architecture uses a programmable bidirectional input current gain stage followed by an integrator-based analog-to-pulse conversion stage. The programmable current gains setting enables one to achieve higher overall input dynamic range. The readout circuit is designed and in 0.18 μm CMOS and consumes 10.3 mW power from a 1.8 V supply. The circuit has been verified using post-layout simulations.
Keywords: dynamic range; low-noise current amplification; programmable gain dynamic range; low-noise current amplification; programmable gain

1. Introduction

There is a growing need to sense very low levels of current in many biosensors and diagnostics applications [1,2,3]. Current levels in such applications can be as low as picoamperes (pA) which are harder to detect using CMOS circuitry due to circuit noise. Several readout circuits have been developed for low current sensing. For example, an integrator or a transimpedance amplifier (TIA) has been employed to convert the current signal into a voltage signal, followed by quantization of the converted voltage signal. However, with the current in the pA range, if the integration method is adopted, it would take a long time to accumulate the small current into measurable voltage signal [4]. If a TIA is employed, the feedback resistance must be large enough (i.e., gigaohms range) to obtain high gain and there is a trade-off between achieving high dynamic range and achieving low input-referred current noise. Moreover, such a large feedback resistor cannot be reliably realized on-chip and must be externally connected. A high-value active pseudo resistor made using off-state transistors have been widely used for small current sensing [5,6,7,8]. However, the resistance is inversely proportional to the input current, which leads to a variable current gain and bandwidth applications [9].
In most applications, the small current signal needs to be amplified at high speed in bandwidths excess of 1 MHz. One such application is for nanopore sensing where the transient activity is in microseconds with Femto ampere current levels. A current conveyor is commonly employed for current amplification; however, the conventional current conveyor is not suitable for the small current amplification since the bias current of the conveyor leads to large input-referred current noise [10,11]. No-bias current conveyor has been adopted for low-noise current sensing [12]. The noise levels achieved may still be prohibitive for low current sensing. A current preamplifier was presented, featuring a matched double-MOS architecture around an amplifier to obtain current amplification in [13]. Capacitors with the same current ratio are needed to increase the bandwidth. The fixed current amplification gain leads to a smaller dynamic range. In this paper, a current preamplifier with a programmable gain is proposed to obtain bidirectional current amplification. The programmable current gains setting enables one to achieve a higher overall input dynamic range. Higher gain allows for faster operation for small input currents while lower gain avoids saturation of the integrator stage for large input currents. Thus, the variable current gain enables a wider input dynamic range. Note the input dynamic range is defined as the ratio of the largest to the smallest input signal that the circuitry can process. For a programmable gain amplifier, the dynamic range will be measured as a ratio of highest input signal level (at lowest gain setting) and the largest referred input noise ever measured for any of the gain settings. A pulse width modulation output stage provides a digital output without the need for clock. The circuit is designed in a 0.18 μ m CMOS process and validated using post-layout simulations.

2. Low-Noise Current Readout Architecture

2.1. Current Amplification

Floating current mirror is utilized to realize high current gain for amplifying weak current levels [13]. In Figure 1, transistor M N 1 and M P 1 are connected across the feedback loop of the amplifier. Transistor M N 2 and M P 2 are connected to the output node V x . The node V o u t connects to the negative input node of a following TIA or integrator stage which keeps V o u t at the exact same voltage potential as node V i n or V c m . Therefore, transistors M N ( P ) 1 and M N ( P ) 2 have the same V g s and V d s . The input current flows in or out through M N 1 or M P 1 , depending on the polarity of the current signal. Transistors M N 2 and M P 2 are sized N times as M N 1 and M P 1 , respectively. Therefore, the current through M N 2 or M P 2 is N times the input current signal. The capacitor C 1 and C 2 have the same ratio of N for high frequency current amplification as in Equation (1).
( W L ) M P 2 ( W L ) M P 1 = ( W L ) M N 2 ( W L ) M N 1 = C 1 C 2 = N
This architecture has the advantage that it provides high current gain so that the input-referred current noise at the input node from the following TIA or integrator is attenuated by the high current gain of this preamplification stage. However, this fixed high current gain would saturate the following TIA or integrator stage when the input current signal is large. The maximum input current is limited to the tens of nA range. In this paper, we design a programmable current preamplification stage to extend the input current signal range. This allows one to trade-off noise performance with a high dynamic range.

2.2. Programmable Gain Current Amplifier Stage

To allow processing of wide range (100 fA − 1 μ A) current signals, the gain of the current amplifier is designed to be programmable, and the gate control voltage of transistor M N ( P ) 1 and M N ( P ) 2 can be externally tuned to adjust to the different range of input currents. Two cascade current gain stages are implemented for a maximum of 1000×. This is designed to amplify currents as low as 100 fA. The first stage offers a maximum current gain of 50, while the second stage provides a maximum current gain of 20. The effective capacitor ratio and the effective transistor ratio are programmable to achieve different current gain for a high dynamic input current range as in Table 1.

2.3. Low-Frequency Gain Setting

The programmable low-frequency current amplification ratio is achieved by turning on or off the mirroring transistors M N 2 and M P 2 in Figure 2. For the first current gain stage, there are a total of 50 sets of transistors-based current mirrors for low-frequency current signal amplification. Let us consider one example. For a gain of 10, the gates of the 10 NMOS transistors M N 2 connect to V B N 1 , while the gates of the remaining 40 NMOS transistors M N 2 connect to G n d ; the gates of the 10 PMOS transistors M P 2 connect to V P N 1 , while the gates of the remaining 40 PMOS transistors M P 2 connect to V d d .

2.4. High-Frequency Gain Setting

The high-frequency programmable gain is obtained by setting the feedback capacitor units. For the first current amplification stage, there are a total of 50 cells of feedback capacitors controlled by the switches in the feedback loop as in Figure 3. The switches are large to reduce the on-resistance. However, the large size switch increases the parasitic capacitance that reduces the accuracy of the high-frequency gain. For example, if a gain of 10 is selected, then the first stage enables 10 capacitors by turning on the 10 switches coupling to the capacitors. The remaining 40 switches are turned off. However, the switches from the disabled paths will still add to the parasitic capacitance in parallel with the feedback capacitors, which provide a signal path for the high-frequency signal as in Figure 4. Consequently, this will influence the gain at high frequency. The problem is exaggerated when two gain stages are cascaded.
To solve this problem, we realize a T-network using two capacitors connecting in series as the feedback capacitor and move the switch between their intermediate node V c and ground as in Figure 5. When the feedback path is enabled, the switch is off, presenting a high impedance node at V c , the high-frequency signal can go through the feedback path. The two feedback capacitors connecting in series form equivalent feedback C as in Figure 6. When the feedback path is disabled, the switch is on presenting a low impedance node at V c , the high-frequency signal has a path to ground, without passing through the feedback path as in Figure 7. This implementation is more stable (better phase margin) compared to conventional implementation as in Figure 4. Note that the NMOS switch is not in the high-frequency signal path when the high-frequency signal gain is enabled, therefore, the size of the NMOS switch can be designed with small size introducing minimal parasitic capacitance. There is also no issue of parasitic capacitance when certain feedback paths are disabled. A dummy disabled NMOS switch is connected at node V D for matching. The programmable low-frequency and high-frequency current gain provide an accurate amplification over a large input current dynamic range and over a large bandwidth.

2.5. System Architecture

The readout system is composed of two current amplification stages, an integrator stage, and a pulse width modulation stage as shown in Figure 8. Two current amplification stages are cascaded to reduce the number of current mirrors. The amplified current flows into a first-order clock-less sigma-delta modulator. This works similarly to the self-resetting integrator stage that generates an output pulse width and frequency-dependent on the value of the input current [14]. If the control bit C is 1, then the current reference at the upper side is on, and the current reference at the lower side is off. The total current flowing into the integrator is 1000 I i n + I R E F . If the control bit C is 0, then the current reference at the upper side is off, and the current reference at the lower side is on. The total current flowing into the integrator is 1000 I i n I R E F . The voltage V P at the output node of the integrator compares with the reference voltage V R E F P and V R E F N . Once V P crosses the voltage window( V R E F N V P V R E F P ), the control bit signal C changes its polarity, which alters the direction of the reference current.
V T h r e s h o l d C I N T = T 1 ( 1000 I I N + I R E F )
V T h r e s h o l d C I N T = T 2 ( 1000 I I N I R E F )
I i n = I R E F ( T 1 + T 2 ) 1000 ( T 2 T 1 )
From Equations (2)–(4), utilizing charge conservation, one can show that the input current can be obtained from the pulse width of the control signal C.
The programmable low-frequency current amplification ratio is achieved by turning on or off the mirroring transistors M N 2 and M P 2 . For the first current gain stage, there are a total of 50 sets of the transistors-based current mirrors for low-frequency current signal amplification and 50 sets of capacitors for high-frequency current signal amplification, respectively as in Figure 8. When the gain of 10 of the first stage is selected, for example, the gates of the 10 NMOS transistors M N 2 connect to V B N 1 , while the gates of the remaining 40 NMOS transistors M N 2 connect to G n d ; the gates of the 10 PMOS transistors M P 2 connect to V B P 1 , while the gates of the remaining 40 PMOS transistors V B P 2 connect to V d d . For the high-frequency gain, 10 sets of NMOS switches of the capacitor in the red box connect to G n d , and the remaining 40 sets of the NMOS switches of the capacitor connected to V d d .

2.6. Programmable Reference Current Stage

To allow for a wide dynamic range at the input, the reference current feeds the clockless delta-sigma modulator (aka pulse width modulation stage). The reference current stage provides a selection of reference currents to the wide range input current signal. The tiny reference current is obtained by the current splitter architecture as in Figure 9 [15]. The attenuation gain is 10 in this design. The R2R topology provides the same V g s voltage, so the current flowing in or out of this circuit will be linearly divided into two parts, according to the transistor size. Different scaled currents can be obtained from different transistor size ratios as in Table 2.
We use a simple divide-by-2 circuit to explain the operation of this circuit as in Figure 10. For a long-channel transistor, the drain current is proportional to the channel size W / L . Based on this statement, in Figure 10a, the transistor M 0 with size W / L is equivalent to the four identical transistors M 01 , M 02 , M 03 , and M 04 , with same size W / L in a series-parallel configuration. The current I splits equally through each of the four transistors. Transistor M 01 and M 02 can be simplified as an equivalent transistor M 012 with a size of 2 W / L . Therefore, in Figure 10b, the transistor-based current split architecture by a factor of 2 is shown.

2.7. Amplifier

The low-noise amplifier composes of a low gain pre-amplification stage and a miller compensation amplifier stage as in Figure 11. The pre-amplification stage provides a gain of 4 with 13 MHz 3-dB bandwidth to reduce the noise and offset from the subsequent stage. The open-loop DC gain is 95 dB, unity gain bandwidth is 47 MHz, and the phase margin is 74 .

2.8. Comparator

The comparator is a continuous-time circuit as shown in Figure 12 [16]. The internet positive feedback loop should be larger enough to enable the hysteresis performance. The hysteresis is 40 mV. The reference voltage V R E F P and V R E F N can be adjusted to select the integration voltage window.

2.9. Layout

The entire design is implemented in 0.18 μ m CMOS technology, and the total layout area is 1410 μ m × 720 μ m. The transistors and the capacitors of the current amplification stage consume most of the layout area in Figure 13.

3. Simulation Result

The circuit was simulated with post-layout extraction. This captures the RC parasitic effects in addition to any coupling capacitance. The current gain for wide dynamic range input current and the noise performance are simulated. By controlling the digital codes, the current gain can be programmed to be 1000×, 100×, 10×, and 1× as in Figure 14. The proposed switch connections enable the flat current gain in various current gain settings.
With high current pre-amplification, the input-referred current noise at the input is given by Equation (5). Note that the noise from the integration stage has been attenuated by the current-amplification gain. The feedback transistors and the input stage amplifier dominate the input reference current noise contribution. q I i n is the shot noise from M P ( N ) 1 in Figure 8 operating in the subthreshold region. The voltage noise e n 2 from the op-amp over the input capacitance C i n sets the minimal noise of the circuit when the input current I i n is small.
i e q 2 = q I i n + ( 2 π f C i n ) 2 ( e n ) 2 .
The equivalent input voltage noise from the front-end amplifier is shown in Equation (6). The pre-amplification stage from Figure 10 has a dominant noise contribution. k is Boltzmann constant, and K is a process related constant which influences the flicker noise.
e n 2 = 16 k T 3 g m M P 1 + 2 K W L C o x f + 8 k T ( g m M P 1 ) 2 R .
The noise density and integrated noise simulation are shown in Figure 15 and Figure 16, respectively.
Table 3 lists the integrated noise (rms) with the signal bandwidth of 100 Hz, 10 KHz, and 1 MHz, and with the current gain of 1000×, 100×, 10×, and 1×, respectively. One can choose a fast operation mode for the small input current with some trade-off with the bandwidth, or one can process high bandwidth signal with a slower operation.
In Figure 17, sinusoidal signals of the amplitude of 100 fA (10 Hz), 1 nA (1 KHz), and 1 μ A (1 MHz) are used as the input signal, respectively, and results show that recovered signal matches well with the input signal [14].
Table 4 lists the proposed readout circuit performance and compares it with other recent state-of-the-art demonstrations. We added a new metric to the table; “Speed improvement factor”. It is defined as the improvement in output data rate from the use of variable gain settings. This can be estimated as follows. V T h r e s h o l d is the threshold voltage of the comparator, and C I N T is the integration capacitor. I is the integration current and T x is the integration time for the 1× current gain setting; 1000I is the integration current and T y is the integration time for the 1000× current gain setting. We can write Equations (7) and (8) for these two settings.
I T x = V T h r e s h o l d C I N T
1000 I T y = V T h r e s h o l d C I N T
T y = T x 1000
Equation (9) implies that the circuit can generate the output pulse at a rate 1000 times using the 1000× current gain setting.

4. Conclusions

This paper presents a low-noise current readout circuit using programmable gain setting switches to process a wide input range of currents of 140 dB. The switch arrangement for choosing the programmable gain has been proposed that introduces no phase distortion and it offers flat high-frequency gain. The programmable amplification current stage offers a fast operation of the small current signal and provides a large input dynamic range. The one-bit clockless delta-sigma modulator produces digital output, the input signal is calculated directly from the duty cycle of the pulse output signal. The current amplification enables a higher output data rate for smaller currents. Simulation results in a 0.18 μ m CMOS process to validate the performance.

Author Contributions

Conceptualization, W.W. and S.S.; methodology, W.W. and S.S.; validation, W.W.; formal analysis, W.W. and S.S.; investigation, W.W. and S.S.; resources, W.W. and S.S.; data curation, W.W.; writing—original draft preparation, W.W.; writing—review and editing, S.S.; visualization, W.W. and S.S.; supervision, S.S.; project administration, S.S.; funding acquisition, S.S. All authors have read and agreed to the published version of the manuscript.

Funding

This research received no external funding.

Conflicts of Interest

The authors declare no conflict of interest.

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Figure 1. Bidirectional current amplification.
Figure 1. Bidirectional current amplification.
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Figure 2. Programmable low-frequency current gain stage.
Figure 2. Programmable low-frequency current gain stage.
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Figure 3. Conventional series switch based high frequency current gain stage.
Figure 3. Conventional series switch based high frequency current gain stage.
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Figure 4. Shows a realization of a gain of 10. Off-switches will still contribute to parasitic capacitance affecting the overall gain and stability.
Figure 4. Shows a realization of a gain of 10. Off-switches will still contribute to parasitic capacitance affecting the overall gain and stability.
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Figure 5. Proposed programmable high-gain stage using a T-network.
Figure 5. Proposed programmable high-gain stage using a T-network.
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Figure 6. Current follows through the two feedback capacitor during amplification state.
Figure 6. Current follows through the two feedback capacitor during amplification state.
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Figure 7. Current follows through the ground during off state.
Figure 7. Current follows through the ground during off state.
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Figure 8. Top architecture of the wide dynamic range current readout circuit.
Figure 8. Top architecture of the wide dynamic range current readout circuit.
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Figure 9. Current splitter for programmable reference current generation.
Figure 9. Current splitter for programmable reference current generation.
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Figure 10. Half Current splitting circuit shown in (a) based on the splitting equivalent representation of a single transistor in (b).
Figure 10. Half Current splitting circuit shown in (a) based on the splitting equivalent representation of a single transistor in (b).
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Figure 11. Low-noise amplifier.
Figure 11. Low-noise amplifier.
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Figure 12. Hysteresis comparator.
Figure 12. Hysteresis comparator.
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Figure 13. Current reader layout.
Figure 13. Current reader layout.
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Figure 14. Current gains of 1000×, 100×, 10×, and 1×.
Figure 14. Current gains of 1000×, 100×, 10×, and 1×.
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Figure 15. Input referred noise density of the current reader with the gain of 1000×, 100×, 10× and 1×.
Figure 15. Input referred noise density of the current reader with the gain of 1000×, 100×, 10× and 1×.
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Figure 16. Input-referred integrated noise of the current reader with the gain of 1000×, 100×, 10× and 1×.
Figure 16. Input-referred integrated noise of the current reader with the gain of 1000×, 100×, 10× and 1×.
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Figure 17. Recovered input current.
Figure 17. Recovered input current.
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Table 1. Current gain in each stage.
Table 1. Current gain in each stage.
Total GainFirst Stage GainSecond Stage Gain
1000×50×20×
100×50×
10×10×
Table 2. Table of comparison with relevant architecture.
Table 2. Table of comparison with relevant architecture.
ParameterValue
( W / L ) 1 6 N 1
( W / L ) 7 ( N 1 ) / N
( W / L ) 8 11 ( N 1 ) / N
Table 3. Input referred integrated current noise (rms).
Table 3. Input referred integrated current noise (rms).
Gain 1000×Gain 100×Gain 10×Gain 1×
100 Hz8 fA8 fA9 fA26 fA
10 KHz0.13 pA0.13 pA0.25 pA2.53 pA
1 MHz0.051 nA0.054 nA0.118 nA1.113 nA
Table 4. Table of comparison with relevant architecture.
Table 4. Table of comparison with relevant architecture.
[4][5][17][18][19]This Work *
Technology ( μ m)0.180.350.35/0.50.180.180.18
Power supply (V)1.8331.83.31.8
3 dB Signal bandwidth (MHz)1.440.11.250.00390.85
Dynamic range (dB)155.195.98016074140
Area (mm 2 )0.0910.340.60.20.51.015
Power consumption (mW)9.413.570.32310.3
Speed improvement factor1×11000×
* Simulation result.
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