## 1. Introduction

There is a growing need to sense very low levels of current in many biosensors and diagnostics applications [

1,

2,

3]. Current levels in such applications can be as low as picoamperes (pA) which are harder to detect using CMOS circuitry due to circuit noise. Several readout circuits have been developed for low current sensing. For example, an integrator or a transimpedance amplifier (TIA) has been employed to convert the current signal into a voltage signal, followed by quantization of the converted voltage signal. However, with the current in the pA range, if the integration method is adopted, it would take a long time to accumulate the small current into measurable voltage signal [

4]. If a TIA is employed, the feedback resistance must be large enough (i.e., gigaohms range) to obtain high gain and there is a trade-off between achieving high dynamic range and achieving low input-referred current noise. Moreover, such a large feedback resistor cannot be reliably realized on-chip and must be externally connected. A high-value active pseudo resistor made using off-state transistors have been widely used for small current sensing [

5,

6,

7,

8]. However, the resistance is inversely proportional to the input current, which leads to a variable current gain and bandwidth applications [

9].

In most applications, the small current signal needs to be amplified at high speed in bandwidths excess of 1 MHz. One such application is for nanopore sensing where the transient activity is in microseconds with Femto ampere current levels. A current conveyor is commonly employed for current amplification; however, the conventional current conveyor is not suitable for the small current amplification since the bias current of the conveyor leads to large input-referred current noise [

10,

11]. No-bias current conveyor has been adopted for low-noise current sensing [

12]. The noise levels achieved may still be prohibitive for low current sensing. A current preamplifier was presented, featuring a matched double-MOS architecture around an amplifier to obtain current amplification in [

13]. Capacitors with the same current ratio are needed to increase the bandwidth. The fixed current amplification gain leads to a smaller dynamic range. In this paper, a current preamplifier with a programmable gain is proposed to obtain bidirectional current amplification. The programmable current gains setting enables one to achieve a higher overall input dynamic range. Higher gain allows for faster operation for small input currents while lower gain avoids saturation of the integrator stage for large input currents. Thus, the variable current gain enables a wider input dynamic range. Note the input dynamic range is defined as the ratio of the largest to the smallest input signal that the circuitry can process. For a programmable gain amplifier, the dynamic range will be measured as a ratio of highest input signal level (at lowest gain setting) and the largest referred input noise ever measured for any of the gain settings. A pulse width modulation output stage provides a digital output without the need for clock. The circuit is designed in a 0.18

$\mathsf{\mu}$m CMOS process and validated using post-layout simulations.

## 3. Simulation Result

The circuit was simulated with post-layout extraction. This captures the RC parasitic effects in addition to any coupling capacitance. The current gain for wide dynamic range input current and the noise performance are simulated. By controlling the digital codes, the current gain can be programmed to be 1000×, 100×, 10×, and 1× as in

Figure 14. The proposed switch connections enable the flat current gain in various current gain settings.

With high current pre-amplification, the input-referred current noise at the input is given by Equation (

5). Note that the noise from the integration stage has been attenuated by the current-amplification gain. The feedback transistors and the input stage amplifier dominate the input reference current noise contribution.

$q{I}_{in}$ is the shot noise from

${M}_{P\left(N\right)1}$ in

Figure 8 operating in the subthreshold region. The voltage noise

${e}_{n}^{2}$ from the op-amp over the input capacitance

${C}_{in}$ sets the minimal noise of the circuit when the input current

${I}_{in}$ is small.

The equivalent input voltage noise from the front-end amplifier is shown in Equation (

6). The pre-amplification stage from

Figure 10 has a dominant noise contribution.

k is Boltzmann constant, and

K is a process related constant which influences the flicker noise.

The noise density and integrated noise simulation are shown in

Figure 15 and

Figure 16, respectively.

Table 3 lists the integrated noise (rms) with the signal bandwidth of 100 Hz, 10 KHz, and 1 MHz, and with the current gain of 1000×, 100×, 10×, and 1×, respectively. One can choose a fast operation mode for the small input current with some trade-off with the bandwidth, or one can process high bandwidth signal with a slower operation.

In

Figure 17, sinusoidal signals of the amplitude of 100 fA (10 Hz), 1 nA (1 KHz), and 1

$\mathsf{\mu}$A (1 MHz) are used as the input signal, respectively, and results show that recovered signal matches well with the input signal [

14].

Table 4 lists the proposed readout circuit performance and compares it with other recent state-of-the-art demonstrations. We added a new metric to the table; “Speed improvement factor”. It is defined as the improvement in output data rate from the use of variable gain settings. This can be estimated as follows.

${V}_{Threshold}$ is the threshold voltage of the comparator, and

${C}_{INT}$ is the integration capacitor.

I is the integration current and

${T}_{x}$ is the integration time for the 1× current gain setting; 1000

I is the integration current and

${T}_{y}$ is the integration time for the 1000× current gain setting. We can write Equations (7) and (8) for these two settings.

Equation (

9) implies that the circuit can generate the output pulse at a rate 1000 times using the 1000× current gain setting.