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Low Power Clock Network Design

Department of Electrical and Computer Engineering, University of Rochester, Rochester, NY 14627, USA
Department of Electrical Engineering, Technion–Israel Institute of Technology, Haifa 32000, Israel
Author to whom correspondence should be addressed.
J. Low Power Electron. Appl. 2011, 1(1), 219-246;
Received: 14 December 2010 / Revised: 8 April 2011 / Accepted: 30 April 2011 / Published: 19 May 2011
(This article belongs to the Special Issue Selected Topics in Low Power Design - From Circuits to Applications)
Power is a primary concern in modern circuits. Clock distribution networks, in particular, are an essential element of a synchronous digital circuit and a significant power consumer. Clock distribution networks are subject to clock skew due to process, voltage, and temperature (PVT) variations and load imbalances. A target skew between sequentially-adjacent registers can be obtained in a balanced low power clock tree using techniques such as buffer and wire sizing. Existing skew mitigation techniques in tree-based clock distribution networks, however, are not efficient in coping with post design variations; whereas the latest non-tree mesh-based solutions reliably handle skew variations, albeit with a significant increase in dissipated power. Alternatively, crosslink-based methods provide low power and variation-efficient skew solutions. Existing crosslink-based methods, however, only address skew at the network topology level and do not target low power consumption. Different methods to manage skew and skew variations within tree and non-tree clock distribution networks are reviewed and compared in this paper. Guidelines for inserting crosslinks within a buffered low power clock tree are provided. Metrics to determine the most power efficient technique for a given circuit are discussed and verified with simulation. View Full-Text
Keywords: low power; skew; skew variation; crosslinks; mesh; topologies low power; skew; skew variation; crosslinks; mesh; topologies
MDPI and ACS Style

Vaisband, I.; Friedman, E.G.; Ginosar, R.; Kolodny, A. Low Power Clock Network Design. J. Low Power Electron. Appl. 2011, 1, 219-246.

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