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Article

An Analytic Compact Model for P-Type Quasi-Ballistic/Ballistic Nanowire GAA MOSFETs Incorporating DIBL Effect

1
State Key Laboratory of Robotics and Intelligent Systems, Shenyang Institute of Automation, Chinese Academy of Sciences, Shenyang 110016, China
2
Shenyang Institute of Automation, Chinese Academy of Sciences, Shenyang 110016, China
*
Author to whom correspondence should be addressed.
Nanomaterials 2025, 15(22), 1734; https://doi.org/10.3390/nano15221734
Submission received: 10 October 2025 / Revised: 13 November 2025 / Accepted: 14 November 2025 / Published: 17 November 2025
(This article belongs to the Section Theory and Simulation of Nanostructures)

Abstract

We present an analytic compact model for p-type cylindrical gate-all-around (GAA) MOSFETs in the quasi-ballistic/ballistic regime, incorporating drain-induced barrier lowering (DIBL). To describe the potential profile, an undetermined parameter is used to represent the channel potential, which is derived from the Laplace equation in the subthreshold region and from Gauss’s law combined with quantum statistics in the inversion region. A smoothing function is applied to this parameter to ensure a continuous source—drain current across all operating regions. The current model is based on the Landauer approach and captures both quasi-ballistic/ballistic transport and quantum-confinement effects. It is validated against non-equilibrium Green’s function (NEGF) simulation results and implemented in Verilog-A for SPICE circuit-level simulation of a CMOS inverter, demonstrating its applicability for nanoscale design.

1. Introduction

The continued scaling of MOSFET dimensions below 10 nm has made strong gate control essential to reduce short-channel effects (SCEs), such as threshold voltage roll-off and drain-induced barrier lowering (DIBL) [1,2,3,4]. At the same time, the silicon body thickness has also been scaled below 10 nm, as predicted by the International Roadmap for Devices and Systems (IRDS) [5]. Among various advanced device structures, gate-all-around (GAA) MOSFETs are promising for future CMOS technologies due to their better electrostatic control and improved SCE suppression. To further increase integration density in a limited footprint, multi-stacked silicon nanosheet GAA structures have been proposed to widen the channel effectively [6,7,8,9]. Although nanosheet GAA FETs has been commercially adopted, nanowire GAA remains valuable as an analytically tractable platform for sub-10 nm studies of ballistic transport and quantum confinement. Its cylindrical geometry enables closed-form treatments of SCE, supporting compact model development. The resulting framework is readily extendable to nanosheet GAA FETs or complementary FETs (CFETs) via appropriate subband/density-of-states (DOS) formulations and geometry-aware electrostatics. Cylindrical GAA MOSFETs have been widely considered as successors to FinFETs at advanced technology nodes, with commercial adoption beginning at the 3 nm node, owing to their excellent subthreshold swing (SS) and high I ON / I OFF ratio [7,10,11]. GAA MOSFETs also show potential in specialized applications such as radiation-hardened circuits and gas sensors [12,13]. Since the channel lengths considered (<10 nm) are on the order of the hole mean free path in silicon [14], transport lies in the quasi-ballistic to ballistic regime, providing a practical guideline indicating that channel lengths comparable to the mean free path are the range where ballistic effects become relevant. As the silicon thickness and channel length continue to shrink, quantum-confinement and ballistic transport effects become more important and cannot be ignored. Phonon processes in low-dimensional structures play a crucial role in carrier transport and scattering mechanisms. Relevant studies include [15], along with experimental and theoretical investigations, such as [16]. These works provide important context for understanding phonon interactions in nanostructured devices. Thus, accurate models must include both quantum and ballistic effects.
Carrier transport in both n-type and p-type GAA MOSFETs under quantum and ballistic conditions can be accurately described using advanced numerical methods, such as the non-equilibrium Green’s function (NEGF) method, ab initio simulations, and the k · p method [9,13,17,18,19,20]. However, the high computational cost of these methods makes them impractical for circuit-level simulations. To solve this problem, several analytical compact models have been developed for short-channel ballistic GAA MOSFETs [21,22,23,24,25]. The models describing the I V behavior under ballistic transport and include effects such as thermionic emission and source-to-drain tunneling (SDT) are reported [26,27]. Nevertheless, most existing models focus only on n-type devices. Due to the anisotropic valence band, p-type devices exhibit stronger orientation dependence, leading to large variations in hole effective mass and mobility. Therefore, a compact model for short-channel p-type GAA MOSFETs that includes the DIBL effect and works across all operating regions remains lacking and is critically needed.
This paper presents an analytic compact model for p-type cylindrical GAA MOSFETs that includes quasi-ballistic/ballistic transport, quantum confinement, and the DIBL effects. The model is validated by technology computer-aided design (TCAD) simulations and implemented in Verilog-A. The remainder of this paper is organized as follows. Section 2 describes the device structure, defines key parameters, and formulates the quasi-ballistic/ballistic current model for p-type devices. Section 3 details the modeling of an unknown parameter in both subthreshold and inversion regions, along with the derivation of the lowest subband energy level across all operation modes. Section 4 presents the simulation results and discusses the accuracy and applicability of the proposed model. To the best of our knowledge, this is the first analytical model for p-type ballistic nanowire GAA MOSFETs that incorporates the DIBL effect and ballistic hole transport, validated in SPICE via Verilog-A.

2. Modeling Ballistic Current

2.1. Model Structure and Coordinates

As shown in Figure 1, the device is modeled as a cylinder with a circular cross-section. The channel is made of intrinsic silicon, and the source/drain regions are heavily doped p-type silicon. The source and drain are treated as ideal contacts that inject carriers without backscattering. The channel is fully surrounded by a metal gate and SiO2 gate oxide, forming a GAA structure.
In the following analysis, cylindrical coordinates are used with z along the channel, r as the radial coordinate, and φ as the angular coordinate. With perfect cylindrical symmetry assumed, the electrostatic potential and subband energy have no dependence on the angular coordinate φ . Therefore we can neglect φ in the analysis.

2.2. Quasi-Ballistic Current Derivation

Figure 2a,b illustrate the quasi-ballistic/ballistic transport mechanism along the channel for electrons and holes, respectively. In the quasi-ballistic/ballistic regime, carrier injection from the source is controlled by the potential barrier along the channel. For electrons, transport is determined by the maximum of the conduction subband profile, while for holes, it is determined by the minimum of the valence subband profile [28]. Thus, carrier transport in both cases is governed by the energy extremum of the corresponding subband profiles. The source—drain current primarily comes from carriers that have sufficient energy to overcome the barrier, a thermionic emission process described by the Landauer formalism. Accordingly, the expression for the quasi-ballistic/ballistic electron current in the device is given as follows [29,30]:
I DS = e π n φ , n r n ν 0 d E z · g n ν 1 R ref f e ( E F , S , E total ) f e ( E F , D , E total ) ,
E total = E MAX + E z ,
f e E F , E total = 1 1 + exp E total E F k B T ,
where e, and k B are the elementary charge, the reduced Planck constant and Boltzmann constant, respectively, n ν denotes the specific valley index of the energy band, g n ν is the corresponding valley degeneracy, and E MAX represents the maximum value of the subband energy level along the channel direction, defined by the angular and radial quantum numbers n φ and n r , respectively, R ref is the backscattering coefficient between the source and drain in quasi-ballistic transport, satisfying 0 R ref 1 [31,32]. The Fermi–Dirac distribution function for electrons, f e ( E F , E total ) , is evaluated by the total carrier energy E total , which is defined with respect to the Fermi level E F . The temperature T is given in Kelvin. On the other hand, based on Fermi–Dirac statistics describing the electron distribution in the channel as given by 1 f e ( E F , E total ) [33].
In this study, only holes injected from the source to drain are considered to contribute to the quasi-ballistic/ballistic current in the p-type devices. The integration limits are reversed compared to electron transport because holes encounter a subband energy barrier at E MIN , which corresponds to the subband energy level in the valence band, as illustrated in Figure 2b. Since the total energy E total of the hole lies below E MIN , the longitudinal kinetic energy, defined as E z = E total E MIN , is negative. As a result, the current integration is carried out over E z from to 0, unlike the electron case where E z is integrated from 0 to + . Therefore, the source-drain current can be expressed as follows:
I SD = e k B T π n φ , n r n ν g n ν 1 R ref ln 1 + exp E n φ , n r E F , S k B T 1 + exp E n φ , n r E F , D k B T .
E F , D = E F , S e V DS ,
where V DS is defined as the source–drain voltage. While the general expressions above include all possible subbands characterized by the quantum numbers n φ and n r , further simplifications will be introduced in the following sections.

3. Potential Profile Formulation

3.1. Subband Energy Profile and Definition of Δ U G

Figure 3a,b illustrate the conduction and valence band edge profiles ( E C and E V ), along with the lower subband energy levels, corresponding to the potential distributions along the z-direction at r = 0 and the r-direction at z = z EXT , respectively. As shown in Figure 3a, the hole subband energy level E n φ , n r at z = z EXT is defined as E EXT . In Figure 3b, the E C at the channel center ( r = 0 ) and the surface ( r = R ) are denoted as e w 0 and e w S , which correspond to the electrostatic potentials w 0 and w S , respectively. Thus, the potential difference between the center and surface of the channel, w 0 w S , is characterized by an unknown parameter Δ U G . Then, E n φ , n r is referenced to E F , S , and can be obtained from the quantum confinement energy, which depends on the surface potential at E V along the channel. The subband energy levels of holes in the channel can thus be expressed as follows:
E n φ , n r = e · w S E g E n φ , n r q ,
E n φ , n r q = E n φ , n r q 0 + e · H n φ , n r · Δ U G ,
E n φ , n r q 0 = 2 2 m xh r R n φ n r R 2 ,
where E g denotes the band gap between E C and E V , so E V at surface is given by e w S E g , E n φ , n r q represents the confinement subband energy level of holes, referenced to e w S E g , while E n φ , n r q 0 denotes the unperturbed confinement energy level, H n φ , n r is the perturbation matrix element, m xh r denotes the effective mass of confined holes along the radial direction, where the subscript x specifies the type of hole (heavy, light or split-off, denoted by h, l or s), and R n φ n r is the n r th zero of the first-kind Bessel function of order n φ , as defined in [34]. However, the objective of analytic compact modeling is to derive an explicit analytical expression for Δ U G as a function of the applied gate and drain biases. The following subsections will focus on formulating the expressions for Δ U G , addressing both the case with the DIBL effect and the long-channel case (without DIBL) in the subthreshold and inversion regions, respectively.

3.2. Analytical Solution for Channel Potential

To capture the DIBL effect in the subthreshold region, we derive an expression of Δ U G as a function of the position along the z-direction. Based on previous studies, the electrostatic potential distribution in the channel can be obtained by solving the Laplace equation with appropriate boundary conditions. Hence, approximate analytic expressions for the electrostatic potential can be derived for both the radial and channel directions. As reported in [25], the electrostatic potential distribution is rewritten as follows:
w ( r , z ) = A exp γ · z + B exp γ · z 1 γ 2 r 2 4 + V GS * ,
V GS * = V GS φ GC + w FB ,
where A and B are coefficients determined by boundary conditions at the drain and source ends of the channel, respectively, V GS is the gate-source voltage, φ GC represents the difference in work function between the gate and channel material, w FB refers to E C under the flat band condition, and γ is a geometric scaling coefficient defined as follows:
γ = 2 · β R ,
β = 1 1 + 4 π ϵ CH C OX ,
where ϵ CH is the dielectric constant of the channel, C OX is the gate oxide capacitance per unit length. The boundary bias coefficients above are defined as follows:
A = K V bi V GS * 1 exp γ L G + V DS ,
B = K V bi V GS * exp γ L G 1 V DS ,
K = 8 β 2 2 β 2 4 + β 4 · 1 exp γ L G exp γ L G ,
where V bi represents the junction built-in potential between the source and channel at equilibrium, which is determined by the electrostatic potential energy level of a subband at the source measured from E F , S / e [25]. Details on how V bi is chosen are discussed in Section 4.
Next, by substituting Equation (11) into Equation (9), we obtain the expression of the electrostatic potential distribution in the channel as follows:
w r , z = A exp γ · z + B exp γ · z 1 β 2 r 2 R 2 + V GS *
By further simplifying, the radial dependence of the electrostatic potential is approximated by a quadratic function of r. Under this assumption, w ( r , z ) can be rewritten in a more compact form as follows:
w r , z = w S z + 1 r 2 R 2 · Δ U G z ,
where w S ( z ) denotes the electrostatic potential of the channel surface along z-axis. According to the previous study [25,34], w S ( z ) can be written as:
w S z = w R , z = V GS * + V OX = V GS * + 4 π ϵ CH C OX Δ U G z ,
where V OX is the potential difference across the oxide, Δ U G ( z ) represents the z-component of potential variation due to DIBL, is expressed as:
Δ U G z = A · exp γ · z + B · exp γ · z · β 2 .
Furthermore, z EXT is defined as the position along the channel where the subband energy level reaches its extremum as shown in Figure 3a, and can be expressed as:
z EXT = 1 2 γ ln B A .
The expression for z EXT enables further analytical development of Δ U G in the subthreshold region. In particular, substituting Equation (20) into Equation (19) gives Δ U G ( z ) at z EXT in terms of coefficients A and B (from Equations (13) and (14)):
Δ U G DIBL z EXT = 2 A B .
Note that Equation (18) can also be derived from the relationships depicted in Figure 4a,b. In Figure 4a, the gate voltage V GS equals the gate contact work function φ GC under the flat-band condition. Both w 0 and w S are identical to the flat-band potential w FB . As V GS decreases, as shown in Figure 4b, V OX increases, leading to a corresponding reduction in w S . Consequently, w S and w 0 diverge and their relationship can be approximated by a quadratic function of Δ U G in the radial direction, as demonstrated in Equation (17).

3.3. Δ U G for All Operation Regions

In the following analysis, the quasi-ballistic/ballistic current is assumed to consist of holes excited only to the lowest subband, characterized by quantum numbers n φ = 0 and n r = 1, across all operating regions. This assumption is based on the fact that, under typical bias conditions and device geometries, hole transport in p-type nanowire GAA MOSFETs is primarily governed by the lowest subband derived from the heavy-hole (HH) subband. Previous studies [26,35,36,37] have confirmed that the occupation of higher-order subbands is negligible for devices with R < 3 nm and V GS < 0.4 V. Building on earlier modeling work for n-type devices without DIBL [34], where Gauss’s law was combined with quantum statistics to compute the carrier density at z EXT , we extend the approach to p-type devices. The corresponding Δ U G at z EXT is obtained numerically and expressed as:
4 π ϵ CH Δ U G = e π k B T m 0 2 n ν × g n ν m hh z m 0 1 + R ref f 1 2 E 0 , 1 E F , S k B T + 1 R ref f 1 2 E 0 , 1 E F , D k B T ,
F j a = 0 d y y j 1 + exp y a ,
where m hh z denotes the effective mass of the HH subband along the channel direction, F j represents the Fermi-Dirac integral function of order j. For sufficiently high drain bias ( | e V DS | k B T ), holes injected from the drain contribute negligibly to the thermionic current [34]. Accordingly, we neglect the second term on the right-hand side of Equation (22) in the analytic development and derive approximate closed-form expressions for Δ U G in both the subthreshold and inversion regimes. To ensure continuity between the two regions, we then combine the two solutions into a unified expression Δ U G ( 1 ) using a smoothing function:
Δ U G ( 1 ) = C 1 C 2 2 1 + 4 C 1 2 C 2 1 α log 1 + exp α · C 3 1 ,
C 1 = H 0 , 1 V t + 4 π ϵ CH C OX · V t ,
C 2 = e 2 k B T m hh z g ν 2 1 + R ref 2 8 π 4 ϵ CH 2 2 ,
C 3 = V GS * V t E 0 , 1 q 0 k B T E g k B T ,
where V t = k B T / e is the thermal voltage, α is an empirical fitting parameter, set to 0.3 to achieve good agreement with NEGF simulation results for source—drain current characteristics in Section 4. Although it has no direct physical meaning, it ensures a smooth and differentiable transition between the subthreshold and inversion regions and is kept constant throughout the model to preserve consistency [36].
Finally, Δ U G all at z EXT , valid across all operating regions, is formulated as follows:
Δ U G all = Δ U G DIBL z EXT + Δ U G ( 1 ) .
This expression represents the superposition of Δ U G DIBL affected by DIBL in the subthreshold region and Δ U G ( 1 ) unaffected by DIBL in the inversion region, which means that the weak-inversion region lacks an explicit expression for Δ U G all . As a result, the lowest subband energy level for holes can be obtained by substituting Equation (28) into Equations (7) and (18).

4. Results and Discussion

For simplicity, the hole effective masses in the radial and channel directions are assumed equal ( m hh z = m hh r ), neglecting the valence anisotropy and using 0.49 m 0 as a representative value for the HH band in the given nanowire orientation [38]. Since the lowest subband comes from the HH band and dominates hole transport under normal conditions, the valence band is modeled as a single valley ( g n ν = 1) [17]. A built-in potential of V bi = −1.35 V, extracted from device simulations, is used for all cases to simplify calculations under different geometries and bias conditions [25]. In addition, we assume that R ref is set as zero for all following calculations. Quantum reflection at the barrier and parasitic resistance at the source and drain are also ignored. This section compares the proposed model with TCAD simulations using six subbands calculations [38]. The TCAD simulations use a Poisson–NEGF (non-equilibrium Green’s function) framework under the effective-mass approximation (mode-space, Fermi statistics), solved self-consistently for a cylindrical Si/SiO2 nanowire. Geometry is swept over R = 1.5 , 2.0 , 2.5 nm and L = 7 , 9 nm, with 10-nm p-doped source/drain extensions and T OX = 0.5 nm. The channel is undoped; the source/drain are uniformly p-doped to 1 × 10 20 cm 3 . The gate work function is 4.8 eV (n-poly). Key NEGF controls include negf_ms, qcrit.negf, esize.negf, sp.smooth, num.band = 3, and eigen = 2. Full input decks, solver options, and scripts are available in the GitHub repository (see Data Availability Statement). NEGF simulations were performed with Silvaco ATLAS v5.22.1.R (DeckBuild). Circuit simulations used Cadence Spectre 15.1.0.284 with the BSIM-CMG 112.0.0 Verilog-A model. Analytical derivations were carried out in Wolfram Cloud (Mathematica), and data post-processing/plotting in R 4.5.1. In the following results, NEGF benchmarks confirm that this simplified HH-based treatment reproduces the main transport characteristics and orientation trends across the reported ranges of L and R.
The drain–source voltage is set to V DS = −0.6 V, following the IRDS roadmap [5], and the source Fermi level E F , S is set to zero in the NEGF simulation. Moreover, in the quasi-ballistic/ballistic regime, orientation is captured via direction-specific heavy-hole masses: m hh r (radial, sets subbands) and m hh z (channel, sets injection velocity and 1D DOS), which together determine the Landauer current. Then, the source–drain current from Equation (4) can be rewritten as:
I SD = e k B T π · ln 1 + exp E 0 , 1 z EXT k B T 1 + exp E 0 , 1 z EXT + e V DS k B T .
Figure 5 shows the calculated Δ U G all (solid red line from Equation (28)), which gives the unknown parameter at the barrier minimum across all operating regions. For comparison, Δ U G DIBL (blue dashed line from Equation (21), subthreshold region) and Δ U G ( 1 ) (green dashed line from Equation (24), inversion region) are also plotted. When the DIBL effect is ignored, Δ U G ( 1 ) becomes zero in the subthreshold region. In contrast, Δ U G DIBL stays negative across all operating regions. As the gate length L decreases, the drain–channel electrostatic coupling strengthens, enhancing the DIBL effect and increasing Δ U G DIBL . Conversely, as the nanowire radius R decreases, quantum confinement is reinforced, which mitigates part of the DIBL-induced potential drop and leads to a smaller Δ U G DIBL compared with that at larger R.
Figure 6 compares the electrostatic potential along the channel center from the proposed model (dots, from Equation (9)) and NEGF simulations (solid lines). The vertical dashed lines indicate the source/channel and drain/channel interfaces. The red, green, and blue curves (top to bottom) represent V GS = 0, −0.2, −0.5 V, respectively. To better match the NEGF results and include the effects of source/drain junctions, the effective channel length was extended empirically by 1 nm (source) and 2 nm (drain) for various device dimensions under all biases. These extensions account for the depletion regions and barrier lowering near the source and drain, which are not directly captured by the core model. Moreover, Figure 6 shows a diminishing radius effect: at R = 1.5 nm, stronger quantum confinement raises the hole subband energy level farther above the Fermi level than for R > 2 nm, leading to a clear change in carrier supply and current. When the radius increases from 2.0 to 2.5 nm, the additional confinement relief is small, so the curves differ only slightly. These observations are consistent with our NEGF results. It should be noted that the V GS values in Figure 6 and Figure 7 are selected to demonstrate the model’s accuracy across subthreshold, linear, and saturation regions, while I SD is calculated from the complete model (Equation (29)) rather than from these specific bias points.
Figure 7 compares the lowest subband energy profile for holes along the channel as obtained from NEGF simulations and the proposed compact model at gate biases of V GS = 0, −0.2, −0.5 V from the bottom to top. Simulation results are well captured by the analytic compact model.
Figure 8 shows the lowest subband energy level for holes at the barrier minimum as a function of gate voltage, comparing NEGF simulation results (dots) with the compact model (solid lines). The results of simulation and analytic compact model agree well across the plotted range.
Figure 9 shows the I SD V GS curves for different channel lengths and nanowire radii, calculated using Equation (29) across all operating regions. Dots represent the compact model, and solid lines are from NEGF simulations.
Figure 10 shows the I SD V DS characteristics comparing NEGF simulations (solid lines) with the compact model (dots) for various channel lengths and nanowire radii. The three curves (red, green, blue from top to bottom) correspond to V DS = −0.6, −0.55, −0.5 V, respectively. The larger deviation between panels (c) and (f) in Figure 10 is attributable to the I SD V GS mismatch around 0.5 0.6 V in Figure 9. Because we use one global fitting parameter (no re-tuning per case), this local mismatch carries over and becomes larger in the corresponding I SD V DS curves.
As shown in Figure 11, the relative error between the model and NEGF results for I SD V GS and I SD V DS was evaluated under different bias conditions. While the relative error exceeds 100% in the subthreshold region for some device sizes, it remains within 0–40% across most operating conditions. Since the subthreshold current is very small, such errors are practically negligible. The model demonstrate good accuracy in the inversion region for compact modeling purposes and captures key trends and bias-dependent behavior. Since a single fitting parameter is used across all cases (no per-corner re-tuning), the results show no simple monotonic dependence on R, L, V GS , V DS and should be viewed as a wide-range one-parameter compromise.
Figure 12 demonstrates a side-by-side I SD - V GS comparisons and error-distribution plots at R = 2 nm with L = 7 , 9 , 12 , 20 nm, respectively. After re-selecting the single fitting parameter for this wider length set, the relative error profile shifts. The errors decrease in inversion but increase in subthreshold, highlighting the trade-off and limitation of a one-parameter calibration over a wide (R, L, V GS , V DS ) range. Compared with our conference paper [36], which focused on subband-energy agreement at L = 20 nm, the present work introduces an analytical DIBL formulation, improves accuracy, and expands validation across R, L, V GS , and V DS . These results emphasize wide-range current agreement under a single α while motivating multi-parameter and physics-refined extensions in future work.
Figure 13a shows the circuit diagrams of the CMOS, NMOS, and PMOS inverters. Figure 13b shows the simulated output voltage ( V OUT ) versus input voltage ( V IN ) from SPICE simulations. To perform these simulations, the proposed quasi-ballistic/ballistic compact model with DIBL effect was implemented in SPICE using a Verilog-A module. Three inverters were simulated: an NMOS inverter (n-type GAA MOSFET with resistive load), a PMOS inverter (p-type GAA MOSFET with resistive load), and a CMOS inverter combining both transistors, as shown in Figure 13a. The new p-type model was used together with an existing n-type GAA model [25] to build the CMOS inverter. In Figure 13b, V OUT versus V IN is shown for all three inverters from SPICE DC sweep. The subscripts in R and L (NMOS or PMOS) indicate the radius and channel length of each transistor. The supply voltage is set to V DD = 0.6 V, according to the IRDS projected range (0.55–0.65 V) [5]. The proposed Verilog-A model supports DC operation only and is applicable to static analyses such as transfer characteristics and bias points. Future work will extend it to dynamic simulations by incorporating charge-based formulations.
As shown in Figure 14, a CMOS inverter and a 4T SRAM butterfly SNM (Static Noise Margin) comparison between the proposed compact model and BSIM-CMG are performed under identical bias conditions. In the inverter simulations, the proposed model exhibits a slightly lower threshold voltage and a steeper near-threshold slope than BSIM-CMG. In addition, the proposed model reproduces the SNM trend across hold/read conditions. A residual offset of 90 mV appears near the near-threshold/read-disturb region. We attribute this to (i) a small threshold mismatch between the proposed compact model and BSIM-CMG and (ii) the current DC-only formulation (capacitances, leakage partition, and noise are not modeled). Moreover, the near-threshold slope of proposed model is slightly steeper than that of BSIM-CMG, which further amplifies the deviation in the read-disturb region. Outside this region, the SNM difference remains within 90 mV. Under identical SPICE settings, the runtime is comparable to BSIM-CMG (Inverter 0–0.6 V/100 steps: 0.387 s vs 0.368 s; 4T SRAM SNM: 0.392 s vs 0.410 s).

5. Conclusions

This work presents an analytic compact DC model for the source—drain current of p-type cylindrical gate-all-around (GAA) MOSFETs, built on the Landauer approach and explicitly including drain-induced barrier lowering (DIBL). The model fills a gap in prior studies by providing a SPICE-compatible framework for quasi-ballistic/ballistic p-type nanowire devices. It shows good agreement with non-equilibrium Green’s function (NEGF) simulations over representative channel lengths, nanowire radii, and bias ranges, and it is implemented in Verilog-A for circuit-level SPICE simulations.
In summary, the present model is exploratory and uses a single global fitting parameter, prioritizing physical clarity and efficiency over industry-level quantitative accuracy. While limited precision appears under certain bias conditions, it consistently captures the key transport trends and the primary directional behavior of p-type devices. The framework can be extended to other confinement shapes, such as nanosheet- or quantum-well-like structures, by using appropriate 2D density-of-states/subband formulas or through NEGF-guided calibration.
Future work will improve quantitative accuracy through multi-parameter calibration, the inclusion of higher-order physics such as scattering and source-to-drain tunneling, and modest smoothing and binning to preserve compactness and transparency. We will also add a charge-based AC capacitance model for small-signal and transient analyses and develop a noise-aware compact model to enable predictive nanoscale CMOS design.

Author Contributions

Conceptualization, H.C.; methodology, H.C. and Z.Z.; software, H.C., C.Z. and Z.Z.; validation, H.C. and Z.Y.; formal analysis, H.C.; investigation, H.C.; resources, H.C. and Z.Y.; data curation, H.C. and Z.Z.; writing—original draft preparation, H.C.; writing—review and editing, H.C.; visualization, H.C.; supervision, Z.Z.; project administration, Z.Y.; funding acquisition, Z.Y. All authors have read and agreed to the published version of the manuscript.

Funding

This research was funded by the State Key Laboratory of Robotics, China, grant number 2025-Z02-07. The APC was funded by the same grant.

Data Availability Statement

All simulation decks, solver options, and analysis scripts that support the findings of this study are openly available at GitHub (https://github.com/hecheng618/PGAA7nm; accessed on 16 October 2025).

Acknowledgments

This work was supported by the Independent Subject of the State Key Laboratory of Robotics, China, under grant No. 2025-Z02-07.

Conflicts of Interest

The authors declare no conflicts of interest.

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Figure 1. Schematic illustration of the nanowire GAA MOSFET structure. The channel length, nanowire radius, and gate oxide thickness are denoted by L G , R, and T OX , respectively.
Figure 1. Schematic illustration of the nanowire GAA MOSFET structure. The channel length, nanowire radius, and gate oxide thickness are denoted by L G , R, and T OX , respectively.
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Figure 2. Simplified schematic of quasi-ballistic/ballistic transport along the z-axis for (a) electrons and (b) holes. E C and E V denote the conduction and valence band edges, shown as colored dashed lines. For electron transport in (a), positive gate and drain voltages are applied, and the subband energy maximum E MAX defines the barrier top at z MAX . For hole transport in (b), negative gate and drain voltages are applied, and the subband energy minimum E MIN occurs at z MIN . E F , S and E F , D represent the source and drain Fermi levels, respectively. This schematic highlights the contrast in energy barrier shapes between electron and hole transport.
Figure 2. Simplified schematic of quasi-ballistic/ballistic transport along the z-axis for (a) electrons and (b) holes. E C and E V denote the conduction and valence band edges, shown as colored dashed lines. For electron transport in (a), positive gate and drain voltages are applied, and the subband energy maximum E MAX defines the barrier top at z MAX . For hole transport in (b), negative gate and drain voltages are applied, and the subband energy minimum E MIN occurs at z MIN . E F , S and E F , D represent the source and drain Fermi levels, respectively. This schematic highlights the contrast in energy barrier shapes between electron and hole transport.
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Figure 3. Rough sketches of the potential energy profiles along the channel and transverse directions, illustrating the carrier transport mechanisms in ballistic thermionic emission modes. (a) Energy level distribution along the z-direction at the channel center ( r = 0 ). (b) Schematic of the confinement potential energy along the r-direction at the subband energy minimum ( z = z EXT ) in the cross-section.
Figure 3. Rough sketches of the potential energy profiles along the channel and transverse directions, illustrating the carrier transport mechanisms in ballistic thermionic emission modes. (a) Energy level distribution along the z-direction at the channel center ( r = 0 ). (b) Schematic of the confinement potential energy along the r-direction at the subband energy minimum ( z = z EXT ) in the cross-section.
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Figure 4. Schematic diagrams of electrostatic potential and potential distribution along r-component at z = z EXT . (a) Electrostatic potential distribution for flat-band condition. (b) Electrostatic potential distribution for V GS < φ GC conditions.
Figure 4. Schematic diagrams of electrostatic potential and potential distribution along r-component at z = z EXT . (a) Electrostatic potential distribution for flat-band condition. (b) Electrostatic potential distribution for V GS < φ GC conditions.
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Figure 5. Comparison of Δ U G all in Equation (28), Δ U G DIBL ( z EXT ) in Equation (21) due to DIBL at z EXT and Δ U G ( 1 ) in Equation (24) component without DIBL. Common simulation conditions: V DS = 0.6 V , V bi = 1.35 V , and φ GS w FB = 0.63 V . Subfigures: (a) R = 1.5 nm , L = 7 nm ; (b) R = 2 nm , L = 7 nm ; (c) R = 2.5 nm , L = 7 nm ; (d) R = 1.5 nm , L = 9 nm ; (e) R = 2 nm , L = 9 nm ; (f) R = 2.5 nm , L = 9 nm .
Figure 5. Comparison of Δ U G all in Equation (28), Δ U G DIBL ( z EXT ) in Equation (21) due to DIBL at z EXT and Δ U G ( 1 ) in Equation (24) component without DIBL. Common simulation conditions: V DS = 0.6 V , V bi = 1.35 V , and φ GS w FB = 0.63 V . Subfigures: (a) R = 1.5 nm , L = 7 nm ; (b) R = 2 nm , L = 7 nm ; (c) R = 2.5 nm , L = 7 nm ; (d) R = 1.5 nm , L = 9 nm ; (e) R = 2 nm , L = 9 nm ; (f) R = 2.5 nm , L = 9 nm .
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Figure 6. Comparison of electrostatic potential profiles along the channel center from the compact model using Equation (9) and NEGF simulation under different gate biases. Gate biases shown: V GS = 0 , 0.2 , and 0.5 V . Common simulation conditions: V DS = 0.6 V , V bi = 1.35 V , and φ GS w FB = 0.63 V . Subfigures: (a) R = 1.5 nm , L = 7 nm ; (b) R = 2 nm , L = 7 nm ; (c) R = 2.5 nm , L = 7 nm ; (d) R = 1.5 nm , L = 9 nm ; (e) R = 2 nm , L = 9 nm ; (f) R = 2.5 nm , L = 9 nm .
Figure 6. Comparison of electrostatic potential profiles along the channel center from the compact model using Equation (9) and NEGF simulation under different gate biases. Gate biases shown: V GS = 0 , 0.2 , and 0.5 V . Common simulation conditions: V DS = 0.6 V , V bi = 1.35 V , and φ GS w FB = 0.63 V . Subfigures: (a) R = 1.5 nm , L = 7 nm ; (b) R = 2 nm , L = 7 nm ; (c) R = 2.5 nm , L = 7 nm ; (d) R = 1.5 nm , L = 9 nm ; (e) R = 2 nm , L = 9 nm ; (f) R = 2.5 nm , L = 9 nm .
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Figure 7. Gate bias dependence of the hole lowest subband energy level along the channel calculated by the NEGF simulation and proposed compact model. Gate biases shown: V GS = 0 , 0.2 , and 0.5 V . Common simulation conditions: V DS = 0.6 V , V bi = 1.35 V , and φ GS w FB = 0.63 V . Subfigures: (a) R = 1.5 nm , L = 7 nm ; (b) R = 2 nm , L = 7 nm ; (c) R = 2.5 nm , L = 7 nm ; (d) R = 1.5 nm , L = 9 nm ; (e) R = 2 nm , L = 9 nm ; (f) R = 2.5 nm , L = 9 nm .
Figure 7. Gate bias dependence of the hole lowest subband energy level along the channel calculated by the NEGF simulation and proposed compact model. Gate biases shown: V GS = 0 , 0.2 , and 0.5 V . Common simulation conditions: V DS = 0.6 V , V bi = 1.35 V , and φ GS w FB = 0.63 V . Subfigures: (a) R = 1.5 nm , L = 7 nm ; (b) R = 2 nm , L = 7 nm ; (c) R = 2.5 nm , L = 7 nm ; (d) R = 1.5 nm , L = 9 nm ; (e) R = 2 nm , L = 9 nm ; (f) R = 2.5 nm , L = 9 nm .
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Figure 8. Comparison of the hole lowest subband energy level minimum obtained from NEGF simulations and the proposed compact model. Common simulation conditions: V DS = 0.6 V , V bi = 1.35 V , and φ GS w FB = 0.63 V . Subfigures: (a) R = 1.5 nm , L = 7 nm ; (b) R = 2 nm , L = 7 nm ; (c) R = 2.5 nm , L = 7 nm ; (d) R = 1.5 nm , L = 9 nm ; (e) R = 2 nm , L = 9 nm ; (f) R = 2.5 nm , L = 9 nm .
Figure 8. Comparison of the hole lowest subband energy level minimum obtained from NEGF simulations and the proposed compact model. Common simulation conditions: V DS = 0.6 V , V bi = 1.35 V , and φ GS w FB = 0.63 V . Subfigures: (a) R = 1.5 nm , L = 7 nm ; (b) R = 2 nm , L = 7 nm ; (c) R = 2.5 nm , L = 7 nm ; (d) R = 1.5 nm , L = 9 nm ; (e) R = 2 nm , L = 9 nm ; (f) R = 2.5 nm , L = 9 nm .
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Figure 9. Comparison of I SD V GS between the NEGF simulation and the proposed compact model, assuming only the lowest subband is occupied. Common simulation conditions: V DS = 0.6 V , V bi = 1.35 V , and φ GS w FB = 0.63 V . Subfigures: (a) R = 1.5 nm , L = 7 nm ; (b) R = 2 nm , L = 7 nm ; (c) R = 2.5 nm , L = 7 nm ; (d) R = 1.5 nm , L = 9 nm ; (e) R = 2 nm , L = 9 nm ; (f) R = 2.5 nm , L = 9 nm .
Figure 9. Comparison of I SD V GS between the NEGF simulation and the proposed compact model, assuming only the lowest subband is occupied. Common simulation conditions: V DS = 0.6 V , V bi = 1.35 V , and φ GS w FB = 0.63 V . Subfigures: (a) R = 1.5 nm , L = 7 nm ; (b) R = 2 nm , L = 7 nm ; (c) R = 2.5 nm , L = 7 nm ; (d) R = 1.5 nm , L = 9 nm ; (e) R = 2 nm , L = 9 nm ; (f) R = 2.5 nm , L = 9 nm .
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Figure 10. I SD V DS characteristics comparison between the NEGF simulation (solid lines) and proposed compact model (dots) for the lowest subband energy level. Common simulation conditions: V DS = 0.6 V , V bi = 1.35 V , and φ GS w FB = 0.63 V . Subfigures: (a) R = 1.5 nm , L = 7 nm ; (b) R = 2 nm , L = 7 nm ; (c) R = 2.5 nm , L = 7 nm ; (d) R = 1.5 nm , L = 9 nm ; (e) R = 2 nm , L = 9 nm ; (f) R = 2.5 nm , L = 9 nm .
Figure 10. I SD V DS characteristics comparison between the NEGF simulation (solid lines) and proposed compact model (dots) for the lowest subband energy level. Common simulation conditions: V DS = 0.6 V , V bi = 1.35 V , and φ GS w FB = 0.63 V . Subfigures: (a) R = 1.5 nm , L = 7 nm ; (b) R = 2 nm , L = 7 nm ; (c) R = 2.5 nm , L = 7 nm ; (d) R = 1.5 nm , L = 9 nm ; (e) R = 2 nm , L = 9 nm ; (f) R = 2.5 nm , L = 9 nm .
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Figure 11. Relative errors between the proposed model and NEGF simulation for both I SD V GS and I SD V DS characteristics. Note: Deviations are reported to document the remaining error; with a single fitting parameter (no per-case re-tuning), residuals are localized rather than strictly monotonic with R, L, V GS or V DS . Subfigures: (a) R = 1.5 nm , L = 7 nm ; (b) R = 2 nm , L = 7 nm ; (c) R = 2.5 nm , L = 7 nm ; (d) R = 1.5 nm , L = 9 nm ; (e) R = 2 nm , L = 9 nm ; (f) R = 2.5 nm , L = 9 nm .
Figure 11. Relative errors between the proposed model and NEGF simulation for both I SD V GS and I SD V DS characteristics. Note: Deviations are reported to document the remaining error; with a single fitting parameter (no per-case re-tuning), residuals are localized rather than strictly monotonic with R, L, V GS or V DS . Subfigures: (a) R = 1.5 nm , L = 7 nm ; (b) R = 2 nm , L = 7 nm ; (c) R = 2.5 nm , L = 7 nm ; (d) R = 1.5 nm , L = 9 nm ; (e) R = 2 nm , L = 9 nm ; (f) R = 2.5 nm , L = 9 nm .
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Figure 12. (a) I SD - V GS comparison at R = 2 nm with L = 7 , 9 , 12 , 20 nm under identical V DS . (b) Relative error distributions for the same set.
Figure 12. (a) I SD - V GS comparison at R = 2 nm with L = 7 , 9 , 12 , 20 nm under identical V DS . (b) Relative error distributions for the same set.
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Figure 13. (a) CMOS, NMOS, and PMOS inverter schematics; (b) Simulated V OUT V IN characteristics from SPICE.
Figure 13. (a) CMOS, NMOS, and PMOS inverter schematics; (b) Simulated V OUT V IN characteristics from SPICE.
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Figure 14. Comparisons between proposed model and BSIM-CMG model in (a) a CMOS inverter (b) a 4T SRAM simulation.
Figure 14. Comparisons between proposed model and BSIM-CMG model in (a) a CMOS inverter (b) a 4T SRAM simulation.
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Cheng, H.; Yang, Z.; Zhang, C.; Zhang, Z. An Analytic Compact Model for P-Type Quasi-Ballistic/Ballistic Nanowire GAA MOSFETs Incorporating DIBL Effect. Nanomaterials 2025, 15, 1734. https://doi.org/10.3390/nano15221734

AMA Style

Cheng H, Yang Z, Zhang C, Zhang Z. An Analytic Compact Model for P-Type Quasi-Ballistic/Ballistic Nanowire GAA MOSFETs Incorporating DIBL Effect. Nanomaterials. 2025; 15(22):1734. https://doi.org/10.3390/nano15221734

Chicago/Turabian Style

Cheng, He, Zhijia Yang, Chao Zhang, and Zhipeng Zhang. 2025. "An Analytic Compact Model for P-Type Quasi-Ballistic/Ballistic Nanowire GAA MOSFETs Incorporating DIBL Effect" Nanomaterials 15, no. 22: 1734. https://doi.org/10.3390/nano15221734

APA Style

Cheng, H., Yang, Z., Zhang, C., & Zhang, Z. (2025). An Analytic Compact Model for P-Type Quasi-Ballistic/Ballistic Nanowire GAA MOSFETs Incorporating DIBL Effect. Nanomaterials, 15(22), 1734. https://doi.org/10.3390/nano15221734

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