Towards Reconfigurable Electronics: Silicidation of Top-Down Fabricated Silicon Nanowires

Featured Application

This work has implications for the fabrication of nickel silicide–silicon Schottky junction-based devices such as reconfigurable field-effect transistors.

Abstract

We present results of our investigations on nickel silicidation of top-down fabricated silicon nanowires (SiNWs). Control over the silicidation process is important for the application of SiNWs in reconfigurable field-effect transistors. Silicidation is performed using a rapid thermal annealing process on the SiNWs fabricated by electron beam lithography and inductively-coupled plasma etching. The effects of variations in crystallographic orientations of SiNWs and different NW designs on the silicidation process are studied. Scanning electron microscopy and transmission electron microscopy are performed to study Ni diffusion, silicide phases, and silicide–silicon interfaces. Control over the silicide phase is achieved together with atomically sharp silicide–silicon interfaces. We find that {111} interfaces are predominantly formed, which are energetically most favorable according to density functional theory calculations. However, control over the silicide length remains a challenge.

1. Introduction

In the last few decades, the conventional downscaling of complementary metal-oxide-semiconductor (CMOS) transistors dominantly relied on the reduction of size to improve the performance as well as to reduce the costs and the power consumption of devices. With the end of physical scaling of field-effect transistors (FETs), further device performance enhancement is expected to be based on new concepts. These concepts include new materials (e.g., high mobility channel materials [1,2,3] such as 2D materials), metal gates with high-k gate dielectrics [4], new device architectures (e.g., 3D integration) [5], new computation principles (e.g., spintronics) [6], and new functionality (e.g., reconfigurability) [7]. Reconfigurability, in particular, can be achieved by selectively injecting a chosen type of charge carrier in the channel and controlling the concentration of these charge carriers at Schottky junctions [8]. This concept is typically implemented by fabricating Schottky junction-based FETs, also known as reconfigurable FETs (RFETs) [9]. In RFETs, undoped silicon nanowires (SiNWs) are nickel (Ni) silicided from both ends using annealing, and the Ni diffusion process creates a silicide–silicon–silicide structure with two Schottky junctions. The observed silicide phases vary in terms of the sheet resistance, Schottky barrier height, built-in strain etc. [10,11]. Hence, the phase of the silicide influences the performance of devices as the injection and the extraction of charge carriers in the silicide–silicon junction depend on the properties of the phase [12,13]. Since the performance of RFETs strongly depends on the quality of the Schottky junctions, proper control over the silicidation process (silicide phase, sharpness of the silicide–Si interfaces, silicide length along the nanowire) in these devices is very important but remains a challenge [14].

This work aims at understanding the Ni-silicide diffusion mechanism and attaining specifically the NiSi₂ phase in top-down fabricated SiNWs by studying the silicide–Si interfaces. The formation of NiSi₂–Si contacts is attractive because NiSi₂ exhibits similar electron and hole barriers [10]. It also has a low lattice mismatch of 0.4% with respect to Si at room temperature, which allows the formation of single-crystalline structures [10,15]. NiSi₂ forms an abrupt heterojunction to Si, thus enabling its use in unipolar devices such as RFETs [16]. To understand the sequence of phase formation within the desired temperature range, various studies have been reported for bottom-up grown nanowires [17,18,19,20,21,22,23,24,25,26,27,28,29,30,31]. However, fewer studies are available for top-down fabricated nanowires [32,33]. In addition to the formation of the suitable silicide phase, control over the sharpness of silicide–Si interfaces, and the silicide length is important for applications such as RFETs and Schottky barrier FETs [34].

Silicides are mostly formed by a temperature-induced interfacial reaction of a transition metal with Si. This process is called the reactive phase formation, which indicates diffusion between two adjacent phases leading to the formation of a single or multiple products along the chemical gradient between those phases [35,36]. Silicidation is governed by diffusion [37,38] and nucleation [35,39] and can be controlled by steps involved in the reaction phase formation.

Ni-silicide formation on bulk Si substrates has been extensively studied in the past [39,40,41,42,43]. Moreover, Ni-silicided nanowires can be produced by direct synthesis or by solid-state reaction of Ni with SiNWs. Wu et al. [44] reported single-crystalline NiSi nanowires produced by radial silicidation of vapor–liquid–solid grown SiNWs, which were coated with thermally-evaporated Ni and annealed at 550 °C in forming a gas atmosphere to produce single-crystalline NiSi NWs. The first report of the longitudinal growth of metal silicides in nanowires and the formation of flat and abrupt interfaces to silicon was given by Weber et al. [16] by the example of NiSi₂–Si nanowire hetero-structures. Schmitt et al. [45] published a detailed review of several processes to produce transition metal silicide nanowires. The desired silicide phase formation is facilitated by proper control of annealing parameters [46] in an axial hetero-structure. These hetero-structures have been used for FET applications and exploration of innovative device concepts [8,16,45,47,48].

The silicide diffusion and phase formation in SiNWs has been described in various publications. Appenzeller et al. [29] demonstrated that the longitudinal growth of silicide in SiNWs is a function of the radius or the cross-sectional area of the nanowire and the produced silicide phase. The nature of the Si–silicide interface also influences the growth and the phase of silicide. The most common Ni-silicide phases in SiNWs are Ni₂Si, NiSi, and NiSi₂. The phase of silicide can be controlled by a proper choice of Ni quantity and quality [27,39], conditions of the reaction [30], strain in the nanowire [28,49], and crystal orientation of nanowires [26]. In <112> nanowires, the hexagonal θ-Ni₂Si is formed at 300 °C, whereas this phase is not observed till 800 °C in bulk structures [47]. In <111> nanowires, first the epitaxial NiSi₂ is formed and it withstands temperatures upto 700 °C. The low-resistive NiSi is formed at 700 °C [26]. The thermal history of the SiNW influences the silicidation rate. Yamashita et al. [50] presented a comparative illustration of silicidation rate for SiNWs fabricated by two different processes: The “doping first” process, where the annealing for dopant activation is carried out before the NW patterning; and the “patterning first” process, where NWs are patterned first and then subjected to further heat treatment for oxidation and dopant activation. They concluded that the silicidation rate in “patterning first” approach nanowires is higher than that for the “doping first” approach, as the oxidation induced strain in the “patterning first” approach is altered and distributed by dopant activation annealing in the later process step.

Here we present the results of our investigations on the Ni silicidation of top-down fabricated SiNWs. In the next section, details of the SiNW fabrication and the analysis techniques are given. The initial investigations were carried out on Si thin film structures to identify the process window for SiNW silicidation. In the third section, the results obtained from scanning electron microscopy (SEM) and transmission electron microscopy (TEM) are presented and compared to simulations. Results of electrical characterization of back-gated RFETs are also presented.

2. Materials and Methods

The devices were fabricated on (100) surface-oriented silicon-on-insulator (SOI) substrates. One set of substrates had a 20 nm top Si layer and a 102 nm buried SiO₂ (BOX) layer, while the second set of substrates had a 50 nm top Si layer with a 110 nm BOX layer. SiNWs were fabricated using electron beam lithography (EBL) and inductively-coupled plasma (ICP) etching. EBL was performed with a Raith e-Line Plus system at an acceleration voltage of 10 kV, 1200 µC/cm² dose, 30 μm aperture size, and with 2 nm area beam step size using the negative tone EBL resist, hydrogen silsesquioxane (HSQ) from Dow Corning (X-1541). HSQ is known to have sub 5 nm resolution and high etch resistance [51]. The original 6% HSQ solution was diluted to 2% concentration in methyl isobutyl ketone (MIBK) and spin coated at 2000 rpm for 30 s to yield a 40 nm thick HSQ layer. Then the samples were baked at 90 °C for 2 min and exposed using the EBL tool. After EBL, the samples were developed with a high-contrast tetramethylammonium hydroxide (TMAH) based development process [52] and dried with a N₂ gun. The HSQ patterns were transferred into the top SOI layer using a SENTECH’s ICP-Reactive Ion Etcher SI 500. The parameters of the etching process were: ten standard cubic centimeters per minute (sccm) SF₆, 20 sccm C₄F₈, 5 sccm O₂, 0.9 Pa chamber pressure, 400 W ICP power, and 12 W RF power. After the SiNW fabrication, a second EBL-based patterning was performed for Ni contact formation using a positive tone resist, ZEP520A (ZEON Corporation, Tokyo, Japan). The exposure parameters were: A total of 10 kV acceleration voltage, 10 μm aperture size and area dose of 40 μC/cm². The development was performed in n-amyl acetate solution (ZED-N50, ZEON Corp.). This was followed by baking at 200 °C for 5 min to smoothen the side walls of the patterned structures. Prior to Ni sputtering, the Si native oxide was etched away from NWs using 1% buffered hydrofluoric acid (BHF) solution and then the samples were transferred into the sputtering chamber. The sputtering was performed at 10 keV with a Gatan 681 High-Resolution Ion Beam Sputter Coater. The sample holder was rotated at a speed of 40 rpm for uniform deposition of Ni at a rate of 1.3 ± 0.2 Å/s. The thickness of Ni was varied between 35 and 50 nm according to the requirements of the experiments. After the sputtering step, lift-off was carried out in N-methyl-2-pyrrolidone (NMP) at 50 °C for 10 min. The samples were then rapid thermally annealed (RTA) at 450 °C in forming gas atmosphere (a mixture of 10% H₂ and 90% N₂) for silicidation of the NWs. The annealing time was varied in order to control the axial diffusion length of Ni into the SiNW. The role of the Ni pads was two-fold: Firstly, they acted as a Ni reservoirs for silicidation of NWs, and secondly, they served the purpose of a contact electrode.

To investigate silicidation of nanowires covered with an oxide shell, the samples were thermally oxidized. The oxidation process started with removal of the native oxide from the samples by dipping them in 1% BHF for 15 s. This was followed by an immediate transfer of samples in a pre-heated (875 °C) rapid thermal oxidation chamber. The samples were kept in the chamber for 10 min in the presence of an oxygen flow of 10 standard liters per minute (slm). Subsequently, the samples were annealed at 875 °C in a nitrogen environment for 5 min. This was followed by annealing in forming gas atmosphere. The oxidation process generates heavy stress in the nanowire due to the volume expansion. This impacts the oxygen diffusion in Si and the surface reaction rate at the Si–SiO₂ interface drops. Therefore, the oxidation process is self-limited [53,54] (i.e., the stress generated by the oxidation process prevents further oxidation of the nanowires). After the oxidation of nanowires, a second EBL step for Ni contacts formation and subsequent annealing for silicidation was performed according to the aforementioned conditions.

To analyze the silicidation process, SEM and TEM investigations were performed. The systems used for SEM and TEM were Raith e-Line Plus and Zeiss Libra 200 TEM, respectively. TEM samples were prepared using focused ion beam (FIB) in a FEI Helios Nanolab 660 machine applying low-damage recipes to preserve the native crystal structure [55].

3. Results and Discussion

3.1. Silicidation in Si Thin Film Structures

To study silicidation in thin films structures, Si pads were patterned in Si substrates in <110> and <100> orientations using EBL and dry etching processes. Ni sputtering and subsequent annealing for silicidation was carried out according to conditions mentioned in Section 2. The purpose of this first study was to determine an initial process window for the nanowire silicidation. Figure 1 shows top-view SEM images of a sample after silicidation. Annealing was performed at 450 °C in forming gas atmosphere for 10 min. It is evident from the bright regions of the Si pads in Figure 1 that the Ni diffusion was not fast enough to reach the nanowires and it was confined within the Si pads. Moreover, the silicide–Si interface has different shapes in Si pads with <110> and <100> orientations. The silicide makes a 90° angle with Si in <110> orientation, whereas in the <100> orientation, the silicide has a step-like interface with Si.

TEM analysis was performed on lamellas, prepared by FIB, from the selected samples. The cross-section was inspected by high-resolution transmission electron microscopy (HREM) and electron energy loss spectrum (EELS). Figure 2 shows the overview of the cross-section with the different layers included in it. The top most sample layer is covered by a carbon protection layer, which is part of the FIB milling process to mitigate the damage incurred by FIB. Below the carbon layer, there are two Ni silicide layers and the Si substrate. The top Ni-containing layer depicts a Ni-rich silicide phase (region I). The following layer has a Si-rich silicide phase (region II). The interface between region I and II is smooth, whereas the interface between regions II and the Si substrate (region III) is rough and jagged. It is evident from Figure 2b–d that the silicide in region II has followed preferential crystal directions. The HRTEM image in Figure 3e shows an abrupt change in the silicide phase from NiS₂ to Ni-rich phase.

To further investigate the silicidation process, zero-loss TEM was performed [56]. The images are presented in Figure 3. The Ni map shows higher concentration of Ni in region I compared to region II. Fast Fourier transform (FFT) confirms that the silicide phase in region II has a cubic lattice structure in accordance to NiSi₂. The silicide in region I is Ni-rich and it has a non-cubic structure. The NiSi₂–Si interface is atomically sharp (Figure 3c).

3.2. Silicidation in Nanowires

After determining an initial silicidation process window from the experiments for silicidation in thin film structures presented in the previous section, experiments for nanowire silicidation were performed. For these experiments, nanowires were fabricated in <100> and <110> crystallographic orientations using the top-down approach. Ni was sputtered according to the conditions described in the Materials and Methods section and, subsequently, rapid thermal annealing was performed at 450 °C in forming gas atmosphere for 80 s. The resulting structures are shown in Figure 4.

As illustrated in Figure 4, the silicide diffusion length is larger in <100> NWs compared to <110> NWs. Appenzeller et al. [29] have shown that silicidation diffusion length is inversely proportional to square of the diameter of the NW. The widths of <100> and <110> NWs in Figure 4a are 28 and 24 nm, respectively, while the silicide diffusion lengths are 745 and 628 nm, respectively. This shows a strong dependence of silicide length on the nanowire orientation. To investigate in detail the dependence of Ni diffusion and silicide formation on crystallographic orientations of NWs, a circular array of NWs with five-degree separation was fabricated. It was followed by the aforementioned steps for silicidation. The results are shown in Figure 5.

Although the silicide diffusion length varies in different crystallographic orientations of the NWs, it was not possible to extract a clear relation since the results vary in different arrays. To further investigate the orientation dependence of the silicide formation, silicidation of nanowire arrays fabricated in <100> and <110> crystallographic orientations was carried out and the results are presented in Figure 6a–d. The width of the NWs is 20 nm. The average silicide diffusion length in <100>- and <110>-oriented SiNWs is 812 and 744 nm, respectively (see Figure 6e). The images distinctly show that the diffusion of Ni and the silicide progression into the NWs of the same array is not homogeneous and on average has scattering of up to 300 nm in <100> and 400 nm in <110> NWs. Silicidation rates are known to vary based on different factors, including the quality of interface between the Ni reservoir and the NW [21]. However, our investigation shows this variation also within an array of NWs, which is processed under the same conditions. We attribute this variation in silicide length to different surfaces of NWs, as these NWs are top-down fabricated and their surfaces can be different due to the subtractive nature of the etching process. Because of this uncontrolled silicide formation and scattered positioning of the Schottky junctions, large top gates have to be placed to ensure that they properly cover the junctions at the two sides of the NWs [14,34]. This limits the possibilities for downscaling the size of devices and compromises their large-scale fabricability.

To have better control over the silicidation length, further investigations were carried out with sets consisting of two and three NWs. The results are shown in Figure 7. It was expected that the outer two NWs might consume excess Ni, giving a better control over the silicide progression in the central NW. However, it was still not possible to obtain a proper control over the silicide progression with this technique. The silicide diffusion length varied in different groups of NWs. Interestingly, the outer nanowires appear to exhibit a distinct silicide phase compared to the inner ones, as indicated by their higher brightness. While the inner NWs appear to have a NiSi₂ phase with a comparable lattice constant to that of Si, the outer ones have Ni-rich phases with a larger lattice constant. This might be an effect of Ni source “competition” between neighboring nanowires. Apparently, the outer nanowires receive their Ni supply from a longer extent, thereby limiting that supply to the inner nanowires.

Dellas et al. [27] and Lin et al. [28] claimed that an oxide shell around the NWs hinders diffusion of silicide into the NWs. Therefore, expecting a better control, further investigations were made with oxidized NWs. However, it also resulted in non-uniform diffusion of silicide into the NW, as shown in Figure 8.

3.3. Properties of Silicide–Si Interface

To investigate the phase of the silicide and the quality of the silicide–Si interface, an exemplary NW was sectioned parallel to its length. Subsequently, HRTEM was performed. The resulting images are shown in Figure 9. Starting with Ni-rich phases near the Ni-reservoir, the Si fraction increases towards the silicide–Si interface.

HRTEM images show the formation of an atomically sharp Schottky junction, which is required for size downscaling and enhanced performance of the devices. FFT studies confirmed the formation of the desired NiSi₂ near the silicide–Si interface. The interface orientation is {111} in accordance with [16].

In order to better understand our experimental observations, we calculated interface energies using density functional theory (DFT) as implemented in Atomistix ToolKit 15.1 [57]. The Perdew–Burke–Ernzerhof exchange-correlation function from [58] was used and the reciprocal space was sampled with a spacing of around 0.25 nm⁻¹.

A periodic structure consisting of alternating silicon and NiSi₂ was studied. The length of the resulting supercell perpendicular to the interface was at least 12 nm. Periodic boundary conditions were employed in the parallel directions. The atomic arrangements of the studied interfaces are described in [59]. In order to mimic our experimental setup of a nanowire lying on a substrate, the lattice constants in the silicon and NiSi₂ regions were both fixed to the silicon lattice constant of the undisturbed silicon crystal. The atomic coordinates of all atoms within a 10 nm neighborhood around the interface were relaxed.

We defined the interface energy density as:

$${ϵ}_{\mathrm{interface}}=\left(E_{\mathrm{supercell}}-N_{{\mathrm{NiSi}}_2}{E}_{{\mathrm{NiSi}}_2}-N_{\mathrm{Si}}{E}_{\mathrm{Si}}\right)/2A.$$

(1)

$E_{\mathrm{supercell}}$ is the total energy of the calculated supercell, $E_{{\mathrm{NiSi}}_2/\mathrm{Si}}$ are the total energies of bulk unit cells, and $N_{{\mathrm{NiSi}}_2/\mathrm{Si}}$ follows from the number of unit cells in the supercell. $A$ is the cross-section of the system and the factor 2 arises because two interfaces are included in a single supercell.

The calculation resulted in interface energy densities of around 2.2 eV/nm² for the {111} interface (an A-type interface was assumed, see [59] for details) and around 4.2 eV/nm² for the {110} interface. This effect is partially compensated by the higher area of a {111} interface in a <110> nanowire, because an angle of 35° between the normal vector of the interface and nanowire orientation occurs. For geometrical considerations, the interface area is increased by a factor of around 1.2 compared to a {110} interface. Hence, the total energy contribution of the interface is smaller for a tilted {111} interface, which makes such an interface energetically more favorable. The experimental observations of the {111} interface are; therefore, explained by the calculated interface energy densities.

3.4. Electrical Characterization of Fabricated Devices

To test the outcome of the silicidation process, electrical characterization of devices based on single unoxidized NWs patterned in both <100> and <110> orientations was carried out by back-gating. The back-gate voltage (V_bg) was swept between −40 to 40 V in a butterfly loop (0 to 40 V, 40 to −40 V, and −40 to 0 V). The drain to source voltage (V_ds) was varied from 0.25 to 1 V. The devices exhibit large hysteresis as the nanowires are not passivated. We extracted a single sweep from the transfer characteristics, as illustrated in Figure 10. The minimum of the curves was shifted to left by 17 V to center the curves around 0 V. An ambipolar behavior of devices was found. The currents in <110>-oriented devices are higher compared to the currents in <100> devices. At V_ds = 1 V, the values of n- and p- currents in <110> devices are 40.7 and 450.0 nA, while in <100> the values are 16.8 and 207.0 nA, respectively. The shift of original curves away from 0 V is attributed to a built-in potential on the NW surface in ambient conditions in the absence of passivation with, for example, an oxidation layer [34]. Unipolar behavior in these devices can be attained by using multiple gate electrodes [9], while p/n current symmetry, which is required for energy efficient functioning of circuits based on RFETs, can be tuned by oxidation induced stress [9,14].

4. Conclusions

In this work, we studied Ni silicidation of silicon thin films and top-down fabricated SiNWs by using the RTA technique. We paid special attention to the formation of the required silicide phase (NiSi₂), the quality of the Schottky junctions, and the reproducibility of the silicide length along the nanowires, which are very important for device performance and scalability. To investigate the influence of the NW orientations on the silicidation process, SiNWs with different crystallographic orientations were silicided. Although large scattering in the silicidation lengths of nanowires was observed even for the nanowires of the same orientation, the silicidation in <100> nanowires is found to be faster than that in <110> nanowires. Furthermore, TEM and FFT analyses revealed the formation of sharp Schottky junctions with {111} interfaces and the NiSi₂ phase of silicide required for the fabrication of RFETs. Density functional theory calculations showed that {111} interfaces are energetically favorable. Control over the diffusion length of silicide into the NW was not achieved. This makes placing of top gates on the Schottky junctions and downscaling of devices a challenge. Alternative annealing techniques with shorter annealing times, like, for example, flash lamp annealing, may be employed to have better control over the silicidation process. Transfer characteristics of the back-gated devices with single unoxidized NWs patterned in <100> and <110> orientations illustrate ambipolar behavior, with currents in <110>-oriented devices being higher compared to the currents in <100> devices.