A Data-Centric Architecture for Smart Cable Harness Assembly: 100% Continuity Testing, Pin-to-Pin Miswiring Diagnosis, Productivity Improvement, and Achieving Zero Customer Defects

Abstract

Manual assembly of multi-pin cable harnesses remains vulnerable to miswiring issues when conductors are visually indistinguishable. This paper presents an industrial case study of a quick-connect harness composed of two connectors (receptacle-type and pin-type) linked by 16 black conductors (2.5 mm² and 200 mm length), where the dominant failure mode is a two-wire swap that breaks correct pin-to-pin mapping and may cause downstream equipment damage. In the baseline state, end-of-line verification relies on visual inspection only (1 min/unit), resulting in an internal nonconformity rate of 4% (repairable). To achieve the operational goal of zero defects (zero escapes), we proposed and integrated an electronic pin-to-pin continuity and mapping fixture as a deterministic End-of-Line (EOL) quality-gate implementing poka-yoke logic (“no PASS—no shipment”) and enabling structured traceability records. Using a before–after workload model that includes a mandatory retest after rework, the fixture reduces test time to 0.33 min/unit. For a monthly volume of 1500 units, total quality workload (test + rework + retest) decreases from 31 h/month to 13.58 h/month, releasing 17.42 h/month. Global quality productivity increases from 48.39 units/h to 110.46 units/h (+128%). The proposed architecture couples deterministic electrical verification with data logging aligned to digital-thread and data-driven quality-management concepts to sustain continuous improvement and prevent customer escapes.

1. Introduction

In the context of current industrial competitiveness, productivity growth no longer depends exclusively on increasing the workload, but on the company’s ability to design and control processes through mathematical models, optimization methods, and analytical tools that reduce variability, unnecessary resource consumption, and non-productive time. For a performance-oriented enterprise, the use of these approaches enables decisions to be based on objective data, which leads to more stable processes, better controlled costs, and superior use of production capacity [1,2,3,4].

From this perspective, the topic of the present paper is relevant because a data-centered architecture for intelligent wire harness assembly is not merely a technical verification solution, but also a managerial mechanism through which the company can increase system productivity. When processes are supported by dedicated devices, control logic, and modern production improvement tools, the organization succeeds in reducing errors, shortening execution cycles, and increasing the repeatability of results, all of which are essential for operational efficiency and consistent quality [4,5,6].

The literature highlights that the application of linear programming, optimal control, and other mathematical methods in production planning and launch directly contributes to the selection of advantageous decision alternatives, the balancing of resource loading, and the reduction in losses generated by the inadequate organization of the technological flow. At the same time, the use of DFM principles and modern process optimization tools makes it possible to reduce manufacturing times and adapt the company more rapidly to market requirements, thereby supporting long term competitiveness [2,3,5,6].

Therefore, for a company seeking to become as efficient as possible, the integration of mathematical models, control devices, and modern analytical tools should be regarded as a strategic investment in productivity. In line with the title of the paper, the proposed data-centered architecture can be understood as part of a broader direction of transforming manufacturing systems into intelligent structures capable of preventing nonconformities, supporting operational decisions, and creating the conditions for sustainable industrial performance [1,2,3,4,5,6].

In the literature, multi-pin wiring harness verification is typically addressed through end-of-line (EOL) testing based on continuity, insulation/resistance tests, and approaches focused on traceability and integration into digital production flows. However, many existing solutions treat separately (i) the electrical conformance verdict, (ii) precise pin-to-pin miswiring diagnosis, and (iii) data capture for traceability and organizational learning. In practice, this separation leads to situations where a defect is detected, but the root cause is not operationally guided to the operator, and test data are not sufficiently structured for longitudinal analysis and continuous improvement.

Therefore, there is a gap between test systems that can only deliver a PASS/FAIL verdict and the industrial need to simultaneously provide a deterministic quality gate, actionable pin-to-pin diagnosis, and full unit-level traceability integrated within a data-centric architecture.

The contributions of this study are (1) a deterministic verification and pin-to-pin miswiring diagnosis logic that enables guided correction and fast retesting; (2) a minimal yet sufficient data model for unit-level traceability and trend analysis (digital thread); and (3) an operational evaluation framework that quantifies the impact on inspection time, rework, and overall productivity in a real industrial case.

In this paper, the term “zero defects” is used strictly in the sense of zero customer escapes (zero shipped defects), i.e., operating as a quality gate that prevents shipment of nonconforming units, without implying complete elimination of defect occurrence at the source.

Smart manufacturing aims to improve operational performance by reducing process variability through standardization, connectivity, and data-driven control. In this context, the concept of digital threading continuity and integration of product and process information across lifecycle stages has gained significant attention as a foundation for traceability, systematic quality improvement, and closed-loop decision-making. Recent studies emphasize both the definitional consolidation of digital-thread concepts and the practical challenges of implementation, such as data integration across heterogeneous systems and ensuring actionable continuity of information from design to manufacturing and operations [7,8].

Despite ongoing advances in automation, many industrial assembly environments remain strongly dependent on manual work. As a result, human error continues to be a key contributor to quality losses, especially in repetitive or cognitively demanding assembly tasks. Empirical research in complex manual assembly has shown that manufacturing systems are sensitive to human reliability factors, and that error mitigation often requires structured interventions: improved work instructions, systematic feedback, and objective verification at critical steps [9]. These findings reinforce the need to strengthen quality assurance in manual or semi-manual operations by reducing reliance on subjective judgment and increasing the repeatability of inspection and control.

A widely adopted principle for robust production systems is mistake-proofing (poka-yoke), which focuses on preventing errors or making them immediately detectable at the point of occurrence. In smart production settings, poka-yoke has been combined with operator guidance systems (e.g., pick-to-light) to reduce picking/assembly errors while improving operational efficiency and accuracy [10]. In addition, poka-yoke can be implemented not only at the workstation level but also as a process gate (shipment gating), where defective products are systematically blocked from moving downstream until corrected and re-verified.

This paper addresses an industrial case involving a quick-connect electrical harness consisting of two main connectors (a receptacle-type connector and a pin-type connector) linked by 16 conductors, each with 2.5 mm² cross-section and 200 mm length, with crimped terminals at both ends. The manufacturing route includes procurement and incoming inspection, cable cutting to length, crimping, intermediate checks, connector assembly, and final inspection prior to packing and shipment. A critical product characteristic is that all conductors are black, which makes visual confirmation of the correct pin-to-pin wiring map unreliable without auxiliary marking or measurement. Under these constraints, visual inspection may confirm gross completeness but cannot robustly validate correct circuit mapping.

The dominant nonconformity observed in production is a miswire (swap) of two conductors among the 16 circuits, leading to an incorrect connector-to-connector mapping. In the baseline condition, quality control relied on visual inspection only (mean inspection time 1 min/unit) and the internal nonconformity occurrence rate was 4%.

In the context of ISO 9001-based quality management, organizations are required to monitor, measure, analyze, and evaluate relevant quality-management performance indicators and to control nonconforming outputs and nonconformities through corrective-action processes [11,12]. Accordingly, in this study, the internal nonconformity occurrence rate is operationalized as the percentage of internally detected nonconformities relative to the relevant total volume checked or produced within the same period.

General formula (percentage):

$$\mathrm{Internal} \mathrm{nonconformity} \mathrm{rate} (\%)={\displaystyle \frac{N_{NC, internal}}{N_{totalinspected/produced/transactions checked}}}\times 100$$

(1)

where:

• $N_{NC, internal}$ is the number of nonconformities detected internally (in production, quality control, internal audit, etc.)
• $N_{total}$ is the total number of units/lots/operations/records inspected, or deliverables produced (the reporting base must be clearly defined)

If the rate was 4%, the equivalent relationship is:

$${\displaystyle \frac{N_{NC, internal}}{N_{total}}}=0.04\Rightarrow N_{NC, internal}=0.04\times N_{total}$$

(2)

For such wiring-map defects, automated verification is often preferred because it directly tests the electrical topology rather than inferring correctness from visual cues. Research on the automation of electrical cable harness testing discusses the feasibility of automated harness testing and highlights strategies to improve adaptability and scalability, including modular hardware/software concepts suitable for broad product ranges [13]. Complementarily, data-driven approaches have also been explored, including AI-based fault detection methods intended to improve quality-control effectiveness in wiring harness manufacturing contexts [14].

Motivated by these approaches, this paper proposes a data-centric architecture that integrates an electronic test fixture into the production flow as a mandatory gate prior to packing. The fixture performs 100% continuity testing and reconstructs the complete pin-to-pin connectivity map, enabling deterministic classification of actionable fault categories: open circuits, short/bridging faults, and miswires (swaps). The system outputs standardized diagnostics to guide rework and retest, and logs test outcomes (unit/lot ID, timestamp, PASS/FAIL, defect type, and affected positions) to support traceability and continuous improvement in line with digital-thread principles [7,8].

A core operational objective of the proposed architecture is zero customer defects, achieved not by assuming error elimination at the source, but by enforcing a poka-yoke shipment rule: no unit may proceed to packing without a PASS result. Units that fail are routed to rework and must be retested until they pass. This form of error-proofing is consistent with broader industrial implementations of sequencing and verification systems that strengthen real-time traceability and prevent process deviations from propagating downstream; for instance, RFID-based sequencing-error-proofing solutions have been reported to improve visibility and control in manufacturing logistics [15]. Beyond quality protection, the proposed fixture reduces test time to 0.33 min/unit, increasing inspection throughput and reducing total QC-plus-rework time at a monthly volume of 1500 units.

The contributions of this work are fourfold (i) an industrially deployable fixture-based method for automated pin-to-pin verification of multi-circuit harnesses with visually indistinguishable conductors; (ii) a deterministic diagnosis workflow for miswiring detection supporting rapid, standardized rework; (iii) a traceability-oriented data model aligned with digital-thread concepts; and (iv) an operational analysis demonstrating productivity gains while supporting the goal of zero customer defects through a poka-yoke shipment gate.

The remainder of this paper is organized as follows. Section 2 details the manufacturing context, the fixture architecture, and the pin-to-pin mapping method. Section 3 highlights the methodology and test logic. Section 4 presents the operational calculations and productivity analysis. Section 5 discusses implementation considerations and limitations. Section 6 concludes the paper and outlines future enhancements.

2. Materials and Methods

2.1. Industrial Context and Product Description

This research is grounded in an industrial production setting manufacturing a quick-connect cable harness intended for industrial equipment (Figure 1). The product consists of two main connectors—a receptacle-type connector (“female”) and a pin-type connector (“male”)—interconnected by 16 individual conductors assembled into a compact harness. Each conductor has a 2.5 mm² cross-section and a nominal length of 200 mm. All conductors are black, eliminating color-based discrimination and increasing the risk of wiring swaps during assembly.

Each conductor is terminated at both ends by a crimped contact that is inserted into the connector cavities according to a specified pin-to-pin mapping. The critical-to-quality (CTQ) characteristic is the mapping correctness (topology) rather than the mechanical presence of terminals alone. A two-wire swap among the 16 circuits constitutes the dominant defect mechanism and can lead to functional nonconformity, equipment malfunction, or potential damage, depending on the downstream application. The product configuration and its susceptibility to human error are consistent with findings in complex manual assembly, where similarity and repetition increase the likelihood of selection/insertion errors [9].

In terms of manufacturing inputs, the typical bill of materials includes (i) two connector housings (female and male); (ii) 32 terminals/contacts (two per conductor); (iii) 16 cable segments; and (iv) auxiliary items for packing and labeling. Manufacturing resources include cutting equipment, crimping tools (manual or semi-automatic), insertion tools (if applicable), and work instructions defining the nominal pin map and assembly sequence.

2.2. Process Route and Baseline Inspection

The end-to-end process route follows a conventional multi-stage manufacturing flow: customer request/quantity definition; quotation; procurement from suppliers; raw material storage; incoming inspection; cable cutting to 200 mm; length verification; crimping; crimp inspection; component staging; harness assembly; end-of-line verification; packing; and shipment (Figure 2). The route includes at least three quality-relevant control points: incoming inspection, in-process checks (length and crimp), and final verification.

The final verification stage is critical because upstream inspections do not guarantee pin-to-pin mapping correctness. For example, correct cable length and acceptable crimp geometry do not prevent a conductor from being inserted into the wrong cavity. In multi-stage manufacturing systems, such hidden defects can propagate unless explicitly captured at a properly designed quality gate [16].

Baseline EOL inspection was visual-only (no multimeter), with mean test time of 1 min/unit. The internal nonconformity rate was 4%, and defects were repairable. Because the dominant defect is miswiring (two-wire swap) in visually identical conductors, visual inspection provides limited detection capability; strengthening the EOL gate is consistent with the multi-stage quality-control literature [16,17].

2.3. Proposed Solution: 100% Electronic Continuity and Mapping Test Fixture (EOL Poka-Yoke)

To achieve the operational goal of zero customer escapes, the proposed intervention is an electronic EOL test fixture performing 100% continuity testing and pin-to-pin mapping verification for all 16 circuits. The fixture is positioned immediately after assembly and before packing, establishing a deterministic EOL quality gate (Figure 3).

The gate is implemented via a poka-yoke rule: “no PASS—no shipment.” Under this rule, any unit failing the mapping test is blocked from packing/shipment and routed to rework, followed by mandatory retest until PASS. Such mistake-proofing logic is consistent with poka-yoke principles emphasizing immediate detection and prevention of defect flow to the customer [18,19]. In addition, formalization of EOL decision-making is aligned with quality-gate and virtual-quality-gate approaches used to prevent defect propagation in multi-stage systems [16,17].

In this work, the acceptance decision is topology-based: the fixture validates that every pin on connector A maps to the correct pin on connector B, and that no opens/shorts are present. Resistance thresholds are not used as acceptance criteria in this version, because the dominant defect risk is miswire topology rather than contact degradation.

2.4. Data-Centric Architecture and Process Integration

The data-centric architecture is operationalized through a minimal set of entities and fields: unit identifier (UID), test timestamp, product/variant configuration, PASS/FAIL result, defect type (taxonomy), involved pin pairs, station/operator, number of retests, and durations. This structuring enables both traceability of a single event (when, where, who, and what defect) and aggregation across batches, shifts, or time windows (e.g., the frequency of swaps on specific pins).

In a minimal scenario, data are exported periodically for reporting and analysis; in a full scenario, the test outcome controls unit release into the flow (digital quality gate) and can be integrated with MES/ERP via API services or standard data-exchange mechanisms.

A key design aspect is that the fixture is not only a test device but also a data source for quality management. Each unit tested generates a structured record containing, at minimum (i) unit or lot identifier; (ii) timestamp; (iii) PASS/FAIL verdict; (iv) defect class (open/short/miswire); (v) pin-level diagnosis (e.g., swapped cavities/pins); and (vi) rework/retest cycle count. This data model supports traceability and continuous improvement.

The approach is consistent with digital-thread concepts, where product and process data are linked across lifecycle stages to enhance decision-making and root-cause analysis [7,20]. It also aligns with data-driven quality-management approaches in multi-stage manufacturing, where structured inspection data enable actionable analytics and prioritization [21]. In industrial deployment, these data can be exported to a local database, a manufacturing execution system (MES), or enterprise resource planning (ERP) systems to enable lot-level reporting and auditability.

2.5. Evaluation Design, Metrics, and Assumptions

To quantify the impact on internal quality and rework volume, we define below the internal nonconformance rate on a consistent basis: the number of nonconforming units identified in internal control relative to the total number of units produced in the analyzed period.

In the baseline model, the internal rate p₀ is kept constant to isolate the effect of the quality gate on rework volume and inspection time. This assumption does not claim that defect generation at the source remains unchanged; rather, it provides a conservative comparison framework: even without upstream improvements, the system can prevent shipment and reduce total effort through rapid diagnosis and retesting.

In practice, p can become a time-dependent function p_(t), because diagnostic data can feed process improvement (training, ergonomics, and standard work). A realistic scenario is a gradual decrease in p as recurring causes are eliminated, which amplifies the model benefits: rework decreases and throughput becomes more stable.

A before–after evaluation was conducted using a monthly workload model based on: N = 1500 units/month, baseline internal nonconformity rate p₀ = 4%, baseline test time t_test,0 = 1 min/unit, rework time t_rw = 5 min/defective unit, and post-implementation test time t_test,1 = 0.33 min/unit. Retest after rework is mandatory in both scenarios to ensure shipment of conforming products.

The model focuses on operationally relevant indicators (i) total monthly QC workload (test + rework + retest time); (ii) global QC productivity computed over total QC workload; (iii) released time/capacity; and (iv) customer escapes targeted to zero via enforced EOL gate logic.

The internal nonconformity rate p₀ is treated as an occurrence rate that may not immediately change due to the gate itself; however, the gate prevents shipment of nonconforming units. This interpretation is consistent with the quality-gate literature, which differentiates internal defect occurrence from outgoing quality (escape rate) [16,17]. In subsequent continuous improvement cycles, the logged data are expected to support upstream preventive actions that reduce the internal occurrence rate over time [21].

3. Methodology and Test Logic

3.1. System Overview

To ensure repeatable end-of-line (EOL) verification and actionable fault localization in cable harness assembly, the proposed solution is implemented as an integrated verification system that combines a dedicated mechanical interface with an electronic addressing layer, deterministic continuity/mapping evaluation, and operator-oriented guidance. This system-level integration follows the general direction reported in the harness testing automation literature, where adaptable architectures and short cycle times are emphasized, and industrial solutions are shown to detect incorrect pinning efficiently.

The main building blocks of the verification system are summarized below:

• a mechanical fixture enabling repeatable mating to both connectors;
• an electronic addressing layer (e.g., switching/multiplexing);
• a continuity and mapping evaluation module;
• HMI feedback (PASS/FAIL + fault guidance);
• data logging for traceability and improvement.

The automation literature on harness testing emphasizes adaptable architecture, and reported industrial systems can detect incorrect pinning with short test times [13,22].

3.2. Acceptance Criterion (No Resistance Thresholds in the PASS/FAIL Verdict)

Given that the dominant risk is a topological error (miswire/swap), the PASS/FAIL verdict is based strictly on:

• continuity for all circuits;
• absence of short/bridging faults;
• conformance of measured mapping to the nominal mapping.

Resistance can be captured as optional diagnostic metadata, but it is not required for the acceptance decision in this study. Where needed, standardized contact resistance test methods are available (e.g., IEC 60512-2-1 and MIL-STD-202 Method 307) [23,24].

3.3. Pin-to-Pin Mapping Model and Fault Taxonomy

Let connector A pins be $i\in \{1,\dots ,16\}$ and connector B pins be $j\in \{1,\dots ,16\}$. The fixture constructs a connectivity matrix $C\in \{\mathrm{0,1}{\}}^{16\times 16}$:

$$C_{ij}=\left\{\begin{array}{cc}1,& \mathrm{if} \mathrm{continuity} \mathrm{exists} \mathrm{between} \mathrm{pin} i \left(\mathrm{A}\right) \mathrm{and} \mathrm{pin} j \left(\mathrm{B}\right)\\ 0,& \mathrm{otherwise}.\end{array}\right.$$

(3)

Conformance is achieved when each row and column contains exactly one “1” and the mapping equals the nominal mapping $p\left(i\right)$. Fault classes:

$$\mathrm{Open} \mathrm{circuit}: {\sum }_j{C}_{ij}=0 \mathrm{for} \mathrm{any} i$$

(4)

$$\mathrm{Short/bridging}: {\sum }_j{C}_{ij}>1 \mathrm{or} {\sum }_i{C}_{ij}>1$$

(5)

Miswire/swap: bijective mapping differs from nominal (swap pins reported).

This fault taxonomy is aligned with the harness test automation literature and reported industrial systems [13,22].

3.4. Scan and Decision Procedure (Deterministic Miswiring Diagnosis)

The diagnostic procedure starts with the expected mapping (a list of pin-to-pin pairs) and constructs the observed mapping by scanning the fixture. It then compares the two representations and determines the defect type.

The steps are (1) initialization and product/variant identification; (2) sequential continuity scan to construct the connectivity matrix C; (3) derivation of the observed mapping from C; (4) comparison with the nominal mapping and classification into PASS, two-wire swap, open, short, or ambiguous case; (5) display of corrective instructions to the operator; and (6) retest and logging of the final result. Ambiguous cases are those where multiple configurations can explain the same matrix (e.g., multiple defects or unstable contacts); these are handled via re-scan and/or escalation to re-inspection.

Scan: address each $i$ on connector A and test continuity against each $j$ on connector B to populate C.

• Decision:

• open detected → FAIL;
• short/bridging detected → FAIL;
• else mapping equals nominal → PASS; otherwise → FAIL with explicit swap diagnosis;
• FAIL → rework + mandatory retest until PASS.

3.5. Traceability Record Structure (Data-Centric Element)

Data are stored in a database (relational or time-series, depending on factory infrastructure), and each record is associated with the unit UID. Event sampling is per test (start/stop, verdict, and diagnosis), and data retention is defined by internal policies (e.g., keeping records for the product warranty period and compliance obligations).

For each tested unit, the system stores:

• unit ID/lot ID, timestamp;
• PASS/FAIL;
• defect class (open/short/miswire);
• affected pins (e.g., swapped indices);
• number of rework/retest cycles;
• optional station/operator identifier.

This minimal dataset supports Pareto analyses, targeted training, and continuous improvement consistent with digital-thread and data-driven quality-management approaches [7,20,21].

3.6. Practical Considerations

In industrial operation, beyond the test logic itself, system performance and repeatability depend on practical factors such as contact stability in the fixture, switching times of the matrix, and how the operator receives diagnostic feedback. The following considerations summarize key implementation aspects that ensure reproducibility and robustness in production.

To reduce the influence of unstable contacts (contact bounce), the connectivity verdict can be validated by repeating the measurement/scan on the same pin selection and by applying a consistency rule (e.g., accepting only if the same result repeats). If results are inconsistent, the system flags the case as unstable and requests refixation of the harness, preventing erroneous diagnoses.

The HMI interface transforms the diagnostic result into an actionable instruction (Figure 4). After scanning, the operator receives the verdict (PASS/FAIL), defect type (e.g., swap), the involved pin pairs, and a recommended action (e.g., “swap wires between pin X and pin Y”). To minimize interpretation time, the display is standardized (defect codes and visual highlight of pins), and retest history for the same unit is retained.

• Fixture wear and mating stability: periodic inspection and replacement are required to prevent intermittent contact effects. Standards and methods exist to support contact resistance characterization if introduced [23,25];
• Upstream workmanship criteria: the EOL gate complements—rather than replaces—workmanship/acceptance practices for harness assemblies (e.g., IPC/WHMA-A-620) [24];
• Scalability: higher pin counts increase scan complexity; modular architectures support adaptation, as recommended in harness testing automation research [13].

4. Results

4.1. Quality Impact: Enforcing Zero Customer Defects (Zero Escapes)

In addition to operational impact, system performance can be characterized through detection/diagnosis indicators: detection rate (sensitivity), false positive rate, and the ability to handle multiple-defect cases. In this work, deterministic logic based on the connectivity matrix reduces ambiguity for dominant defects (e.g., two-wire swaps), while atypical cases (e.g., intermittent contacts) can be labeled as “unstable result” and routed to re-inspection/refixation.

For statistical reporting, results should be contextualized by volume and period: within the analyzed interval March 2025–August 2025, 9000 units were tested and the number of customer escapes was 0, indicating the effectiveness of the quality gate in preventing shipment of nonconforming units in the observed time window.

Visual-only inspection has limited capability to confirm correct pin-to-pin mapping when conductors are indistinguishable. The proposed system enforces a poka-yoke EOL rule (“no PASS—no shipment”), which eliminates customer escapes by preventing shipment of miswired units. This aligns quality-gate principles [16,17] and the mistake-proofing literature [18,19].

Interpretation notes: “zero customer defects” here means zero shipped defects (zero escapes); internal defects may still occur but are detected and corrected before shipment by the EOL gate [16,17].

4.2. Workload Recalculation (Test + Rework + Retest)

Monthly defective units:

$$N_{def}=N\cdot p_0=1500\cdot 0.04=60 \mathrm{units}/\mathrm{month}$$

(6)

Before implementation (visual test + rework + visual retest):

$$T_0=N\cdot t_{test,0}+N_{def}\cdot t_{rw}+N_{def}\cdot t_{test,0}$$

(7)

$$T_0=1500\cdot 1.00+60\cdot 5.00+60\cdot 1.00=1860 \min /\mathrm{month}=31.00 \mathrm{h}/\mathrm{month}$$

(8)

After implementation (fixture test + rework + fixture retest):

$$T_1=N\cdot t_{test,1}+N_{def}\cdot t_{rw}+N_{def}\cdot t_{test,1}$$

(9)

$$T_1=1500\cdot 0.33+60\cdot 5.00+60\cdot 0.33=814.8 \min /\mathrm{month}\approx 13.58 \mathrm{h}/\mathrm{month}$$

(10)

Time released:

$$\Delta T=T_0-T_1=1045.2 \min /\mathrm{month}\approx 17.42 \mathrm{h}/\mathrm{month}$$

(11)

These results are coherent with the multi-stage quality-control literature, where strengthening EOL verification reduces total quality workload and prevents downstream propagation [16,17].

Table 1. Input parameters and derived monthly indicators for the before–after evaluation (visual inspection vs. EOL fixture).

Category	Parameter	Symbol	Baseline (Visual)	After Implementation (EOL Fixture)	Unit/Notes
Production	Monthly production volume	N	1500	1500	units/month
Quality (internal)	Internal nonconformity rate (occurrence)	$p_0$	0.04	1.2%	* Occurrence assumed unchanged; customer escapes prevented by gate
Quality (derived)	Defective units per month	$N_{def}=N\cdot p_0$	60	60	units/month
Testing	EOL test time per unit	$t_{test,0}$ $t_{test,1}$	1	0.33	min/unit
Rework	Rework time per defective unit	$t_{rw}$	5	5	min/defective unit (repairable)
Policy	Retest after rework	—	Yes	Yes	Mandatory retest until PASS
QC workload (derived)	Total monthly QC time (test + rework + retest)	$T_0, T_1$	1860	814.8	min/month
QC workload (derived)	Total monthly QC time	$T_0/60, { T}_1/60$	31	13.58	h/month
Productivity (derived)	Global QC productivity	Pglobal = N/(T/60)	48.39	110.46	units/h (over test + rework + retest)
Improvement (derived)	Time released	ΔT = T0 − T1	—	1045.2	min/month (17.42 h/month)
Customer quality	Customer defects (escapes)	—	Possible	Target: 0	Achieved through “no PASS—no shipment” gate

* The internal nonconformity rate $p_0$ represents defect occurrence prior to the EOL gate; after implementation, the gate enforces “no PASS—no shipment”, aiming at zero customer escapes (zero shipped defects), even if repairable internal defects still occur and are corrected via rework and mandatory retest. This interpretation is consistent with quality-gate/virtual-quality-gate concepts for preventing defect propagation downstream [14,15]. Computation: $T_0=N\cdot t_{test,0}+N_{def}\cdot t_{rw}+N_{def}\cdot t_{test,0}$ and $T_1=N\cdot t_{test,1}+N_{def}\cdot t_{rw}+N_{def}\cdot t_{test,1}$ The use of dedicated electrical fixtures for harness continuity and incorrect pinning/miswiring detection is aligned with reported harness test automation approaches [13,22]. Data-centric note: structured logging of PASS/FAIL and pin-level diagnoses support data-driven quality management and digital-thread-aligned traceability for continuous improvement [7,20,21].

summarizes the input parameters and derived monthly indicators used to quantify the before–after impact of replacing visual EOL inspection with a deterministic electrical test fixture. In repetitive manual assembly, perceptual checking of high-similarity components is susceptible to human error and inter-operator variability; therefore, converting inspection into an objective functional gate is a recognized mitigation strategy.

The quality-gate and virtual-quality-gate literature highlights that robust end-of-line gates can achieve zero customer escapes by blocking shipment until conformance, even when internal defects remain repairable. The selected time parameters (test, rework, and mandatory retest) are consistent with prior work on automated cable-harness testing systems that detect opens, shorts, and incorrect pinning/miswires while reducing test time through dedicated fixtures/testers. Finally, the table supports a data-centric perspective: structured EOL logging enables traceability and continuous improvement aligned with digital-thread concepts and data-driven quality management.

4.3. Productivity Improvement

The productivity improvement is reported as the percentage difference between the baseline (visual inspection + rework) and the fixture-based scenario. Both station throughput (units/hour) and overall quality-related productivity (test + rework + retest) are reported to avoid conclusions based on a single indicator (Figure 5a).

For time related indicators (test duration, rework duration, and reinspection/retest duration), variability (e.g., standard deviation) is recommended on a representative sample, because operational performance depends on the operator, fixture placement and type.

4.3.1. Test-Station Throughput

$$P_{test}={\displaystyle \frac{60}{t_{test}}}$$

(12)

$$\mathrm{Before}: P_{test,0}={\displaystyle \frac{60}{1}}=60 \mathrm{units}/\mathrm{h}$$

(13)

$$\mathrm{After}: P_{test,1}={\displaystyle \frac{60}{0.33}}\approx 181.8 \mathrm{units}/\mathrm{h}$$

(14)

4.3.2. Global Quality Productivity (Test + Rework + Retest)

$$P_{global}={\displaystyle \frac{N}{T/60}}$$

(15)

$$\mathrm{Before}: P_{global,0}={\displaystyle \frac{1500}{31}}=48.39 \mathrm{units}/\mathrm{h}$$

(16)

$$\mathrm{After}: P_{global,1}={\displaystyle \frac{1500}{13.58}}=110.46 \mathrm{units}/\mathrm{h}$$

(17)

Relative gain:

$${\displaystyle \frac{P_{global,1}}{P_{global,0}}}\approx 2.28\Rightarrow +128\%$$

(18)

The direction and magnitude of improvement are consistent with published findings that document how harness test automation reduces test time and increases detection reliability [13,22].

To support validation of the proposed solution under production conditions, we built a monthly evaluation scenario over a 6-month period (March–August 2025), where production volume varies with the number of working days (

Table 2. Monthly summary: production, rejections, and savings.

Month	Target Units	Rejects V1 (4.0%)	Rejects V2 (1.2%)	Savings (RON)
March 2025	1454	58	17	9020
April 2025	1523	61	18	9460
May 2025	1523	61	18	9460
June 2025	1454	58	17	9020
July 2025	1592	64	19	9900
August 2025	1454	58	17	9020

). In Scenario B, the daily production rate is considered constant; therefore, monthly production increases/decreases with working days. Rejection volumes were computed as a share of monthly production (V1 = 4%, V2 = 1.2%), and the difference between areas highlights the gain in good units after implementation.

Across the analyzed interval, the estimated total production is 9000 units. The reduction in rejects from 4% to 1.2% corresponds to a cumulative decrease of 254 rejected units and, consequently, to an increase in good units available for downstream operations (Figure 5b).

Economic efficiency can be approximated as “avoided cost” associated with reducing rejects. For each month m, the savings are computed as: E_m = (R_{1, m} − R_{2, m}) * P, where R_{1, m} and R_{2, m} are the numbers of rejected units for v₁ and v₂ in month m, and P is the unit price (P = 220 RON/unit). This simple model provides a transparent, first-order estimate of the financial impact driven by reduced internal failure (Figure 6).

The estimated total savings over 6 months are 55,880 RON (P = 220 RON/unit).

In productivity terms, reducing rejects (and implicitly retesting and associated rework activities) contributes to increasing the volume of good units and to stabilizing the inspection workload. This aligns with the Cost of Quality/Cost of Poor-Quality perspective, where internal failure costs (scrap/rework) can be reduced through prevention and appraisal mechanisms such as mistake-proofing and quality gates [26,27].

5. Discussion: Human Factors and Data Value

A key limitation is scalability: as the number of pins increases, scan complexity and the number of potential ambiguous cases also increase, especially in the presence of multiple defects. For high-pin-count harnesses, optimizing scan order and constraining the assumed defect set become essential.

The economic benefit comes from reducing inspection time and rework time and from preventing the costs associated with shipped defects (complaints, returns, and line stops). Costs include fixture design and manufacturing, electronic integration, and maintenance (e.g., contact replacement and calibration). In production, payback is driven primarily by volume and time saved per unit; the higher the baseline visual inspection time and the higher p₀, the faster the investment is recovered.

An alternative approach is to prevent miswiring through design (mechanical keying, differentiated connectors, and coding). In practice, this may be constrained by cost, existing standards, compatibility with installed equipment, and retrofit needs. Therefore, the proposed quality gate is complementary: it reduces operational risk when product design cannot be changed rapidly.

The results can be complemented with a sensitivity analysis on key parameters (p₀, test time, rework time, and retest rate) to show the range of productivity gains. This analysis highlights which parameters dominate the outcome and under what conditions the solution remains advantageous.

The proposed EOL fixture substantially reduces reliance on perceptual discrimination in a high-similarity assembly context (all black conductors). In the baseline workflow, the operator’s final judgment depended on visual checking and cognitive verification of a wiring order that is not directly observable once conductors are routed and inserted. Such tasks are known to be susceptible to attention lapses, working memory overload, and confirmation bias, particularly under repetitive work, time pressure, or frequent changeovers. By converting the verification step from a subjective visual assessment into a deterministic functional check, the fixture decreases the probability that a miswire will remain undetected and reduces inter-operator variability. This is consistent with human reliability findings in complex manual assembly, where standardization and objective feedback mechanisms reduce error occurrence and improve inspection consistency [9].

From a human factors’ standpoint, the fixture also enables immediate, actionable feedback. Instead of a generic “fail” condition, the system can indicate the fault class (open/short/miswire) and, for miswiring, provide pin-level localization. This changes the operator’s task from searching for an error in an ambiguous condition to performing a guided correction with lower cognitive burden. Over time, this can support learning effects and more stable performance across shifts because the operator receives consistent feedback and the process becomes less dependent on tacit experience. In practice, such feedback loops are a key mechanism for reducing the probability of repeated errors in manual assembly settings [9].

From a data perspective, architecture’s value is not limited to gatekeeping. The structured logging of PASS/FAIL outcomes together with fault classes, affected pin indices, timestamps, and rework cycles creates a minimal but high leverage dataset for continuous improvement. In a digital-thread-oriented perspective, these records can be linked to batch/lot information, work orders, material traceability (connectors and terminals), and station/operator identifiers, thereby creating an auditable chain of evidence for each shipped unit and supporting root-cause analysis when anomalies arise. Such linkage is aligned with digital-thread concepts emphasizing lifecycle continuity of product and process information [7,20]. Furthermore, the systematic collection of inspection and rework data enables a data-driven quality-management approach by supporting KPI tracking (e.g., first-pass yield, rework rate, and retest cycles), defect Pareto analyses (e.g., recurring swapped pin pairs), and targeted interventions (training, work-instruction changes, and fixture maintenance strategies). These practices are consistent with data-centric quality-management approaches in multi-stage manufacturing [21].

In addition, the logged dataset provides a practical foundation for more advanced analytics if pursued in future work. For example, time-series monitoring can identify drift in failure patterns (e.g., increasing open-circuit occurrences linked to tooling wear in crimping). More sophisticated approaches could combine EOL test results with upstream process signals (crimp parameters, operator sequence, or changeover events) to predict risk and recommend preventive actions. Recent research on AI-assisted fault detection in wiring harness manufacturing suggests that machine learning can be used to improve fault identification and decision support, provided that sufficiently structured data are available. In this context, the proposed logging strategy becomes a prerequisite for scaling toward AI-supported quality control, while maintaining deterministic EOL acceptance criteria for shipment decisions [14].

6. Conclusions and Future Work

6.1. Conclusions

The results indicate that a deterministic quality gate, combined with pin-to-pin diagnosis and data-centric traceability, can substantially reduce inspection effort and increase overall productivity in manual harness assembly. The main value is transforming a predominantly visual inspection into a verifiable, repeatable, and analyzable process, where the defect is not only detected but also localized and corrected in a guided manner.

Limitations: the solution depends on the availability of a dedicated fixture for each connector type/variant, and performance may be affected by fixture wear, contact stability, and the prevalence of multiple-defect cases.

This study proposed and validated a data-centric end-of-line (EOL) architecture for smart cable harness assembly that combines 100% electrical continuity testing, deterministic pin-to-pin mapping verification, and explicit miswiring diagnosis for a 16-circuit industrial quick-connect harness with visually indistinguishable conductors. The core contribution is the translation of an error prone, perception-based final check into a deterministic functional quality gate that enforces the operational rule “no PASS—no shipment.” In line with quality-gate and virtual-quality-gate concepts, the EOL gate prevents downstream propagation and supports the target of zero customer escapes, even when internal repairable defects still occur [16,17].

From a quality engineering standpoint, the proposed method directly addresses the dominant failure mode, two-wire swaps (miswires), which is difficult to detect visually when all conductors share the same color and geometry. By computing and validating the connectivity topology rather than relying on visual confirmation, the fixture provides a repeatable and auditable PASS/FAIL decision. This approach is consistent with the harness test automation literature reporting successful detection of incorrect pinning and electrical faults through dedicated test systems [13,22].

Operationally, the study quantified the impact using a before–after workload model with mandatory retest after rework. With $N=1500$ units/month, $p_0=4\%$, $t_{test,0}=1$ min/unit, $t_{rw}=5$ min/defect, and $t_{test,1}=0.33$ min/unit, total quality workload (test + rework + retest) decreased from 31 h/month to 13.58 h/month, releasing 17.42 h/month. This corresponds to a 56% reduction in monthly quality workload. In parallel, global quality productivity increased from 48.39 units/h to 110.46 units/h (+128%). These results substantiate that a deterministic EOL verification strategy can simultaneously strengthen outgoing quality and improve capacity utilization, consistent with the broader rationale of quality-gate placement in multi-stage manufacturing systems [16,17].

Beyond verification, a key outcome is the data-centric nature of the proposed solution. By logging test outcomes (PASS/FAIL), fault class (open/short/miswire), and pin-level localization, the architecture creates a minimal but high-value dataset for process learning. This enables evidence-based actions such as Pareto analysis of recurring swap pairs, station-level comparison, and monitoring of rework loops. Such logging is consistent with data-driven quality-management perspectives and supports traceability aligned with digital-thread concepts [7,20,21].

Finally, the study clarifies the meaning of “zero defects” as zero shipped defects (zero escapes) achieved through the EOL gate logic rather than the elimination of internal defect occurrence. This distinction is critical for correct interpretation and aligns with the role of quality gates in preventing defect propagation [16,17].

6.2. Future Work

Future work can extend both the technical scope and the manufacturing-system integration of the proposed architecture:

• MES/ERP integration and stronger digital-thread linkage. Implement automated association between test records and work orders, material lots (connectors, terminals, cable batches), station IDs, and operator IDs. This would transform the current local log into an enterprise traceability asset and strengthen lifecycle continuity in line with digital-thread definitions and frameworks [7,22];
• Statistical-process monitoring and structured continuous improvement. Use the logged dataset for systematic monitoring of first-pass yield, rework cycles, defect Pareto (swap pairs), and time-based trends. This enables targeted interventions (training, work-instruction refinement, fixture maintenance, and upstream process controls) and aligns data-driven quality-management approaches for multi-stage manufacturing [21];
• Optional electrical metrics beyond continuity (process indicators). While acceptance is continuity/topology-based in this study, future variants could record contact/loop resistance values for condition monitoring (e.g., early indication of crimp degradation or connector wear). If resistance thresholds become a customer requirement, standardized methods such as IEC 60512-2-1 and MIL-STD-202 Method 307 provide guidance for contact resistance measurement [23,25];
• Scalability to higher pin counts and multiple harness variants. Develop modular hardware/software addressing strategies, barcode/QR-driven variant recognition, and configurable mapping tables to support multi-product lines. This direction follows recommendations in the harness testing automation literature emphasizing adaptability and modularization [13,22];
• AI-assisted analytics for defect prevention (beyond EOL detection). Use historical EOL data to predict risk patterns (e.g., specific swap pairs correlating with shifts, changeovers, or upstream tooling states) and to recommend preventive actions. Recent research suggests that AI-based fault detection is feasible in harness manufacturing when structured datasets are available, making the proposed logging strategy a practical foundation for advanced analytics [14];
• Human factors and workstation design improvements. Complement EOL detection with upstream error-prevention measures (operator guidance, improved work instructions, kitting strategies, or pick-to-light support), aiming to reduce internal defect occurrence while maintaining zero escapes through the EOL gate. The rationale is consistent with mistake-proofing principles that emphasize prevention and rapid detection [10,18,19].