Reduct for Large Datasets: Parallel Multi-Processor Architecture in FPGA

This work introduces a parallel architecture that leverages both a Field-Programmable Gate Array (FPGA) and a softcore CPU to accelerate reduct computation for large-scale datasets using rough set theory. The proposed designs were evaluated on two real-world datasets executed directly on the FPGA platform, with dataset sizes ranging from 1000 up to 1,000,000 objects. An equivalent software implementation was used as a reference. Experimental results demonstrate that the hardware-supported reduct generation achieves substantial reductions in computation time compared to the software solution, giving speed-up factors from 5 up to 16 times for the same number of cores both in hardware and software, up to 52 times when comparing hardware four-core approach with single software core solution.