All-Integer Quantization for Low-Complexity Min-Sum Successive Cancellation Polar Decoder

Abstract

It is widely acknowledged in communication theory that polar codes have been proven to achieve channel capacity across a range of communication channels. However, their exceptional performance is usually evaluated through simulations or analyses conducted under the assumption of infinite precision, i.e., floating-point arithmetic, which represents an ideal numerical computation. To address this implementation challenge, this work proposes a min-sum successive cancellation (MS-SC) polar decoder employing all-integer quantization to improve practicality in real-world scenarios. To balance the trade-off between practicality and decoding performance, we investigate whether 5-bit all-integer quantization is the optimal choice for the MS-SC polar decoder. Moreover, the simulation results over fading channels show that the proposed decoder achieves a performance almost equivalent to the high-precision successive cancellation (SC) decoder. The integer-based calculation for the MS-SC polar decoder reduces computational complexity by $75\%$ compared to the conventional SC decoding algorithm with infinite-precision computation.

1. Introduction

Polar codes, exploiting channel polarization, were proven by Arikan [1] to achieve channel capacity on symmetric binary-input discrete memoryless channels (B-DMCs) when code length $\mathit{N}$ becomes large. For finite block lengths, SC decoding was first introduced for polar codes. To simplify the hardware implementation, an approximation method for SC decoding was explored in [2]. Applying the min-sum approximation (MSA) forms the MS-SC decoder, which has slightly lower performance than that of the original SC decoder. To significantly improve the decoding performance, decoding algorithms such as Successive Cancellation List (SCL) decoding and Cyclic Redundancy Check (CRC)-aided SCL decoding were proposed in [3]. Moreover, the computational complexity of SCL decoding grows linearly with the list size. Due to their superior error correction capabilities, polar codes have been selected for use in 5G enhanced mobile broadband (eMBB) scenarios, particularly in the control channel [4]. Additionally, applications such as speech communication [5], decoders based on field-programmable gate arrays (FPGAs) [6], and exploration for future 6G communication [7] highlight the diverse potential of polar codes.

In theory, decoding algorithms rely on infinite-precision calculations, but practical implementations, such as those discussed in [8], do not require such high precision. An approximation technique, known as quantization, is important for practical channel coding schemes, including polar, turbo, and low-density parity-check (LDPC) codes, as it significantly reduces computational complexity and hardware resource usage. However, reduced precision can degrade the error correction performance. Therefore, quantization is a key challenge in improving polar decoding while balancing complexity and performance.

Reducing the number of quantization levels is an alternative approach to achieve a balance between computational complexity and decoding performance in SC decoding. A nonuniform quantized SC decoding method was proposed in [9] to reduce complexity without a significant degradation in the error-correction performance, demonstrating only a $0.1$–$0.2$ dB performance loss at a frame error rate (FER) of ${10}^{-3}$ when using 2-, 3-, and 4-bit precision levels compared to floating-point SC decoding. The minimum distortion quantizers proposed in [10] achieved an FER close to floating-point decoding with 5-bit nonuniform quantization. However, this method still results in a 0.1 dB loss at an FER of ${10}^{-4}$. An alternative approach, as proposed in [11], combines a 1-bit quantizer with an improved polar belief propagation (BP) decoder, which applies deep learning techniques to enhance the decoding process through a neural network decoder. This approach achieves a performance gain of 2 dB compared to the 1-bit quantized BP decoder.

To further minimize the computational effort, the Information Bottleneck method was applied to LDPC decoding, where quantizers mapped log-likelihood ratios (LLRs) to unsigned integers, leading to decoders that outperformed traditional min-sum decoders in terms of error performance and computational efficiency [12]. Similarly, in [13], lookup tables were utilized in a discrete SCL decoding algorithm, achieving a performance comparable to a floating-point SCL decoder with a list size of 32, proving the feasibility of integer-based decoding for practical applications. Additionally, ref. [14] applied a 4-bit all-integer quantization to an MSA-based LDPC decoder. Their proposed method achieved performance close to that of its floating-point counterpart, highlighting the potential of integer quantization in modern channel coding techniques.

High-precision floating-point calculation is often computationally intensive and less suitable for hardware-constrained environments such as resource-constrained Internet of Things (IoT) devices [15], wireless sensor networks [16], and NAND flash memory [17]. Motivated by the need to overcome these challenges, the SC and MS-SC decoding algorithms are of interest in this work due to their low computational complexity in polar codes. This work focuses on integer-based quantized SC decoding algorithms. This paper addresses the practical challenges of SC decoder implementation and makes the following key contributions:

• Proposal of an All-Integer-Quantized MS-SC Decoder: We introduce an integer-based quantized min-sum SC (QMS-SC) decoder that eliminates floating-point computations, making it more suitable for hardware implementations.
• Performance–Complexity Trade-off Analysis: We investigate the impact of integer-based quantization and demonstrate that 5-bit integer quantization approaches a performance comparable with high-precision MS-SC decoding. We also analyze the decoding performance over fading channels, showing that quantization beyond 5 bits leads to performance saturation.
• Computational Complexity Reduction: The all-integer QMS-SC decoder reduces computational complexity by approximately 75% compared to the conventional SC decoder, significantly improving efficiency.

The remainder of this paper is organized as follows: Section 2 presents the background and the system model. Section 3 discusses the related work. Section 4 discusses the role of integer quantization. The experimental results and the comparison in computational complexity are provided in Section 5. We discuss the implementation results of polar coding in Section 6. Finally, Section 7 provides the conclusions.

2. Background and System Model

2.1. Polar Codes

Polar codes, a class of linear block codes, are purposefully designed for memoryless channels. To generate polar codes, let ${\mathit{u}}_1^{\mathit{N}}$ be the encoding input vector $({\mathit{u}}_1,{\mathit{u}}_2,\dots ,{\mathit{u}}_N)$ comprising both the information set and frozen set. The information bits are placed according to the index set $\mathcal{A}$, while the frozen bits (set to zero) are allocated based on the index set ${\mathcal{A}}^c$. In addition, the index set $\mathcal{A}$ comprises $\mathit{K}$ bits, while the other set ${\mathcal{A}}^{\mathit{c}}$ consists of $\mathit{N}-\mathit{K}$ bits. An input vector is first formed by identifying the reliable indices of set $\mathcal{A}$. For the sake of simplicity, a polar code construction method known as the Gaussian Approximation (GA) algorithm [18] is employed to determine the reliable set $\mathcal{A}$. Additionally, the design signal-to-noise ratio (SNR) [19], corresponding to a given value of ${\mathit{RE}}_{\mathit{b}}/{\mathit{N}}_0$, serves as a crucial parameter for initializing polar code construction. The codewords ${\mathit{c}}_1^{\mathit{N}}$ can be obtained by

$${\mathit{c}}_1^{\mathit{N}}={\mathit{u}}_1^{\mathit{N}}{\mathbf{G}}_{\mathit{N}},$$

(1)

where ${\mathbf{G}}_N$ is the generator matrix and the code length is denoted by $\mathit{N}=2^{\mathit{n}}$. To obtain the generator matrix, ${\mathbf{G}}_{\mathit{N}}={\mathbf{B}}_{\mathit{N}}{\mathbf{F}}^{\otimes \mathit{n}}$. ${\mathbf{B}}_{\mathit{N}}$ denotes the bit-reversal permutation matrix. Additionally, a bit-reversal permutation matrix rearranges the elements of a vector in a specific way based on the bit-reversal operation. The Kronecker power of ${\mathbf{F}}^{\otimes \mathit{n}}$ is recursively defined as $\mathbf{F}\otimes {\mathbf{F}}^{\otimes \mathit{n}-1}$ and the kernel matrix is $\mathbf{F}=\left[\begin{array}{cc}1& 0\\ 1& 1\end{array}\right]$. Fortunately, the encoding process of polar codes can be implemented with the complexity $O(\mathit{N}log\mathit{N})$. For instance, a polar encoder for $\mathit{N}=8$ bits and the frozen set ${\mathcal{A}}^{\mathit{c}}=\{1,2,3,5\}$ are illustrated in Figure 1. The encoding input is first rearranged using the bit-reversal operation before performing calculations.

2.2. Successive Cancellation Decoding Algorithm

The underlying concept of the decoding algorithm, known as successive cancellation, focuses on enhancing the reliability of subsequent bits to retrieve the message from corrupted codewords. In order to estimate the decoded vector ${\widehat{\mathit{u}}}_1^{\mathit{N}}$, it is essential to calculate the random variables from the channel outputs as LLRs before commencing the decoding process. According to the SC decoder, the process consists of $\mathit{n}+1$ stages and $\mathit{N}$ levels. To consider each unit of the decoder, let $\mathit{i}\in \{1,2,\dots ,\mathit{N}\}$ and $\mathit{j}\in \{1,2,\dots ,\mathit{n}+1\}$. Within the SC decoding algorithm calculations, the LLR can be denoted as ${\mathit{L}}_{\mathit{i},\mathit{j}}$. Let vector ${\mathit{y}}_1^{\mathit{N}}$ be the channel output. The initial LLR is denoted by ${\mathit{L}}_{\mathit{i},\mathit{n}+1}=ln({\displaystyle \frac{\mathit{P}\left(\mathit{y}\right|{\mathit{u}}_{\mathit{i}}=0)}{\mathit{P}\left(\mathit{y}\right|{\mathit{u}}_{\mathit{i}}=1)}})$, where ln represents the natural logarithm. Prior to implementing the SC decoding algorithm, the initial LLR ${\mathit{L}}_{\mathit{i},\mathit{n}+1}$ needs to undergo rearrangement through bit-reversal permutation. The transition probabilities within the conventional SC decoding algorithm can be calculated using the following equations:

$${\mathit{L}}_{\mathit{i},\mathit{j}}=\left\{\begin{array}{cc}\mathit{f}({\mathit{L}}_{\mathit{i},\mathit{j}+1},{\mathit{L}}_{\mathit{i}+2^{\mathit{j}-1},\mathit{j}+1}),\hfill & \lfloor {\displaystyle \frac{\mathit{i}-1}{2^{\mathit{j}-1}}}\rfloor \mathrm{mod}2=0,\hfill \\ \mathit{g}({\widehat{\mathit{u}}}_{\mathit{i}-2^{\mathit{j}-1},\mathit{j}},{\mathit{L}}_{\mathit{i}-2^{\mathit{j}-1},\mathit{j}+1},{\mathit{L}}_{\mathit{i},\mathit{j}+1}),\hfill & \mathrm{otherwise},\hfill \end{array}\right.$$

(2)

$$\mathit{f}({\mathit{L}}_{\mathit{a}},{\mathit{L}}_{\mathit{b}})=2{tanh}^{-1}\left(tanh\left({\displaystyle \frac{{\mathit{L}}_{\mathit{a}}}{2}}\right)tanh\left({\displaystyle \frac{{\mathit{L}}_{\mathit{b}}}{2}}\right)\right),$$

(3)

$$\mathit{g}({\widehat{\mathit{u}}}_{\mathit{s}},{\mathit{L}}_{\mathit{c}},{\mathit{L}}_{\mathit{a}})=(1-2{\widehat{\mathit{u}}}_{\mathit{s}})·\left({\mathit{L}}_{\mathit{c}}\right)+{\mathit{L}}_{\mathit{a}},$$

(4)

$${\widehat{\mathit{u}}}_{\mathit{i},\mathit{j}+1}=\left\{\begin{array}{cc}{\widehat{\mathit{u}}}_{\mathit{i},\mathit{j}}\oplus {\widehat{\mathit{u}}}_{\mathit{i}+2^{\mathit{j}-1},\mathit{j}},\hfill & \lfloor {\displaystyle \frac{\mathit{i}-1}{2^{\mathit{j}-1}}}\rfloor \mathrm{mod}2=0,\hfill \\ {\widehat{\mathit{u}}}_{\mathit{i},\mathit{j}},\hfill & \mathrm{otherwise},\hfill \end{array}\right.$$

(5)

where stage $\mathit{j}$ and level $\mathit{i}$ are represented by individual identifiers: $\mathit{a}$, $\mathit{b}$, $\mathit{c}$, and $\mathit{s}$. The identifier $\mathit{a}$ is defined as $(\mathit{i},\mathit{j}+1)$, $\mathit{b}$ as $(\mathit{i}+2^{\mathit{j}-1},\mathit{j}+1)$, $\mathit{c}$ as $(\mathit{i}-2^{\mathit{j}-1},\mathit{j}+1)$, and $\mathit{s}$ as $(\mathit{i}-2^{\mathit{j}-1},\mathit{j})$. The SC decoding algorithm is executed as a recursive process. Subsequently, the preceding bit is employed to update the transition probability in (4). To determine the updated bit corresponding to the prior decoded bit, refer to (5). The estimated bits $\{{\widehat{\mathit{u}}}_1,{\widehat{\mathit{u}}}_2,\dots ,{\widehat{\mathit{u}}}_{\mathit{N}}\}$ are sequentially determined using the following equation:

$${\widehat{\mathit{u}}}_{\mathit{i}}=\left\{\begin{array}{cc}0,\hfill & \mathrm{if}{\mathit{L}}_{\mathit{i},1}⩾0\mathrm{and}\mathit{i}\in \mathcal{A},\hfill \\ 1,\hfill & \mathrm{if}{\mathit{L}}_{\mathit{i},1}<0\mathrm{and}\mathit{i}\in \mathcal{A},\hfill \\ {\mathit{u}}_{\mathit{i}}=0,\hfill & \mathit{i}\in {\mathcal{A}}^c.\hfill \end{array}\right.$$

(6)

For finalizing the SC decoding process, the recovered information can be derived from $\{{\widehat{\mathit{u}}}_1,{\widehat{\mathit{u}}}_2,\dots ,{\widehat{\mathit{u}}}_i,\dots ,{\widehat{\mathit{u}}}_{\mathit{N}}\}$, where $\mathit{i}\in \mathcal{A}$. In the context of hardware implementation, the $\mathit{g}$ function in (4) primarily features an adder–subtracter influenced by the updated bit ${\widehat{\mathit{u}}}_{\mathit{s}}$. Conversely, the hardware complexity arises with the $\mathit{f}$ function in (3). Despite this, approximating the $\mathit{f}$ function can be achieved using a minimization function resembling techniques found in LDPC codes [20]. The $\mathit{f}$ function can be approximated as

$$\mathit{f}({\mathit{L}}_{\mathit{a}},{\mathit{L}}_{\mathit{b}})\approx \mathrm{sign}\left({\mathit{L}}_{\mathit{a}}\right)\mathrm{sign}\left({\mathit{L}}_{\mathit{b}}\right)\min \left(\right|{\mathit{L}}_{\mathit{a}}|,|{\mathit{L}}_{\mathit{b}}\left|\right).$$

(7)

In comparison to conventional SC decoding, the performance of the min-sum algorithm for SC decoding, as discussed in [2], exhibits slight performance degradation for moderate code lengths and a larger gap for longer codes.

2.3. System Model

A simple polar-coded communication system is illustrated in the block diagram in Figure 2. First, binary information of length $\mathit{K}$ is generated following a uniform distribution. This binary information is then encoded into a binary polar code of length $\mathit{N}$ using a polar encoder, as defined in (1). After encoding, each bit of the codeword is mapped to a modulated symbol using binary phase shift keying (BPSK), given by ${\mathit{s}}_{\mathit{i}}=1-2\left({\mathit{c}}_{\mathit{i}}\right)$, where $\mathit{i}\in \{1,2,\dots ,\mathit{N}\}$. The transmitted BPSK symbols are corrupted by additive white Gaussian noise (AWGN).

To obtain LLRs, the received symbols are processed using the probability density function (PDF) of a normal distribution, considering BPSK modulation. The polar decoder then computes $\mathit{N}$ LLRs using Equation (2) and retrieves $\mathit{K}$-bit information using (6). Performance evaluation is conducted by measuring the bit error rate (BER), which is determined as the ratio of bit differences between the transmitted and received information to the total number of transmitted bits. Additionally, FER is calculated as the proportion of received $\mathit{K}$-bit blocks that contain at least one erroneous bit to the total number of transmitted frames.

3. Related Work

Polar codes have gained significant attention in modern communication systems due to their capacity-achieving properties, as well as their low-complexity construction and decoding. Considering future wireless communication systems, [7] highlighted the potential of polar codes as a candidate for 6G wireless networks, which demand ultra-low latency (100 $\mathsf{\mu }$s) and extremely high reliability (FER below ${10}^{-6}$ to ${10}^{-7}$). In [15], polar codes were investigated as a replacement for Long-Term Evolution (LTE) turbo codes in narrowband Internet of Things (NB-IoT). With their proposed BP decoding for polar codes, the performance gap was reduced by 1.2 dB when compared to turbo codes. Additionally, the complexity of polar codes was shown to be lower than that of turbo codes. Recent studies [17] have explored the significant increase in NAND flash memory, which has led to data becoming more prone to errors, as well as an increased uncertainty in the channel. To address these issues, they proposed a polar code construction, which reduces the uncorrectable bit error rate by up to 90.5%. As polar codes continue to be explored in applications such as 6G, IoT, and NAND flash memory, optimizing their implementation becomes crucial. One key approach to achieving efficient decoding while maintaining performance is through quantization techniques, which balance computational complexity and error correction capability.

In [2], the performance of quantized SC decoding was compared to that of a floating-point algorithm using fixed-point operations with five and six quantization bits. The study also demonstrated that higher quantization levels and longer code lengths lead to increased area usage in hardware implementations. A nonuniform-quantized SC decoder was proposed in [9] to reduce the bit precision level of quantization, as low-bit precision is beneficial for applications requiring low-energy transceivers. To observe the performance of a semi-parallel architecture for SC decoding, proposed by [21], the performance of SC decoding with quantization, where the input is limited to the range $[-2,2]$ before the quantization process, almost matches that of the non-quantized decoder with 5 bit precision. To design a fast low-complexity SC decoder, ref. [22] employed 6-bit quantization to represent internal LLRs while maintaining an error correction performance close to that of the floating-point representation. To implement a multi-kernel decoder based on the fast-simplified SC algorithm, ref. [23] employed a quantization scheme $\mathit{Q}({\mathit{Q}}_{\mathit{i}},{\mathit{Q}}_{\mathit{c}},{\mathit{Q}}_{\mathit{f}})$, where ${\mathit{Q}}_{\mathit{i}}$, ${\mathit{Q}}_{\mathit{c}}$, and ${\mathit{Q}}_{\mathit{f}}$ represent the number of LLR quantization bits for internal, channel, and fractional bit sizes, respectively. With 5-bit quantization, the performance of their proposed SC decoder is very close to that of the floating-point scheme. Two novel processing element (PE) units for SC decoders were proposed in [24], where a 6-bit quantization scheme was chosen to balance the trade-off between BER performance and complexity. In [25], their method optimized hardware resource utilization by reducing memory usage. The implementation on a Virtex UltraScale-XCVU190 FPGA demonstrated a throughput of 2672 Mbps, with a $17\%$ reduction in lookup table (LUT) usage and a $17.34\%$ speed improvement for a code length of 128. The study also explored different quantization schemes, analyzing the trade-offs between integer and fractional bit precision in SC decoding. To reduce latency and energy consumption, a novel Fast-SSC decoder, proposed in [26], was designed using fixed-point operations with 5-bit uniform quantization to optimize memory usage in hardware.

While these studies have explored and utilized various quantization strategies for SC decoding, most focus on achieving hardware efficiency while maintaining a performance close to floating-point implementations. However, there is limited investigation into the trade-offs between quantization precision and decoding performance. Additionally, the impact of integer-only quantization with restricted bit precision has not been extensively analyzed. In this work, we extend prior research by evaluating the performance of an all-integer-quantized min-sum SC decoder with varying bit precision levels. Our study provides insights into the effectiveness of integer-based quantization in maintaining decoding accuracy while reducing computational complexity.

4. All-Integer Quantization for Successive Cancellation Decoding Algorithm

Quantization is an essential process in decoding algorithms, significantly impacting both performance and computational complexity. Generally, quantization techniques can be classified into uniform and nonuniform (nonlinear) quantization. Uniform quantization maintains a fixed step size across the entire dynamic range, making it computationally efficient and straightforward to implement. In contrast, nonuniform quantization employs variable step sizes, allocating finer resolution to small-magnitude values and coarser steps to larger values. The SC decoding performance comparison between uniform and nonuniform quantization is presented in [9]. While nonuniform quantization can improve precision for specific distributions, it introduces additional computational overhead. Uniform quantization is chosen in this work due to its low computational complexity and ability to maintain simplicity in the decoding process. This approach ensures the fast execution and low complexity of the SC decoding algorithm, which is crucial for efficient real-time decoding in practical systems. In general, a quantization function is characterized by a quantization step and quantization level denoted by $\mathit{q}$ bits. Throughout the experiments, the quantization step is consistently set to 1 to preserve symmetry around zero, and this choice is maintained throughout the analysis without further discussion. To signify integer uniform quantization, the function $\mathit{Q}(\mathit{x},\mathit{q})$ can be defined as

$$\mathit{Q}(\mathit{x},\mathit{q})=\left\{\begin{array}{cc}\lfloor \mathit{x}+0.5\rfloor \hfill & ,-\mathit{T}\left(\mathit{q}\right)+1<\mathit{x}<\mathit{T}\left(\mathit{q}\right)-1,\hfill \\ \mathrm{sign}\left(\mathit{x}\right)\left(\mathit{T}\right(\mathit{q})-1)\hfill & ,\mathrm{otherwise},\hfill \end{array}\right.$$

(8)

where $\mathit{x}$ is the input to the function and can be either a real or an integer value. The quantization boundary $\mathit{T}\left(\mathit{q}\right)$ is defined as $2^{\mathit{q}-1}$, where $\mathit{q}\in \{2,3,4,...\}$, and $\mathit{q}$ refers to the number of bits used to determine the quantization levels. For example, 3-bit quantization assigns values to eight specific levels. However, in 3-bit quantization, this approach utilizes seven distinct levels as $\{-3,-2,-1,0,1,2,3\}$ to maintain symmetry and uniformity around zero.

In this work, a C-based implementation is employed to study all-integer quantization behavior. Integer rounding and clamping techniques are applied to simulate this process in the polar decoder. By replicating hardware-like integer quantization through simple arithmetic operations, this software-based approach efficiently evaluates the impact of quantization on the decoding performance before actual hardware deployment. The CPU (Central Processing Unit) serves as the computational platform for this implementation, allowing flexibility in testing different mathematical computations. To clearly illustrate the integration of the quantization function $\mathit{Q}(\mathit{x},\mathit{q})$ into the SC decoder, the SC decoding algorithm and its key sub-algorithm are shown in Algorithms 1 and 2.    

Algorithm 1: Successive Cancellation Decoding Algorithm

Algorithm 2: RecursivelyUpdateLLR($\mathit{i},\mathit{j}$)

During the recursive LLR update process, the function $\mathit{Q}(\mathit{x},\mathit{q})$ is applied to quantize values at multiple stages of Algorithm 2, including LLR inputs and the results of addition or subtraction operations. This ensures that the SC decoding algorithm consistently processes and operates on integer values, maintaining uniformity throughout the computation. Considering Equation (3), the quantization function (8) can be used to approximate nonlinear functions, i.e., $\mathit{Q}(tanh(x),\mathit{q})$ and $\mathit{Q}({tanh}^{-1}\left(\mathit{x}\right),\mathit{q})$. By incorporating this approach, the decoding process preserves numerical stability in hardware implementation. The next section presents experimental results, analyzing the performance and computational complexity of all-integer quantization SC decoding techniques compared to conventional floating-point MS-SC decoding.

5. Experimental Results

In this section, we investigate the BER and FER performance metrics to evaluate SC decoding algorithms through Monte Carlo simulations. For simplicity, the non-systematic SC decoding algorithm is only considered in this work. The polar codes are modulated using BPSK over AWGN channels. Fractional values are disregarded during quantization to enforce integer-domain calculations, except for the floating-point SC decoding algorithm, which accounts for infinite decimal precision in its computations. Additionally, fixed-point calculations represent values with a limited number of decimal places. The polar code construction follows the GA method and is optimized for a design-SNR of 2 dB for all experiments.

5.1. Decoding Performance Under Integer Quantization

This section examines the impact of integer calculations on QMS-SC decoding (7) and quantized SC (QSC) decoding (3) in relation to BER and FER performance, by varying the quantization level from 3-bit to 5-bit. The BER performance is presented because the non-systematic SC decoding algorithm is sensitive to error propagation, as shown in [27]. Consequently, the numerical results, which are quantized to integer values, within the SC decoding calculation may lead to error propagation. The results are presented in Figure 3 for polar codes with $\mathit{N}=256$ and $\mathit{R}=0.5$, and in Figure 4 for $\mathit{N}=4096$ and $\mathit{R}=0.83$. For short-length polar codes, the performance improves with increasing quantization levels in both BER and FER metrics. Notably, QMS-SC decoding outperforms QSC decoding, demonstrating performance gains of 0.84 dB, 1.68 dB, and 2.45 dB for 3-bit, 4-bit, and 5-bit quantization levels, respectively. For polar codes with a higher length of 4096 and a rate of 0.83, the min-sum SC decoding also outperforms the conventional SC decoding in the integer-based quantization domain.

To deeply evaluate integer-based decoding algorithms, it is necessary to compare the LLR outputs of QMS-SC and QSC decoding with those of floating-point SC decoding under identical conditions, including the same transmitted information and noise levels. Unfortunately, the original SC decoding output cannot be directly used as the exact value because (4) may occasionally produce excessively large outputs. In the sequential calculations of the SC decoding algorithm, such large values can serve as inputs to the transcendental Equation (3), potentially resulting in infinite outputs. Ensuring an accurate comparison, the output of (4) is clamped at $\pm 2^{\mathit{q}-1}-1$. To quantify the difference in LLRs, let $ϵ$ represent the difference between the approximate LLR outputs and the exact LLR outputs (infinite-precision values), as defined by

$$ϵ={\displaystyle \frac{1}{\mathit{K}}}\sum _{\mathit{i}\in \mathcal{A}}{\left({\widehat{\mathit{L}}}_{\mathit{i}}-{\mathit{L}}_{\mathit{i}}\right)}^2,$$

(9)

where quantized LLR, denoted as ${\widehat{\mathit{L}}}_i$, at the decoder output for the index set $\mathcal{A}$ are compared with the exact LLR, denoted by ${\mathit{L}}_{\mathit{i}}$. To illustrate the error in the LLR outputs of the decoding methods with full-integer quantization compared to infinite-precision values, we consider $E_{\mathrm{b}}/N_0$ that achieves a BER of ${10}^{-5}$ for block lengths of 256 bits and 4096 bits. The quantization level varies from 3-bit to 5-bit. The results are obtained by (9) and presented in

Table 1. Error measurement between integer LLR outputs relative to exact LLRs of SC decoding.

Decoding	Rate	Length	Average $\mathit{ϵ}$
			3-Bit	4-Bit	5-Bit
Quantized MS-SC	0.5	256	≈0.84	≈0.75	≈0.72
	0.83	4096	≈2.02	≈1.29	≈1.28
Quantized SC	0.5	256	≈1.26	≈3.77	≈15.7
	0.83	4096	≈2.06	≈1.54	≈3.53

.

Considering the performance metrics, the conventional SC decoding algorithm is highly sensitive to integer computation, resulting in a poor decoding performance for polar codes. Moreover, the significant discrepancy in LLRs highlights the inaccuracies in the decoding calculations, which result in an inferior performance. In contrast, the min-sum SC decoding algorithm is well suited to integer calculations. Additionally, a reasonable increase in the quantization level improves the performance of the quantized MS-SC decoding algorithm while reducing the error value $ϵ$.

5.2. Optimal Integer Quantization Level

To determine the optimal quantization level, we implement the integer-based min-sum algorithm in the SC decoder, considering quantization levels ranging from 3 to 6 bits. First, the performance of polar codes with a length of 256 bits and a rate of 0.5 is analyzed, as shown in Figure 5a. At an FER of ${10}^{-5}$, the integer-quantized MS-SC decoder with 4-bit quantization exhibits a 1.25 dB performance degradation compared to the floating-point MS-SC decoder. However, increasing the quantization level to 5 bits results in a significant improvement, showing a 2.5 dB enhancement over the 3-bit decoder. Notably, both the 5-bit and 6-bit integer-quantized decoders deliver a performance closely matching that of the high-precision floating-point MS-SC decoder, indicating that higher quantization levels effectively mitigate the loss in accuracy caused by integer approximation.

The performance analysis extends to larger code lengths, with Figure 5b illustrating the decoding performance of polar codes with a length of 1024 bits and a code rate of 0.67. As the code length increases, the performance improvement depends on the quantization level. For the polar codes with 1024 bits, the 5-bit integer-quantized MS-SC decoder closely matches the performance of the high-precision decoder. This trend continues with even larger code lengths, as shown in Figure 5c for polar codes with a length of 2048 bits and a rate of 0.5, and Figure 5d for polar codes with a length of 4096 bits and a rate of 0.83. In both cases, the integer-based MS-SC decoding algorithm with 5-bit quantization achieves an optimal balance, delivering performance nearly indistinguishable from the infinite-precision decoder. As the code length increases, the impact of quantization on performance becomes more apparent, and the results clearly demonstrate how different quantization levels influence the accuracy of the decoding process across these extended code lengths. Collectively, these results demonstrate that the 5-bit quantized MS-SC decoding algorithm provides a robust and efficient solution, delivering a performance close to that of the high-precision method.

5.3. Performance over Fading Channels

Fading in wireless communication results from multipath propagation, where transmitted signals suffer from varying delays and attenuations. In our simulation, a Rayleigh fading channel is modelled using uncorrelated distributions, where independent channel coefficients are assigned to each BPSK symbol and vary randomly across transmissions. We evaluate the decoding performance of a polar code of length $\mathit{N}=1024$ and $\mathit{K}=512$, comparing conventional min-sum SC decoding with all-integer quantization min-sum SC decoding at 5- to 8-bit levels. The results, shown in Figure 6, highlight the impact of quantization on the decoding performance under fading conditions.

For a BER of ${10}^{-5}$ and FER of ${10}^{-4}$, the performance of QMS-SC decoding is approximately 0.2 dB worse than that of high-precision MS-SC decoding, even when the quantization level is increased to 8 bits. However, this 0.2 dB gap is considered negligible in most communication systems. Furthermore, the performance of QMS-SC decoding saturates when the quantization level exceeds 5 bits, indicating that additional bit precision does not yield further performance gains.

5.4. Complexity Analysis

Intuitively, integer-based calculations are known to be faster and less complex than computations using high-precision floating-point arithmetic. To clearly illustrate this speed improvement, let ${\mathit{C}}_{\mathit{appx}}\left(\mathit{N}\right)$ represent the computational time of the approximated SC decoding algorithms, where $\mathit{N}$ denotes the code length. The reduction in relative computational complexity can be expressed as $({\mathit{C}}_{\mathit{sc}}\left(\mathit{N}\right)-{\mathit{C}}_{\mathit{appx}}\left(\mathit{N}\right))/{\mathit{C}}_{\mathit{sc}}\left(\mathit{N}\right)$. To measure the reduction in complexity, the simulation (written in C) is set up with normalized SNR values fixed to achieve a target FER of approximately ${10}^{-4}$. For comparison purposes, arithmetic operations and high-precision floating-point values provided by the C math header are not directly utilized. Considering IEEE 754 [28], we store the mantissa and exponent of the values separately before performing the integer-based calculations. To maintain precision in fixed-point calculations, all mantissa values are scaled to ${10}^7$. For simplicity, the hyperbolic functions and related operations are directly employed to calculate the floating-point values in conventional SC decoding, as these functions can be efficiently computed on the CPU, offering a good balance of speed and very high precision. The comparison of computational complexity is shown in

Table 2. Reduction gain in computational complexity relative to conventional SC decoding algorithm.

Decoding	Reduction Gain per Block Length (Bits)
	256	1024	4096	16,384
Integer-quantized MS-SC	$74.06\%$	$75.51\%$	$76.61\%$	$77.23\%$
Fixed-point MS-SC	$34.21\%$	$36.07\%$	$37.83\%$	$34.65\%$

. The fixed-point min-sum SC decoding algorithm reduces computational complexity by approximately $35\%$ relative to the original SC decoding algorithm. Furthermore, this reduction increases to $75\%$ with the all-integer-quantized min-sum SC decoding algorithm, clearly demonstrating that all-integer calculations can significantly reduce the computational complexity in polar code decoding.

The experiment highlighted that, in scenarios where the precision of floating-point calculations is not essential, the integer-based MS-SC decoding algorithm is a more efficient and practical choice, offering a better balance between performance and resource utilization. This comparison underscores the practical benefits of integer-based implementations in real-world communication systems.

6. Discussion

In our research, we designed and evaluated a low-complexity quantization technique using a CPU-based simulation because a CPU is more flexible in computation, particularly for handling high-precision floating-point arithmetic. However, unlike CPUs, FPGAs rely on fixed-point arithmetic and often require approximations to optimize performance due to hardware constraints. Our experiment is carefully designed to handle all-integer computation, ensuring compatibility with FPGA hardware while reducing the need for complex arithmetic operations.

Table 3. Comparison of arithmetic differences between CPU and FPGA.

Feature	CPU (Floating-Point)	FPGA (Fixed-Point/Integer)
Precision	High (32-bit/64-bit)	Limited (fixed-point)
Computation Type	Floating-point and integer	Mostly fixed-point or integer
Multiplication, Division	Fast and direct	Uses *DSPs or shift-add approximations
Nonlinear Functions (atanh, tanh, sqrt, exp)	Direct computation	Approximated using *LUTs, or Taylor series
Hardware Flexibility	No constraints on arithmetic complexity	Needs optimization for area, power, and latency

FPGA implementations often approximate arithmetic operations to optimize hardware efficiency. *DSPs are Digital Signal Processors (or Digital Signal Processing units, depending on context). *LUTs are lookup tables.

summarizes the key differences between CPU and FPGA arithmetic, highlighting the necessary adjustments for hardware implementation. Given these differences, our proposed quantization method is expected to be FPGA-efficient due to its reduced reliance on floating-point operations, optimized bit-width representation, and minimized computational complexity.

Our results highlight the significant impact of all-integer quantization on the performance of the SC decoding algorithm, confirming that MS-SC decoding is well suited to this approximation method. In terms of error propagation, ambiguous results are observed, as shown in Figure 4. For 5-bit integer quantization, the BER performance does not improve over the 4-bit level at ${\mathit{E}}_{\mathrm{b}}/{\mathit{N}}_0$ values below 6 dB for QMS-SC decoding, even though their FERs are identical. This suggests that, while increasing the quantization level improves the accuracy in certain scenarios, it may not significantly enhance BER in low ${\mathit{E}}_{\mathrm{b}}/{\mathit{N}}_0$ regimes. However, such low ${\mathit{E}}_{\mathrm{b}}/{\mathit{N}}_0$ regions are not typically utilized, as their BERs are quite poor. The integer-based conventional SC decoding results show that expanding the integer range does not lead to performance improvement because integer values are poorly suited for accurately representing hyperbolic functions in SC decoding. To optimize the quantization level, the 5-bit quantization level is concluded to be optimal for operating the MS-SC decoding in the integer domain. Notably, the performance at low quantization levels, lower than the 5-bit level, closely resembles that of infinite-precision MS-SC decoding as the length and rate of polar codes increase. On fading channels, the performance of QMS-SC does not improve despite increasing the bit level from 5 bits to 8 bits, and it saturates at the 5-bit level, suggesting that increasing bit precision does not result in further performance improvements.

Compared to the results of [26], which employed fixed-point quantization, our all-integer quantization approach achieves a similar BER/FER performance, as shown in Figure 7. Considering the computational complexity in Table 2, the results of this experiment confirm that our method significantly reduces computational complexity compared to fixed-point operations in FPGA implementation. In comparison, as shown in

Table 4. Comparison of quantization methods.

Method	Quantization Complexity	Decoding Performance
Proposed	Minimal	Satisfactory
Fixed-point [26]	Low	Satisfactory
Nonuniform [9]	High	Excellent

, the fixed-point calculations reported in [26] have low implementation complexity but still result in sufficient decoding performance. On the other hand, as discussed in [9], the nonuniform quantization method introduces higher implementation complexity due to its sophisticated design for optimizing quantization levels. However, it offers a superior decoding performance in specific scenarios, making it more suitable for applications where performance is prioritized over hardware constraints. These comparisons highlight that, while the proposed method offers a good balance of low complexity and adequate performance, higher-performance methods such as the nonuniform approach may be preferred in scenarios where decoding accuracy is paramount and the hardware can support the increased complexity.

Considering computational complexity, the reduction in complexity relative to conventional SC decoding is $75\%$, since integer calculations involve only integer values, in contrast to fixed-point and floating-point calculations that strictly consider fractional parts to achieve high-precision results. This suggests that the all-integer quantization min-sum SC decoding algorithm is highly effective in optimizing the decoding algorithm for polar codes, particularly in resource-constrained environments. Unlike previous studies relying on floating-point arithmetic, our approach demonstrates that integer-based decoding achieves a comparable performance with lower complexity, enabled by the use of a simple quantizer.

To enable SC decoding in practical hardware implementations, efficient computational resources such as FPGAs, CPUs, and Graphics Processing Units (GPUs) play a critical role in devices like IoT systems, mobile communication devices, and massive machine-type communication (mMTC) networks. The simplicity of the all-integer quantization method proposed in this work facilitates faster processing speeds while maintaining an acceptable level of error correction, making it particularly well suited to real-time applications. By striking a balance between high-performance decoding and hardware efficiency, this work bridges the gap between complex decoding algorithms and practical implementation. It offers a promising solution for next-generation communication systems where both performance and resource constraints are key considerations.

7. Conclusions

Quantization plays a crucial role in making polar decoders feasible for real-world applications. Among various quantization techniques, all-integer quantization stands out as a highly efficient approach that significantly reduces computational complexity, making it well suited to hardware-constrained environments. While it is computationally challenging, it eliminates the need for floating-point operations, ensuring faster and more energy-efficient decoding in practical implementations. This study demonstrates that all-integer quantization is particularly effective for MS-SC decoders. Specifically, a 5-bit all-integer quantization closely approximates the performance of infinite-precision decoding while maintaining computational efficiency. Our results confirm that this method remains viable even in fading channels, with a negligible performance gap of 0.2 dB compared to floating-point calculations, making it highly efficient for practical implementation. Additionally, integer-based computations can reduce computational complexity by up to $75\%$, making decoding significantly more efficient. The proposed all-integer quantization method enables substantial reductions in hardware resource requirements, making it particularly valuable for resource-constrained environments. This method is applicable to low-power systems such as IoT devices, wireless sensor networks, and storage systems, where hardware complexity, energy efficiency, and error correction accuracy are prioritized, respectively. By eliminating complex floating-point arithmetic, this approach aligns well with the growing demand for energy-efficient, real-time decoding solutions in modern communication systems. Future research could explore methods to mitigate precision loss, such as nonuniform quantization approaches that combine integer techniques and nonuniform quantization schemes to balance complexity and accuracy. Quantization techniques could also be applied to SC-flip decoding and SCL decoding to further enhance the decoding performance. Additionally, further studies should assess the real-world hardware implementations of this method across various communication systems to ensure robustness and adaptability in diverse practical scenarios.

Overall, the proposed all-integer quantization method for MS-SC decoding offers a promising balance between performance and hardware efficiency. As communication systems continue to evolve, this approach presents a compelling solution to meet the increasing demand for low-latency and energy-efficient decoding methods in next-generation networks.