A 300 mV Josephson Arbitrary Waveform Synthesizer Chip at NIM ^†

Abstract

This paper describes the status of developing Josephson arbitrary waveform synthesizer (JAWS) chips at NIM (National Institute of Metrology, China). To obtain high junction integration density and fewer data input channels, the chip employs an on-chip Wilkinson power divider and inside/outside dc blocks, enabling both arrays to be driven by a single pulse-generator channel. In addition, the tapered coplanar waveguide structure is used to ensure the microwave uniformity of the long-junction array. Each array consisted of 4000 double-stack Nb/Nb_xSi_1−x/Nb junctions, and 16,000 junctions are integrated in the chip in total. The JAWS chip demonstrates good performance, capable of synthesizing a 300 mV root mean square (rms) voltage with exceptionally low harmonic distortion. Dc and ac voltage-current characteristics measurements indicate that the junctions are with a critical current of 2.5 mA, and a normal-state resistance of 4.5 mΩ per junction. Contact aligners are manually operated to fabricate the chips, and process errors in the fabrication are estimated in this paper.

1. Introduction

Since the discovery of the Josephson effect [1] and its application in electrical metrology, the Josephson voltage standards (JVSs) have brought a dramatic improvement in the accuracy of primary dc voltage references [2,3,4]. The first generation JVSs are conventional Josephson voltage standards (CJVSs) with series-connected superconductor–insulator–superconductor (SIS) Josephson junction (JJ) arrays. The SIS junctions have hysteretic dc I-V characteristics and zero-current crossing steps under radio frequency microwave irradiation. Although the CJVSs have the disadvantages of the step number not being able to be quickly set and the spontaneous step transition problems caused by noise, they are still widely used as primary voltage standards by many national metrology institutes.

As for ac voltage references, programmable Josephson voltage standards (PJVSs) [5,6,7,8,9,10] and the Josephson arbitrary waveform synthesizer (JAWS) [11,12,13,14,15,16,17] have been developed for different applications. The junctions in both types are designed to be non-hysteretic, that is, the junction voltage is a single-valued function of the biased current. The physical principle of the PJVS is that the combination of a dc and a radio frequency ac current f drives N flux quanta Φ₀ (N is the step number) through the M junctions (M is the junction number) in a JJ array. The flux quanta is Φ₀ = h/2e, in which h is the Planck constant and e is elementary charge. The PJVS has the advantage of rapid settling time and inherent step stability, which make it superior to the CJVS for dc measurements. In ac waveform synthesizing application, PJVS obtains the ac output voltage by biasing different segments of the JJ array with different dc bias currents. It has the advantage of higher output voltage over 10 V compared with JAWS, but with a limited stepwise approximated waveform frequency up to few kilohertz containing higher harmonics due to the unpredictable transients between steps and limitations from the sampler. To overcome the above limitation, a sub-sampling technique was developed [18].

As a complementary type, the Josephson arbitrary waveform synthesizer (JAWS) was invented to solve the problem of undefined voltage during transitions between steps by biasing the array with pulses. In PJVSs, the way to program the voltage of a JJ array is to change the junction number M. The same result could be achieved by changing pulse repetition frequency f_p(t). In JAWS, the JJ array is employed as a quantum accurate sigma–delta digital-to-analog converter, and each pulse from the pulse generator drives the JJ array to generate a quantized voltage’s time integral which is exactly equal to M times flux quanta Φ₀. In this way the synthesis ac waveforms are with a computable rms value. Although the JAWS produces a lower output voltage compared to the PJVS (2 V per chip at most with two pulse inputs), it has the capability of synthesizing waveforms from a few hertz up to megahertz with extremely high spectral purity. The JAWS circuit requires uniformly arranged, elongated arrays of JJs to generate an effective voltage. Like in the PJVS chips, self-shunted and non-hysteretic JJs are required in JAWS chips to provide stable arbitrary dc voltage and ac waveform with a computable rms voltage. The National Institute of Standards and Technology (NIST) has fabricated two-volt JAWS chips, which have 8 JJ arrays and 102,480 JJs [16]. Physikalisch-Technische Bundesanstalt (PTB) added signals from 16 JJ arrays to synthesize a waveform of 2.25 V. These JJ arrays are distributed on 8 chips, containing in total 162,000 JJs [17]. PTB also demonstrated an optical pulse-drive JAWS recently [19]. Both NIST and PTB use advanced automated lithography tools such as stepper and e-beam lithography to fabricate JVS chips. Contact aligners are used at NIM, and they can cause more defects and a larger mismatch of the patterns. NIM has been working on JVS chips based onNbxSi_1−x barrier technology since 2011. This paper describes the current status of developing Josephson arbitrary waveform synthesizer (JAWS) chips at NIM, and it is an extended version of our abstract from CPEM 2024 [20].

2. Chip Design

As for one JJ only produces a flux quanta with a very small voltage by each pulse’s drive, tens of thousands of JJs are connected in series to achieve a practical and useable output voltage. The NIM JAWS chip has two JJ arrays, and each consist of 4000 double-stack Nb/Nb_xSi_1−x/Nb junctions embedded in the central line of a coplanar waveguide (CPW). The stacked junctions technology has been used to increase the integration density of junctions and improve pulse dispersion and coupling between the junctions. Double- and triple-stacked JJ arrays have been widely employed in both the PJVS and JAWS chips. More sophisticatedly, the process for the fabrication of JAWS chips consisting of up to five-stacked JJ arrays was successfully developed at PTB [21].

The schematic and microscope graph of the JAWS chip are shown in Figure 1. An on-chip broadband one-to-two Wilkinson power divider is employed so that the two JJ arrays can be driven by one arbitrary waveform generator channel. Inside–outside dc blocks are used between Wilkinson power divider outputs and JJ array inputs so that the synthesized waveforms of the two JJ arrays can be summed in series. There are in total 16,000 junctions in serial connection, providing the 300 mV rms output magnitude. The JAWS chip is 5 mm wide and 30 mm in length, and no “U-turn” is used in the CPW. A termination resistor is designed to match the impedance of CPW at the end to prevent reflections of the high-speed pulses. In the JAWS chips, the driving pulses are distributed in a wide frequency range, and the synthesized signals are in audio frequency. Therefore, on-chip superconducting low-pass filters are applicated to isolate the low-frequency output signals from the high-frequency driving signals, which is represented by “LPF” in Figure 1a. Four leads are used for each array: two for voltage output wires and two for compensating bias wires.

Nb_xSi_1−x is chosen for the barrier layer in the NIM JAWS chip to achieve non-hysteresis I-V characteristics. However, the Nb_xSi_1−x barrier is dissipative, and for a transmission line with a characteristic impedance of 50 Ω the number of JJs that generally can be integrated in an array is less than 15,000. Therefore, it is necessary to drive multiple series-connected multiple arrays. Early circuit designs [22,23,24,25] did not adopt an on-chip microwave power distribution scheme. Instead, each JJ array was directly connected to the pulse-generator output channel with high-frequency semi-rigid cables and connectors. This simplest configuration has the lowest microwave loss and reflections, and it allowed for the optimization of bias parameters for each array’s characteristics. However, it came with high system costs for the expensive AWGs channels. Furthermore, the large number of cables increased system complexity and brought cooling challenges for the cryogenic environment. The later NIST JAWS chips adopted the one-to-two Wilkinson power dividers used in PJVS circuits, so each pulse-generator channel can drive two JJ arrays for one-layer Wilkinson dividers and four arrays for two layers [7,26]. At PTB, several kinds of modified CPW-CPS dividers were investigated and integrated into their JAWS chips [27,28,29]. One practical divider splits the one AWG channel into two chains to drive two JJ arrays (18,000 JJs). In the NIM JAWS chip, an on-chip broadband one-to-two Wilkinson power divider is employed. Instead of a single-frequency sine wave bias, the pulses in the JAWS typically contain significant power from 1 GHz to >30 GHz [30] and the JJs are sensitive to the non-linear responses of power dividers. So, the power dividers used in JAWS chips should be broadband to ensure the chips can operate properly. The effective working bandwidth of the power divider is a key factor affecting the amplitude of the output voltage of the array. In addition to considering the performance of the power divider in the design, it is also necessary to make it as compact as possible to reduce its space occupation on the chip: this is reason for us choosing the Wilkinson power divider. Due to the narrow operating frequency band of Wilkinson power dividers, impedance transformers are often used to expand the operating bandwidth. The λ/4 impedance converter can achieve impedance transformation and is an important component of the Wilkinson power divider. Among them, adding an additional stage of the λ/4 wavelength transformer at the input port can achieve a more ideal effective bandwidth extension. Power dividers are often implemented through coplanar waveguides or strip lines, so they are still relatively large in size. A π-type LC circuit with lumped parameters is used to equivalently convert the λ/4 converter section. Although this equivalence only achieves complete equivalence with the λ/4 converter at the center frequency, it can achieve approximate equivalence within a certain bandwidth range. The broadband Wilkinson power divider used in the 300 mV JAWS chip is shown in Figure 2, where each λ/4 converter is equivalently replaced by an inductor and two capacitors. Simulation and preliminary measurement results of our power divider can be seen in [31]. This structure is similar to that used by NIST [5].

Experimental research has been pursued with a variety of junction technologies, including SIS junctions, superconductor–insulator–normal metal–insulator–superconductor (SINIS) junctions, and superconductor–normal metal–superconductor (SNS) junctions. For the superconducting layers of the JJs in JVS applications, Nb is typically used at 4.2 K, and NbN at 10 K, respectively. High-temperature superconductors with grain boundary junctions also have potential for JVS application at the temperature of liquid nitrogen [32]. Several technologies have been employed as barrier layers for the JJs in JVS. SIS-type Nb/Al-AlO_x/Nb JJs [33] were used in the early CJVS, which have zero-current crossing steps. For later PJVS and JAWS applications, the SINIS- and SNS [34]-type JJs with non-hysteric I-V characteristics are desirable to achieve intrinsic stability and rapid programmability. The SINIS junctions successfully developed by PTB consisted of a multilayer structure of Nb/AlO_x/Al/AlO_x/Nb, and they were employed in fabricating their 10 V PJVS chip [35]. For SNS junctions, different materials like PdAu [36], HfTi [37], MoSi₂ [38], and Ti [39] have been investigated as barrier layers for Nb-based junctions. The National Metrology Institute of Japan (NMIJ) of the National Institute of Advanced Industrial Science and Technology (AIST) has developed junction technology based on NbN/TiN_x/NbN materials and successfully fabricated PJVS devices to reach a voltage of at least 10 V [40]. However, the fabrication of NbN-based junctions is more complex, as it requires epitaxial growth. NIST developed a new barrier layer for Nb-based SNS junctions, which is realized by amorphous Si doped with Nb [41] and shows superior properties. The Nb_xSi_1−x is co-sputtered by two separate targets. The advantage of this barrier layer is that the Nb content could be adjusted by tuning the sputtering power. In this way, the junction characteristic parameters such as critical current I_c and characteristic voltage I_cR_N are adjustable over a wide range. The Nb_xSi_1−x barrier SNS junction also showed excellent process compatibility in the deposition and etching with the Nb-based superconductor chip fabrication processes. For this reason, it has been typically used in both PJVS and JAWS chips at present at NIST, PTB, and NIM [41,42,43].

The JAWS chip structure and processes are designed based on the Nb_xSi_1−x barrier layer SNS JJs technology. The fact that should be considered is the dissipative Nb_xSi_1−x barrier, so the microwave power gradually decays along the array. As illustrated in Figure 3a, for the traditional CPW structure this results in a significant uniformity problem for the microwave current received by the JJs in the array, which can cause differences in their ac working status, ultimately significantly reducing the quantum locking region (QLR) for the array when all the JJs are working simultaneously. In order to ensure that the JJ array has sufficient current margin, it is necessary to make the bias pulse current of each junction remain the same. Dresselhaus et al. adopted a tapered coplanar waveguide structure with gradually decreasing characteristic impedance to compensate for the microwave dissipation in SNS JJ arrays [44]. By gradually varying the physical dimensions of the coplanar waveguide, impedance transformation is achieved to maintain a constant microwave drive current. Josephson junctions are current-driven devices. Although the microwave power decreases along the array due to junction dissipation, the attenuation in power can be compensated by continuously and smoothly reducing the characteristic impedance of the transmission line, thereby keeping the microwave current through each junction essentially consistent, as shown in Figure 3b. By adopting this tapered coplanar waveguide design, not only can the current margin be improved, but also the maximum number of JJs in an array can be increased. In the NIM JAWS chip, this technology is also applied and the impedance CPW is design to be tapered from 50 Ω to 30 Ω in a linear way.

3. Device Fabrication

Double stacks of Nb/Nb_xSi_1−x/Nb multilayers are deposited without breaking the vacuum on oxidized silicon wafers using a Lesker CMS-18 sputter system (Kurt J. Lesker Company, Jefferson Hills, PA, USA). The Nb_xSi_1−x barrier layers are deposited by co-sputter technique [14,15], with a sputtering power of 39 W for Nb and 210 W for amorphous Si, and a duration of 340 s. Nb_xSi_1−x is one of the preferred choices for normal metal barrier materials because it allows for a large tuning range of junction properties by adjusting both the barrier’s stoich and thickness. The JJs and BEs are defined and etched by reactive ion etching (RIE) using fluorine-based dry etching processes. The JJ stacks should be etched with a vertical etching profile to ensure the upper and lower junctions in the stack have the same area to obtain uniform junction critical currents. The etching processes are performed using a mixture of SF₆ and C₄F₈. C₄F₈ was used to form sidewall-protection films. On the contrary, a mixture of CF₄ and O₂ is used as the etching gas to obtain a sloped etch profile for the BE layer. The oxidized layer on the silicon wafer could be used as the etch stop layer in this step. A 360 nm SiO₂ insulation layer was deposited by inductively coupled plasma chemical vapor deposition (ICP-CVD) at 80 °C. Connection vias are defined and dry etched with a sloped profile by a mixture of CHF₃ and O₂. Then the Nb wiring layer was sputtered, defined, and dry etched with a sloped profile. Finally, a 120 nm PdAu resistor layer was deposited and lifted-off.

In PTB’s process for five-stacked JJ arrays, a thin SiO₂ layer deposited by atomic layer deposition (ALD) was added before the ordinary plasma-enhanced chemical vapor deposition (PECVD) SiO₂ process to ensure perfect sidewall coverage over the thick junction stacks. Also, a chemical–mechanical polishing (CPM) process of the SiO₂ layer was introduced in their process to obtain a smoother surface before deposition of the later Nb wiring layer. In our case, the double-stacked JJs only had vertical steps of less than 600 nm, so the ALD and CMP processes were not employed.

Both NIST and PTB use advanced automated lithography tools such as stepper and e-beam lithography to fabricate Josephson voltage standard (JVS) chips. Contact aligners are manually operated at NIM, and it can cause slightly more mismatch of the patterns at different positions and layers. Since the alignment tolerance is 0.75 μm, it should be performed very carefully to ensure alignment. However, it is still possible for us to fabricate JAWS chips with ten thousand JJs. The fabrication errors are analyzed in Figure 4a,b.

In the design of the JVS chips, the JJs are integrated on the center signal line of the traditional coplanar waveguide. The center line’s width W and gap’s width G are the key factors to determine the characteristic impedance when the dielectric material and its thickness are fixed.

In the chip fabrication, any of the alignment, exposure, development, or etching can result in process errors. ∆_BE is the size error for the BE layer, ∆_WR is the size error for the WR layer, and δ is the lateral alignment error between BE and WR. The size errors △ of each layer preparation are caused by exposure, development, and etching processes during fabrication, and the interlayer alignment errors δ originate from the random differences in the accuracy of the BE and WR layer alignment. These random errors result in differences between the actual structure of the waveguide and the ideal structure, and we assume that these errors can be linearly superimposed. For the beginning of the CPW, the centerline width W₀ is 15 μm and the gap width G₀ is 10 μm, respectively.

To avoid confusion, it is necessary to specify the sign conventions for ∆ and δ. The sign of ∆ is determined relative to the designed centerline width W₀: if the actual centerline width W < W₀, then ∆ < 0; if W > W₀, then ∆ > 0. δ is always positive because the reference structure is axisymmetric. Therefore, the characteristic impedance shift is independent of the misalignment direction between the WR layer and the BE layer.

The designed and SEM-measured CPW size parameters and the calculated characteristic impedances based on them are shown in

Table 1. The designed and measured CPW size parameters, and the calculated Z₀.

	Centerline BE Width	Centerline WR Width	Gap Width	δ	Calculated Z0
Designed	15.00 μm	15.00 μm	10.00 μm	-	51.4 Ω
Measured	14.40 μm	13.85 μm	11.14 μm	0.185 μm	53.6 Ω

. Figure 5 shows the SEM image of the beginning of CPW. The measured BE and WR widths in the central line are 14.40 μm and 13.85 μm, respectively. ∆_BE = −0.60 μm and ∆_WR = −1.15 μm could be obtained. G₁ = 11.14 μm and G₂ = 11.01 μm are the airgaps from the WR and BE to the upper ground, respectively, while G₃ = 11.17 μm and G₄ = 10.67 μm are the airgaps from the WR and BE to the lower ground, respectively. The interlayer alignment error δ can be calculated as ${\displaystyle \frac{1}{2}}\left|(G_1-G_2)-(G_3-G_4)\right|$ after analysis. The interlayer alignment error δ = 0.185 μm was obtained.

The characteristic impedance Z₀ at 15 GHz was calculated by AppCAD (Version 4.0.0) [45] by ignoring the small alignment error δ for a substrate thickness of 500 μm. As shown in Table 1, the characteristic impedance at the beginning of the CPW was designed to be 51.4 Ω, and the fabrication errors caused a 2.2 Ω impedance deviation. The tendency was same at the end of CPW.

4. Measurement Results and Discussion

The chip is measured in a liquid helium dewar at 4.2 K. The dc and ac I-V curves of the arrays in the chip were measured. The critical current I_c is 2.5 mA, and the normal resistance R_n of each junction is 4.5 mΩ. Characteristic voltage V_c = I_cR_n = 11.3 μV. To demonstrate the JJ arrays response broadbands, ac I-V curves were measured while sweeping the microwave drive from 1 to 25 GHz to observe the frequency dependence of the first-order Shapiro step versus microwave frequency. The value of dV/dI is introduced and plotted as a function of frequency. The I-V curves at all frequencies are integrated together, as shown in Figure 6. During the measurements the microwave power was adjusted to keep the zero-order Shapiro step constant at 1.5 mA. Due to the value of dV/dI at the voltage step being 0, it is shown in white in the distribution map. The white area on the lower side of the figure is the zero-order step. A broad first Shapiro step is visible for all frequencies from 1 to 25 GHz. This is also proof of the good performance of the broadband Wilkinson power divider, as well as of tapered CPW.

Then, we synthesized a 10 kHz and 300 mV rms sinusoidal signal using the chip. A sinusoidal wave with a frequency of 10 kHz and 150 mV (for 8000 junctions operating in a single array) is encoded using the second-order delta–sigma modulation technique as a binary pulse pattern with a length of M = −1,440,000 bits and a sampling frequency of f_s = 14.4 GHz. The repetition frequency of the waveform is f_s/M = 10 kHz. The fast pulses are provided by an arbitrary waveform generator (Keysight M8195A) with a rate of 14.4 × 10⁹ pulses/s.

The quantized voltage spectrums of a 150 mV rms sinusoidal signal synthesized by Array 1, Array 2, and the two arrays are shown in Figure 7, respectively. All spectra were recorded using a NI PXI-5922 (National Instruments (NI), Austin, TX, USA). In the measurements, the output voltage distortions are very low, with harmonic components below −106 dBc. The distortion harmonics in Figure 7 are caused by nonlinearity in the NI PXI-5922 digitizer [46]. The QLR of operating current could be estimated to be more than 0.5 mA, as shown in Figure 8. NIST’s 2 V JAWS chips are composed of two data inputs, and each input has four JJ arrays connected to two stages of power dividers. Each array has 12,800 JJs and has an output of 250 mV. To improve our chip’s output, we should increase the current operating margin (Quantum Locking Range, QLR). The QLR is not good enough for our current CPW design when integrating 12,000 JJs in an array, due to the nonuniform pulse intensity caused by dissipation of the normal metal barrier of SNS junctions. The electrical characteristics of JJs should be optimized. To use more stages of power dividers in each data input, on the one hand the power divider should be broadband, and on the other hand the QLR also should be improved as it will be reduced by 50% by adding another divider stage.

5. Conclusions

This article presents the JAWS chip developed at NIM. The chip integrates 16,000 Nb_xSi_1−x junctions in series, and all the junctions are working properly. A one-stage broadband one-to-two Wilkinson on-chip power divider was used to distribute the input pulse power to two JJ arrays, and it was also in good function. The chip is used to synthesize a 10 kHz and 300 mV rms sinusoidal signal. The output signals had low distortion, and the harmonics were 106 dB below the fundamental. In the future, we will improve JAWS chips in two directions: One is to develop the technology to vertically integrate more junctions. While the current chip utilizes a double-stack junction structure, future work will focus on fabricating triple-stacks and even higher-layer junction stacks. This approach increases the junction density in unit chip area, thereby directly enhancing the output voltage of a single array without significantly altering the existing planar layout. A self-aligned dielectric planarization method with in-situ monitoring for multi-junction stacks has been investigated to improve subsequent coverage of Nb superconducting interconnections. The second is to adopt multi-stage power divider networks. Plans are underway to upgrade the current single-stage power divider to two or more stage configurations, enabling the integration of four or more parallel arrays into a single channel. JAWS chips with one to three power dividers are also under development. By driving more channels and more arrays simultaneously per channel, the synthesized voltage is expected to reach a higher level. In order to make the chip more compact, broadband “U-turns” will be employed in the next step.