An Asymmetric SiC Power Module Directly Integrated with Vapor Chamber for Thermal Balancing in MMC

Featured Application

The asymmetric silicon carbide (SiC) power module directly integrated with vapor chamber (VC) can be applied to the modular multilevel converter (MMC) for thermal balancing inside the submodules (SMs). The chips of the lower side of the half bridge (HB) SM are soldered onto a VC which is added on direct bonding copper (DBC). The proposed structure can significantly reduce the hotspot temperature, maximum temperature difference and low-frequency temperature swing of the chips, thus the local over-temperature and thermal imbalance module inside the SM of SiC-MMC can be well solved.

Abstract

Power modules in silicon carbide (SiC)-based modular multilevel converters (MMCs) suffer from notably severe thermal imbalance and localized overheating. This paper puts forward an asymmetric SiC power module with direct integration of a vapor chamber (VC), designed to balance the thermal distribution inside MMC SMs. Specifically, the chips on the lower side of the HBSM are soldered onto a VC, which is additionally mounted on the direct bonding copper (DBC). Endowed with merits such as favorable temperature uniformity, exceptional thermal conductivity, compact size, flexible design, high integration level, and reasonable cost, the VC serves as an outstanding heat diffuser significantly expanding the effective thermal conduction area and reducing thermal resistance. Moreover, in this structure, the VC also functions as a conductor for device current. Finite element method (FEM) simulation results reveal that the proposed structure can notably reduce the hotspot temperature (from 109 $°\mathrm{C}$ to 71.8 $°\mathrm{C}$), the maximum temperature difference among chips (from 45 $°\mathrm{C}$ to 13.89 $°\mathrm{C}$), and the low-frequency temperature swing (TSL) (from 68 $°\mathrm{C}$ to 38 $°\mathrm{C}$). Consequently, the issues of localized overheating and thermal imbalance in SiC-MMC SMs are effectively addressed. Lifetime analysis further indicates that the proposed structure can reduce the annual damage rate of the chip solder layer by 92.6%.

1. Introduction

Currently, modular multilevel converters (MMCs) have emerged as one of the most appealing converters in high-voltage direct current (HVDC) transmission systems [1], high-power motor drive systems [2], and static synchronous compensators (STATCOMs) [3], thanks to their advantages of high modularity, good scalability, high efficiency, and excellent waveform quality [4,5].

Traditionally, silicon (Si)-based insulated gate bipolar transistors (IGBTs) are widely adopted in MMCs. However, the performance of such converters is constrained by the inherent theoretical limits of Si devices. As a wide bandgap (WBG) semiconductor, SiC devices exhibit superior performance compared to Si devices, including higher voltage ratings, higher operating temperatures, faster switching speeds, and lower switching losses [6]. Owing to these advantages over Si IGBTs, SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) hold great potential for advancing the performance of state-of-the-art MMCs and have garnered significant attention in recent years [7]. First, the use of SiC MOSFETs can drastically reduce switching losses, thereby improving system efficiency [8]. Second, high-voltage SiC MOSFETs enable a reduction in the number of SMs, simplifying system complexity [8]. A prototype of a SiC-based MMC for medium-voltage electric machine drives has been developed in [9], and several other studies have explored issues related to SiC-MMCs, such as electromagnetic interference (EMI) reduction [8], modulation schemes [7,10], and power loss analysis [4,5]. Nevertheless, very few studies concentrate on the device-level reliability of SiC-MMCs.

As noted in [11], when the MMC system operates at a high-power factor, the power loss distribution across power modules becomes severely unbalanced due to the inherent DC bias in arm currents. Specifically, the chips on the lower side of the HB module experience much higher heat flux and form hotspots with the highest TSL, which seriously threaten the reliability of the entire module [11]. Furthermore, as shown in Figure 1 [12], the chip size of SiC MOSFETs is significantly smaller than that of Si IGBTs with the same voltage and current ratings. According to [13], the heat flux of WBG dies can reach up to 1 kW/cm². Therefore, when SiC-MMCs operate at high-power factors, the hotspots will exhibit extremely high heat flux. If the thermal resistance of the power module is not sufficiently low, the hotspot temperature will rise even more sharply, easily triggering thermal runaway. Although SiC MOSFETs can operate at high temperatures (typically above 200 °C), power modules with conventional packaging structures (shown in Figure 2) fail to withstand such high temperatures, as the solder layers and bond wires are prone to failure. In addition, the small size of SiC dies results in lower thermal capacitance, leading to more significant junction temperature swings. Finally, SiC is stiffer and has a much higher Young’s modulus than Si. A higher Young’s modulus causes significantly greater thermomechanical stress, more accumulated creep strain, and concentrated creep energy in the die-attached solder under the same junction temperature [14]. Thus, it is essential to resolve the issues of excessively high hotspot temperatures, large TSL, and severe thermal distribution imbalance in SiC-MMC power modules.

Numerous studies have focused on lifetime prediction for MMCs [15,16,17,18,19,20,21,22,23,24,25,26]. However, only a limited number of studies have addressed the alleviation of localized overheating and thermal imbalance in MMCs to extend their service life. In [27], an active thermal control (ATC) strategy is proposed to balance the thermal distribution in hybrid MMCs. In [28,29,30,31], device-level power loss balancing control strategies for MMCs are presented. Reference [32] argues that circulating currents affect the loss distribution of power devices and can thus be used as a control variable to indirectly regulate device temperatures. In [33,34], thermal optimization strategies for MMCs based on second-order harmonic circulating currents are proposed. In general, the uneven loss distribution in MMCs is inherent to their circuit topology. Since the DC bias in arm currents cannot be eliminated, the effectiveness of control algorithms in addressing this issue is rather limited.

Some studies have also attempted to reduce the TSL of devices in power converters. References [35,36] reduce TSL by optimizing switching losses. However, this approach is not suitable for MMCs, as switching losses account for only a small portion of the total losses in MMCs. Furthermore, in [32], the reduction in TSL is achieved at the cost of increased average junction temperature and fundamental-frequency junction temperature swing. Adaptive cooling systems proposed in [37,38,39,40] add considerable complexity and energy consumption to external cooling systems.

Therefore, optimizing the mechanical design of power modules is considered a more feasible solution to the thermal imbalance in MMCs. In [41], an air-cooled heatsink with embedded O-shaped heat pipes is designed to reduce the hotspot temperature of IGBT modules in MMCs. However, this design fails to reduce the temperature difference among chips, as the heat pipes are not integrated inside the power modules. Reference [18] indicates that using chips with higher current ratings can reduce the thermal stress on hotspots and extend their lifetime. Nevertheless, chips with higher current ratings are more costly, and excessively increasing the chip current rating is impractical given the strict size constraints of power modules. Hence, a more feasible, effective, and low-cost mechanical structure for power modules is required.

Benefiting from merits such as exceptional thermal conductivity, favorable temperature uniformity, compact size, flexible design, high integration level, and reasonable cost, VCs are ideal thermal conduction components for power modules with high local heat flux. References [42,43,44] propose replacing the copper baseplate of power modules with VCs. However, due to the considerable distance between the VC and the chip, as well as the presence of a high-thermal-resistance DBC ceramic layer in between, the reduction in the thermal resistance of the power module is not significant.

This paper proposes an asymmetric power module structure with direct vapor chamber integration, which effectively mitigates the critical challenges of localized hotspot overheating and thermal imbalance in SiC-based MMCs, thereby significantly enhancing device-level reliability and offering a robust hardware solution for high-performance power conversion systems. The remainder of this paper is organized as follows: Section 2 briefly introduces the principle of uneven loss distribution inside MMC SMs; Section 3 presents the theoretical analysis of heat transfer and the mechanical structure design; Section 4 describes the FEM simulation and lifetime analysis; Section 5 concludes the study.

2. Principle of Uneven Loss Distribution Inside the SMs of MMC

Figure 3 illustrates the schematic diagram of a three-phase SiC-MMC inverter and an HBSM. It is observable that each phase consists of an upper arm and a lower arm, and each arm comprises N HBSMs and a series-connected arm inductor. Each HBSM contains two SiC MOSFETs (S1 and S2), two anti-parallel SiC Schottky diodes (D1 and D2), and a capacitor. S1 and D1 are located on the upper side of the HBSM, while S2 and D2 are on the lower side.

The operating modes of the HBSM are shown in Figure 4 and

Table 1. Operating Modes of HBSM.

Modes	S1	S2	ism	usm
A	0	1	ism > 0	0
B	0	0	ism > 0	uc
C	0	0	ism < 0	0
D	1	0	ism < 0	uc

. The HBSM operates in two distinct switching states. During the inserted mode (states B and D in Figure 4), the upper switch is turned on while the lower switch is turned off, allowing current to flow through the submodule capacitor and enabling the submodule to output the capacitor voltage. Conversely, in the bypassed mode (states A and C in Figure 4), the lower switch is turned on while the upper switch is turned off, creating an alternative current path where the capacitor is bypassed and the submodule output voltage becomes zero.

The MMC topology and operating modes of the HBSM form the basis for analyzing the uneven power loss distribution that motivates our thermal management approach.

For HBSMs based on MOSFETs, S1 and S2 stay in the off-state in Mode B and Mode C (with a gate-source voltage V_GS = 5 V). When V_GS = −5 V, the body diodes of the MOSFETs have a threshold voltage higher than 2 V (based on their characteristics), making it difficult to turn them on. Consequently, all current flows through the anti-parallel diodes. The reasoning underlying this design is that the equivalent resistance of the body diodes has a negative temperature coefficient, which would lead to severely uneven current distribution. Additionally, the conduction of body diodes complicates the calculation of power losses.

The ac voltage, ac current and upper arm current of phase A can be expressed as:

$$V_{\mathrm{a}}=U_{\mathrm{m}}\sin \omega t$$

(1)

$$i_{\mathrm{a}}=I_{\mathrm{m}}\sin (\omega t-\phi )$$

(2)

$$i_{\mathrm{ap}}={\displaystyle \frac{I_{\mathrm{dc}}}{3}}+{\displaystyle \frac{I_{\mathrm{m}}}{2}}\sin (\omega t-\phi )$$

(3)

$$\tan \phi ={\displaystyle \frac{\omega L_{\mathrm{L}}}{R_{\mathrm{L}}}}$$

(4)

$$U_{\mathrm{m}}=I_{\mathrm{m}}\sqrt{R_{\mathrm{L}}^2+{(\omega L_{\mathrm{L}})}^2}$$

(5)

where $U_{\mathrm{m}}$ denotes the peak value of the ac voltage, $I_{\mathrm{m}}$ is the peak value of the ac current, $\omega$ is the angular frequency, $\phi$ is the phase-shift angle, $I_{\mathrm{d}\mathrm{c}}$ is the dc current, L_L is the load inductance and R_L is the load resistance. The arm current comprises a fundamental-frequency sinusoidal component and a DC bias. Since the circulating current suppression strategies can be applied in MMC systems, the even-order harmonics circulating current is neglected.

When the power loss is ignored, the DC-side power equals the active power on the AC side, expressed as:

$$U_{\mathrm{dc}}{I}_{\mathrm{dc}}=3{\displaystyle \frac{U_{\mathrm{m}}}{\sqrt{2}}}{\displaystyle \frac{I_{\mathrm{m}}}{\sqrt{2}}}\cos \phi$$

(6)

where $U_{\mathrm{d}\mathrm{c}}$ is the DC side voltage. Furthermore, the modulation index can be written as:

$$m={\displaystyle \frac{U_{\mathrm{m}}}{0.5U_{\mathrm{dc}}}}$$

(7)

Substituting Equations (6) and (7) into Equation (3), the upper arm current of phase A is:

$$i_{\mathrm{ap}}={\displaystyle \frac{m{I}_{\mathrm{m}}\cos \phi }{4}}+{\displaystyle \frac{I_{\mathrm{m}}}{2}}\sin (\omega t-\phi )$$

(8)

As shown in Figure 5, the arm current has zero crossing points. When $i_{\mathrm{a}\mathrm{p}}$ is positive, the current flows alternately through S₂ and D₁. And when $i_{\mathrm{a}\mathrm{p}}$ is negative, the current flows through $D_2$ and $S_1$. The duration of current flow through each device can be expressed as:

$$\left\{\begin{array}{l}{t}_{\mathrm{cd}1}=t_1-t_0={\displaystyle \frac{\pi +2\alpha }{\omega }}{, \mathrm{for} \mathrm{S}}_2{ \mathrm{and} \mathrm{D}}_1\\ t_{\mathrm{cd}2}=t_2-t_1={\displaystyle \frac{\pi -2\alpha }{\omega }}{, \mathrm{for} \mathrm{S}}_1{ \mathrm{and} \mathrm{D}}_2\end{array}\right.$$

(9)

$$\alpha =\arcsin ({\displaystyle \frac{m\cos \phi }{2}})$$

(10)

Unlike traction inverters, the current duration of S2 and D1 is longer than that of S1 and D2, due to the inherent DC bias in the arm current. As a result, power losses are distributed unevenly across devices, and some devices may form hotspots. According to Equation (10), thermal imbalance worsens as the power factor and modulation index increase. As most grid-connected loads are motors, taking an MMC-based high-power motor drive system as an example, thermal imbalance becomes much more severe because both cos $\phi$ and m are typically around 0.9. Moreover, if SiC power modules are used in such MMC systems, the smaller size of SiC dies will further increase the hotspot temperature. Therefore, there is an urgent need to develop a new mechanical structure for SiC-MMC power modules.

3. Theoretical Analysis of Heat Transfer and Mechanical Structural Design

3.1. Theoretical Analysis of Heat Transfer

Benefiting from merits such as exceptional thermal conductivity, favorable temperature uniformity, compact size, flexible design, high integration level, and reasonable cost, VCs are ideal thermal conduction components for power modules with high local heat flux. As shown in Figure 6, a VC consists of a metal shell with a capillary wick structure on its inner wall, and a vacuum-sealed vapor core inside. The working fluid in the vapor core absorbs heat from heat sources and vaporizes. When the vapor comes into contact with a cooler wall surface, it releases latent heat and condenses. The condensed working fluid then flows back to the heat sources via capillary force and vaporizes again. This cycle spreads concentrated heat over a much larger area, significantly expanding the effective thermal conduction area. Notably, the VC operates without requiring additional energy input. Copper columns connect the upper and lower plates of the VC, reinforcing the metal shell to withstand pressure changes in the vapor.

Existing research explores the use of VCs as a replacement for the copper baseplate in conventional packaging structures (shown in Figure 7). In practice, this structure only marginally improves cooling performance. The primary reason is that the VC is positioned beneath the DBC layer. Heat must first pass through the DBC before reaching the VC, preventing the VC from optimizing the heat flux distribution within the DBC layer. Additionally, the ceramic material in the DBC has inherently low thermal conductivity, resulting in a small effective heat transfer area for the ceramic layer. The thermal resistance can be expressed as

$$R_{\mathrm{th}}={\displaystyle \int \frac{\mathrm{d}z}{kA(z)}}$$

(11)

where k is the thermal conductivity, A(z) is the effective heat transfer area. Therefore, a small heat transfer area results in an increase in thermal resistance.

Therefore, this paper proposes a new mechanical structure (shown in Figure 8) where the VC is relocated upward. Specifically, the chip is directly soldered onto the VC, which is then soldered onto the DBC. This design aims to rapidly spread the heat generated by the chip over a larger area at an early stage, thereby expanding the effective thermal conduction area of the ceramic layer and reducing its thermal resistance. In this configuration, the VC not only acts as a heat diffuser but also functions similarly to the upper copper layer of the DBC by providing electrical conductivity. Since the VC is made of copper (which has excellent electrical conductivity), this structure is theoretically feasible.

3.2. Mechanical Structural Design of the SiC Power Module

Figure 9 shows the mechanical structure of the power modules. In the proposed structure, the devices on the lower side of the HBSM are directly soldered onto a VC, which is then soldered onto the lower DBC. The parameters of the VC are listed in

Table 2. Parameters of the VC.

Parameters	Value
VC size	60 mm $\times$ 40 mm $\times$ 5 mm
Thickness of the copper shell	1 mm
Thickness of the wick	0.5 mm
Height of the vapor core	2 mm
Working fluid	Water
Working fluid filling weight	1.5 g
Vacuum degree	9.31 Pa (9.19 $\times$ 10−5 atm)

. Figure 10 presents a cross-sectional view of the VC’s internal structure in this study. Copper powder is sintered on the inner wall of the shell to form a wick with a porosity of 70%. The wick inside the upper copper shell (directly below the bottom switches) is thickened to 8 mm to maximize the return of working fluid to the hotspots.

The MOSFET and diode dies used in this study are the PWC020M120 and PWC70D120, respectively, both provided by Alpha Power Solutions (a Hong Kong-based semiconductor manufacturer). The sizes of the MOSFET and diode dies are 4.785 mm × 6.4 mm and 4.92 mm × 4.96 mm, respectively. The sizes of the upper and lower DBCs are 65 mm × 49.29 mm and 65 mm × 55.49 mm, respectively. The copper baseplate has a size of 79 mm × 120 mm. Gate drive PCBs are mounted on the top of the VC or DBC, and bond wires establish electrical connections between the upper surface of the dies and the upper surface of the DBC or gate drive PCBs.

4. Thermal Simulation and Lifetime Analysis

4.1. Three-Dimensional Model of the Power Module

Figure 11 shows the 3D model of the power module used for FEM simulation. The effective thermal conductivities of the wick and vapor core are 50 W/(m·K) and 50,000 W/(m·K), respectively [45]. The properties of the power module’s packaging materials are listed in

Table 3. Power Module Package Material Properties.

Sheet	Materials	Thickness mm	Ther. Conduct W/m·K	Spec. Heat J/kg·K
MOSFET	SiC	0.175	490	690
Diode	SiC	0.11	490	690
Chip solder	Pb40Sn60	0.1	32.7	150
Top copper	Copper	0.3	400	385
Ceramic	Al2O3	0.635	24	30
Bottom Copper	Copper	0.3	400	385
DBC solder	Pb40Sn60	0.3	32.7	150
Baseplate	Copper	3	400	385
TIM	Thermal grease	0.1	5	1000

. The thermal interface material (TIM) is labeled in Figure 2, Figure 7 and Figure 8.

The heatsink is made of aluminum, with its size shown in Figure 11. The fin pitch and thickness are 2.6 mm and 1.75 mm, respectively. The frontal area of the heatsink (120 mm × 120 mm) is designed to match the frontal profile of the fan.

4.2. Mission Profiles of MMC System and Power Devices

To determine the average power loss of the chips, the mission profiles of the devices must first be obtained.

A simulation model of the MMC inverter (shown in Figure 3) was built in MATLAB v2018 Simulink to acquire the device mission profiles. The schematic diagram of the MATLAB–Simulink model is shown in Figure 12. The system parameters are listed in

Table 4. Parameters of MMC Simulation Model.

Symbol	Meaning	Value
SN	System rated apparent power	0.83 MVA
P	System active power	0.75 MW
Udc	DC-link voltage	3 kV
Um	Amplitude of ac side phase voltage	1.35 kV
N	Number of SMs	5
L	Arm inductor	5 mH
RL	Load resistor	2.965 $\Omega$
LL	Load inductor	4.58 mH
C	SM capacitor	4.7 mF
fs	Switching frequency	1 k Hz
f	Fundamental frequency	50 Hz
m	Modulation index	0.9

. The model uses a voltage outer loop controller and a current inner loop controller, with carrier phase-shift pulse width modulation (CPS-PWM) as the modulation scheme.

Figure 13 shows the one-day apparent power profile of the MMC inverter [16]. This curve aligns with typical human activity patterns, confirming the rationality of its design. S_max denotes the apparent power of the MMC inverter under the operating conditions listed in Table 4. Figure 14a shows the device currents of the MMC inverter at S_max. Since the DC voltage and modulation index are constant in this study, the amplitude of the AC voltage is also constant (per Equation (7)). Thus, according to Equation (6), an apparent power of 0.5S_max is achieved by reducing the AC current by 50% (i.e., doubling the load impedance in Table 4). Figure 14b shows the device currents of the MMC inverter at 0.5S_max. Current data from both full-power (S_max) and half-power (0.5S_max) operating conditions were employed to calculate the corresponding power device losses, thereby facilitating subsequent thermal simulations to obtain the junction temperatures under these respective conditions.

4.3. Heat Sources Calculation

This section presents the calculation of the average power loss of the dies, which is used for steady-state FEM thermal simulation in the subsequent section.

As shown in Figure 9, each device in the HB module consists of three parallel dies. The current distribution across the parallel dies is assumed to be uniform, for the following reasons:

(1)

The power module exhibits high symmetry in terms of terminal shape/position and chip layout.

(2)

Reference [46] points out that the positive temperature coefficient of the on-resistance (R_on) of SiC MOSFETs balances the static current across parallel devices.

(3)

Unbalanced dynamic current distribution is more likely to occur in high-switching-frequency applications [46]. However, MMCs operate at relatively low switching frequencies.

(4)

This study focuses on the temperature uniformity of the four devices in the HB module, rather than that of the parallel dies.

(5)

The paralleled chips are from the same production batch.

The average power loss of SiC MOSFET can be expressed as:

$$P=I_{\mathrm{RMS}}^2{R}_{\mathrm{on}}(T_j)+{\displaystyle \frac{{\displaystyle \sum E_{\mathrm{SW}}}}{T}}$$

(12)

where $I_{\mathrm{R}\mathrm{M}\mathrm{S}}$ is the root mean square values of the die current (obtained from MATLAB), $R_{\mathrm{o}\mathrm{n}}\left(T_j\right)$ is the on-resistance of the SiC MOSFET (obtained from the $R_{\mathrm{o}\mathrm{n}}$ − $T_j$ curve in the manufacturer’s datasheet), T is the fundamental period and $E_{\mathrm{s}\mathrm{w}}$ is the switching loss of the SiC MOSFET, expressed as:

$$E_{\mathrm{SW}}=E_{{\mathrm{SW}@\mathrm{T}}_{\mathrm{REF}}}(i){({\displaystyle \frac{U_{\mathrm{SM}}}{U_{\mathrm{DC}@\mathrm{REF}}}})}^{K_1}[1+K_2(T_j-T_{\mathrm{REF}})]$$

(13)

where i is the instantaneous chip current at the start of the turn-off process or the end of the turn-on process (obtained from Figure 14), $U_{\mathrm{D}\mathrm{C}@\mathrm{r}\mathrm{e}\mathrm{f}}$ is the nominal test voltage (600 V, per the datasheet), $U_{\mathrm{S}\mathrm{M}}$ is the SM capacitor voltage (600 V, per Table 4). Since switching losses account for only a small portion of the total losses in SiC-MMCs and the junction temperature has a negligible impact on the switching losses of the PWC020M120, the switching loss calculation can be simplified to:

$$E_{\mathrm{SW}}=E_{\mathrm{SW}@25°\mathrm{C}}(i)$$

(14)

where $E_{sw@25 °C}\left(i\right)$ is obtained from the $E_{\mathrm{o}\mathrm{n}}/E_{\mathrm{o}\mathrm{f}\mathrm{f}}$ − $I_{DS}$ curves in the datasheet. As shown in Figure 14, the maximum instantaneous current of a single diode die is 82 A. According to the forward characteristics of the PWC70D120 at 75 $°\mathrm{C}$, the forward voltage is 1.8 V, lower than the threshold voltage of the body diode (as discussed in Section 2). Thus, the body diodes of the SiC MOSFETs do not conduct under this operating condition. The average power loss of the SiC Schottky diode is expressed as:

$$p_{\mathrm{D}}=\left|I_{\mathrm{AV}}\right|[U_{{\mathrm{cond}@\mathrm{T}}_{\mathrm{REF}}}+K_3(T_j-T_{\mathrm{REF}})]+I_{\mathrm{RMS}}^2[r_{{\mathrm{cond}@\mathrm{T}}_{\mathrm{REF}}}+K_4(T_j-T_{\mathrm{REF}})]$$

(15)

where $I_{\mathrm{a}\mathrm{v}}$ is the average value of the die current (obtained from MATLAB). $U_{\mathrm{c}\mathrm{o}\mathrm{n}\mathrm{d}@T_{ref}}$, $r_{\mathrm{c}\mathrm{o}\mathrm{n}\mathrm{d}@T_{ref}}$, $K_3$ and $K_4$ are the coefficients derived from the forward characteristics of PWC70D120 (listed in

Table 5. Measured Power Loss Coefficients for the SiC Schottky Diode.

Parameters	${\mathit{U}}_{\mathbf{c}\mathbf{o}\mathbf{n}\mathbf{d}@{\mathit{T}}_{\mathit{r}\mathit{e}\mathit{f}}}$ [V]	${\mathit{r}}_{\mathbf{c}\mathbf{o}\mathbf{n}\mathbf{d}@{\mathit{T}}_{\mathit{r}\mathit{e}\mathit{f}}}$ [Ω]	${\mathit{K}}_3$ [1]	${\mathit{K}}_4$ [1]
$\mathrm{V}\mathrm{a}\mathrm{l}\mathrm{u}\mathrm{e}\mathrm{s}$	0.9428	9 × 10−3	−1.39 × 10−3	8.85 × 10−5

). The reverse recovery loss of the SiC Schottky diode is neglected.

4.4. FEM Simulation

A square simulated fan (120 mm × 120 mm) was included in the FEM simulation, with its front aligned with the windward side of the heatsink (and no gap between them). The fan flow rate is 35 CFM, and the ambient temperature is 20 $°\mathrm{C}$. In practical applications, power modules are encapsulated with silica gel for electrical insulation. Thus, the upper surface of the power module is set as adiabatic in the thermal simulation. The chips are treated as heat sources with the calculated average power losses.

The electrothermal coupling effect refers to the significant impact of junction temperature on the on-resistance of SiC MOSFETs and the forward characteristics of SiC Schottky diodes. To ensure accurate simulation results, the influence of junction temperature is considered in power loss calculations. Specifically, power loss calculation and thermal simulation are performed iteratively. The device characteristics used for power loss calculation are continuously corrected based on the calculated junction temperature. The iteration stops when the difference between the calculated junction temperature and the temperature corresponding to the used characteristics is less than 0.5 $°\mathrm{C}$.

Figure 15 shows the average power losses of the dies. The power loss distribution is more unbalanced at S_max than at 0.5S_max. Additionally, the power loss of S2 in the VC-based power module is lower than that in the conventional power module, due to the reduced on-resistance.

Figure 16 shows the temperature contours of the two power modules at S_max. Figure 17 presents the junction temperatures of the dies at S_max. The conventional power module exhibits severe thermal imbalance, with dies S21~S23 forming hotspots (hotspot temperature of 109 $°\mathrm{C}$, much higher than that of other dies) and a maximum temperature difference of 45 $°\mathrm{C}$ across the dies. By adding a VC between the bottom devices and the DBC, the temperature of S21~S23 is reduced to approximately 71.8 $°\mathrm{C}$ (the largest temperature reduction among all devices), achieving localized cooling enhancement. In the VC-based module, the hotspots shift to D11~D13 (hotspot temperature of 73.5 $°\mathrm{C}$, close to that of S21~S23). Furthermore, the junction temperature of D21~D23 is close to that of S11~S13, and the maximum temperature difference across the dies is reduced to 13.89 $°\mathrm{C}$. Thus, the proposed structure achieves thermal balance between the upper and bottom devices in the MMC power module.

Figure 18 shows the thermal distribution of the DBC in the two power modules. The DBC in the conventional power module has a significantly large in-plane temperature gradient, whereas the VC-based power module exhibits a much more uniform temperature distribution on the DBC, confirming that the VC significantly expands the effective thermal conduction area of the DBC.

Figure 19 shows the temperature contours of the two power modules at 0.5S_max, and Figure 20 presents the junction temperatures of the dies at 0.5S_max. The TSL (calculated as the difference between the corresponding data in Figure 17 and Figure 20) is shown in Figure 21. It is evident that the dies S21~S23 in the conventional power module have the largest TSL.

4.5. Lifetime Analysis

The service life of the submodule is paramount, as it directly impacts the maintenance strategy, operational availability, and overall lifecycle cost of the MMC system.

According to [47,48], the temperature cycle with heating time (the period where power losses are generated in the IGBT resulting in a temperature swing) below 1 min has a significant effect on the fatigue of bond wires, while a much longer heating time will be more likely to induce the solder fatigue. And according to [49], thermal cycles with periods larger than 3 h cause much more annual damage (AD) in chip solder than baseplate solder. The period of the TSL in this paper is one day. Hence, the solder lifetime model is used to calculate the AD caused by the TSL. The Coffin-Manson law [50,51,52], which estimates the fatigue life according to plastic strain, is selected in this paper since it is widely accepted and considers the size of the solder layer. The model is given in the following equation:

$$N_f=0.5\cdot {({\displaystyle \frac{L\cdot \Delta \alpha \cdot \Delta T_j}{\gamma \cdot \chi }})}^{-{\displaystyle \frac{1}{c}}}$$

(16)

where N_f is the number of power cycles, L is the diagonal length of the chip solder joint, $∆\alpha$ is the CTE mismatch between the upper and lower plate (12.6$\times {10}^{-6}$ for SiC and Cu, regardless of whether the chip is soldered onto a VC or a DBC substrate, the materials on both sides of the solder joint remain SiC and Cu), $∆T$ is the temperature swing shown in Figure 20, x is the thickness of the solder layer shown in Table 3, c = $-$0.229 is the fatigue exponent and $\gamma$ = 0.606 is the ductility factor of the solder [52]. According to the Miner’s rule [53], the AD can be calculated as

$$AD={\displaystyle \frac{n}{N_f}}$$

(17)

where n is the number of cycles in a year for the same stress. In conventional power modules, the lower-arm MOSFET (S₂₁~S₂₃) experiences the highest junction temperature and TSL, making it the lifetime bottleneck of the power module. Therefore, its AD is the focus of this study, and the calculated results are shown in Figure 22. The maximum annual damage values for the two power module types are 0.0555 and 0.0041, respectively. This demonstrates that employing VC can reduce the maximum annual damage of the chip solder joint by 92.6%, extending the service life of the solder joint by more than tenfold.

5. Conclusions

This paper proposes an asymmetric SiC power module with direct VC integration, designed to balance the thermal distribution inside MMC SMs. The chips on the lower side of the HBSM are soldered onto a VC, which is mounted on the DBC. The VC serves as an excellent heat diffuser, significantly expanding the effective thermal conduction area and reducing thermal resistance. It also conducts device current in this structure. FEM simulation results demonstrate that the proposed structure can notably reduce the hotspot temperature, the maximum temperature difference among chips, and the TSL. The hotspot temperature is reduced from 109 $°\mathrm{C}$ to 71.8 $°\mathrm{C}$, the maximum temperature difference is reduced from 45 $°\mathrm{C}$ to 13.89 $°\mathrm{C}$, and the TSL is reduced from 68 $°\mathrm{C}$ to 38 $°\mathrm{C}$. Thus, the issues of localized overheating and thermal imbalance in SiC-MMC power modules are effectively resolved. Lifetime analysis further demonstrates that the VC can achieve a 92.6% reduction in annual damage to the chip solder joint.